320 lines
11 KiB
C
320 lines
11 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_Emif_defines.h
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//
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// TITLE: #defines used in EMIF examples
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//
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//###########################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_EMIF_DEFINES_H
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#define F2837xD_EMIF_DEFINES_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//
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// Defines
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//
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//
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//cpu1 to cpu2 message for handshaking
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//
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#define CPU1_CPU2_MSG 0x3fd00
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//
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//cpu2_to_cpu1 message ram for handshaking
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//
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#define CPU2_CPU1_MSG 0x3fb00
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#define MSEL_EMIF1_CPU1 0x93A5CE71
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#define MSEL_EMIF1_CPU2 0x93A5CE72
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#define MSEL_DEF_3 0x93A5CE73
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#define MSEL_DEF_0 0x93A5CE70
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#define MSEL_DEF_1 0x93A5CE71
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#define MSEL_DEF_2 0x93A5CE72
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//
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//soft reset bit register
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//
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#define EMIF_SOFT_PRES_REG 0x5D084
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//
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//Device capability/EMIF customization register
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//
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#define EMIF_DEV_DC_REG 0x5D014
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//
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// Values for ASYNC_CSx_CR Registers
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//
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#define EMIF_ASYNC_ASIZE_8 0x0
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#define EMIF_ASYNC_ASIZE_16 0x1
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#define EMIF_ASYNC_ASIZE_32 0x2
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#define EMIF_ASYNC_TA_1 0x0
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#define EMIF_ASYNC_TA_2 0x4
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#define EMIF_ASYNC_TA_3 0x8
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#define EMIF_ASYNC_TA_4 0xC
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#define EMIF_ASYNC_RHOLD_1 0x00
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#define EMIF_ASYNC_RHOLD_2 0x10
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#define EMIF_ASYNC_RHOLD_3 0x20
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#define EMIF_ASYNC_RHOLD_4 0x30
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#define EMIF_ASYNC_RHOLD_5 0x40
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#define EMIF_ASYNC_RHOLD_6 0x50
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#define EMIF_ASYNC_RHOLD_7 0x60
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#define EMIF_ASYNC_RHOLD_8 0x70
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#define EMIF_ASYNC_RSTROBE_1 0x0000
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#define EMIF_ASYNC_RSTROBE_2 0x0080
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#define EMIF_ASYNC_RSTROBE_3 0x0100
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#define EMIF_ASYNC_RSTROBE_4 0x0180
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#define EMIF_ASYNC_RSTROBE_5 0x0200
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#define EMIF_ASYNC_RSTROBE_6 0x0280
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#define EMIF_ASYNC_RSTROBE_7 0x0300
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#define EMIF_ASYNC_RSTROBE_8 0x0380
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#define EMIF_ASYNC_RSTROBE_9 0x0400
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#define EMIF_ASYNC_RSTROBE_10 0x0480
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#define EMIF_ASYNC_RSTROBE_11 0x0500
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#define EMIF_ASYNC_RSTROBE_12 0x0580
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#define EMIF_ASYNC_RSTROBE_13 0x0600
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#define EMIF_ASYNC_RSTROBE_14 0x0680
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#define EMIF_ASYNC_RSTROBE_15 0x0700
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#define EMIF_ASYNC_RSTROBE_16 0x0780
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#define EMIF_ASYNC_RSTROBE_17 0x0800
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#define EMIF_ASYNC_RSTROBE_18 0x0880
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#define EMIF_ASYNC_RSTROBE_19 0x0900
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#define EMIF_ASYNC_RSTROBE_20 0x0980
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#define EMIF_ASYNC_RSTROBE_21 0x0A00
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#define EMIF_ASYNC_RSTROBE_22 0x0A80
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#define EMIF_ASYNC_RSTROBE_23 0x0B00
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#define EMIF_ASYNC_RSTROBE_24 0x0B80
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#define EMIF_ASYNC_RSTROBE_25 0x0C00
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#define EMIF_ASYNC_RSTROBE_26 0x0C80
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#define EMIF_ASYNC_RSTROBE_27 0x0D00
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#define EMIF_ASYNC_RSTROBE_28 0x0D80
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#define EMIF_ASYNC_RSTROBE_29 0x0E00
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#define EMIF_ASYNC_RSTROBE_30 0x0E80
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#define EMIF_ASYNC_RSTROBE_31 0x0F00
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#define EMIF_ASYNC_RSTROBE_32 0x0F80
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#define EMIF_ASYNC_RSTROBE_33 0x1000
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#define EMIF_ASYNC_RSTROBE_34 0x1080
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#define EMIF_ASYNC_RSTROBE_35 0x1100
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#define EMIF_ASYNC_RSTROBE_36 0x1180
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#define EMIF_ASYNC_RSTROBE_37 0x1200
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#define EMIF_ASYNC_RSTROBE_38 0x1280
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#define EMIF_ASYNC_RSTROBE_39 0x1300
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#define EMIF_ASYNC_RSTROBE_40 0x1380
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#define EMIF_ASYNC_RSTROBE_41 0x1400
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#define EMIF_ASYNC_RSTROBE_42 0x1480
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#define EMIF_ASYNC_RSTROBE_43 0x1500
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#define EMIF_ASYNC_RSTROBE_44 0x1580
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#define EMIF_ASYNC_RSTROBE_45 0x1600
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#define EMIF_ASYNC_RSTROBE_46 0x1680
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#define EMIF_ASYNC_RSTROBE_47 0x1700
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#define EMIF_ASYNC_RSTROBE_48 0x1780
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#define EMIF_ASYNC_RSTROBE_49 0x1800
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#define EMIF_ASYNC_RSTROBE_50 0x1880
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#define EMIF_ASYNC_RSTROBE_51 0x1900
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#define EMIF_ASYNC_RSTROBE_52 0x1980
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#define EMIF_ASYNC_RSTROBE_53 0x1A00
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#define EMIF_ASYNC_RSTROBE_54 0x1A80
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#define EMIF_ASYNC_RSTROBE_55 0x1B00
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#define EMIF_ASYNC_RSTROBE_56 0x1B80
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#define EMIF_ASYNC_RSTROBE_57 0x1C00
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#define EMIF_ASYNC_RSTROBE_58 0x1C80
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#define EMIF_ASYNC_RSTROBE_59 0x1D00
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#define EMIF_ASYNC_RSTROBE_60 0x1D80
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#define EMIF_ASYNC_RSTROBE_61 0x1E00
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#define EMIF_ASYNC_RSTROBE_62 0x1E80
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#define EMIF_ASYNC_RSTROBE_63 0x1F00
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#define EMIF_ASYNC_RSTROBE_64 0x1F80
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#define EMIF_ASYNC_RSETUP_1 0x0000
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#define EMIF_ASYNC_RSETUP_2 0x2000
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#define EMIF_ASYNC_RSETUP_3 0x4000
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#define EMIF_ASYNC_RSETUP_4 0x6000
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#define EMIF_ASYNC_RSETUP_5 0x8000
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#define EMIF_ASYNC_RSETUP_6 0xA000
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#define EMIF_ASYNC_RSETUP_7 0xC000
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#define EMIF_ASYNC_RSETUP_8 0xE000
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#define EMIF_ASYNC_RSETUP_9 0x10000
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#define EMIF_ASYNC_RSETUP_10 0x12000
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#define EMIF_ASYNC_RSETUP_11 0x14000
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#define EMIF_ASYNC_RSETUP_12 0x16000
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#define EMIF_ASYNC_RSETUP_13 0x18000
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#define EMIF_ASYNC_RSETUP_14 0x1A000
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#define EMIF_ASYNC_RSETUP_15 0x1C000
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#define EMIF_ASYNC_RSETUP_16 0x1E000
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#define EMIF_ASYNC_WHOLD_1 0x00000
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#define EMIF_ASYNC_WHOLD_2 0x20000
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#define EMIF_ASYNC_WHOLD_3 0x40000
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#define EMIF_ASYNC_WHOLD_4 0x60000
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#define EMIF_ASYNC_WHOLD_5 0x80000
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#define EMIF_ASYNC_WHOLD_6 0xA0000
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#define EMIF_ASYNC_WHOLD_7 0xC0000
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#define EMIF_ASYNC_WHOLD_8 0xE0000
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#define EMIF_ASYNC_WSTROBE_1 0x0000000
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#define EMIF_ASYNC_WSTROBE_2 0x0100000
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#define EMIF_ASYNC_WSTROBE_3 0x0200000
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#define EMIF_ASYNC_WSTROBE_4 0x0300000
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#define EMIF_ASYNC_WSTROBE_5 0x0400000
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#define EMIF_ASYNC_WSTROBE_6 0x0500000
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#define EMIF_ASYNC_WSTROBE_7 0x0600000
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#define EMIF_ASYNC_WSTROBE_8 0x0700000
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#define EMIF_ASYNC_WSTROBE_9 0x0800000
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#define EMIF_ASYNC_WSTROBE_10 0x0900000
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#define EMIF_ASYNC_WSTROBE_11 0x0A00000
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#define EMIF_ASYNC_WSTROBE_12 0x0B00000
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#define EMIF_ASYNC_WSTROBE_13 0x0C00000
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#define EMIF_ASYNC_WSTROBE_14 0x0D00000
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#define EMIF_ASYNC_WSTROBE_15 0x0E00000
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#define EMIF_ASYNC_WSTROBE_16 0x0F00000
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#define EMIF_ASYNC_WSTROBE_17 0x1000000
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#define EMIF_ASYNC_WSTROBE_18 0x1100000
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#define EMIF_ASYNC_WSTROBE_19 0x1200000
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#define EMIF_ASYNC_WSTROBE_20 0x1300000
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#define EMIF_ASYNC_WSTROBE_21 0x1400000
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#define EMIF_ASYNC_WSTROBE_22 0x1500000
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#define EMIF_ASYNC_WSTROBE_23 0x1600000
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#define EMIF_ASYNC_WSTROBE_24 0x1700000
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#define EMIF_ASYNC_WSTROBE_25 0x1800000
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#define EMIF_ASYNC_WSTROBE_26 0x1900000
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#define EMIF_ASYNC_WSTROBE_27 0x1A00000
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#define EMIF_ASYNC_WSTROBE_28 0x1B00000
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#define EMIF_ASYNC_WSTROBE_29 0x1C00000
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#define EMIF_ASYNC_WSTROBE_30 0x1D00000
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#define EMIF_ASYNC_WSTROBE_31 0x1E00000
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#define EMIF_ASYNC_WSTROBE_32 0x1F00000
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#define EMIF_ASYNC_WSTROBE_33 0x2000000
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#define EMIF_ASYNC_WSTROBE_34 0x2100000
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#define EMIF_ASYNC_WSTROBE_35 0x2200000
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#define EMIF_ASYNC_WSTROBE_36 0x2300000
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#define EMIF_ASYNC_WSTROBE_37 0x2400000
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#define EMIF_ASYNC_WSTROBE_38 0x2500000
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#define EMIF_ASYNC_WSTROBE_39 0x2600000
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#define EMIF_ASYNC_WSTROBE_40 0x2700000
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#define EMIF_ASYNC_WSTROBE_41 0x2800000
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#define EMIF_ASYNC_WSTROBE_42 0x2900000
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#define EMIF_ASYNC_WSTROBE_43 0x2A00000
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#define EMIF_ASYNC_WSTROBE_44 0x2B00000
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#define EMIF_ASYNC_WSTROBE_45 0x2C00000
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#define EMIF_ASYNC_WSTROBE_46 0x2D00000
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#define EMIF_ASYNC_WSTROBE_47 0x2E00000
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#define EMIF_ASYNC_WSTROBE_48 0x2F00000
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#define EMIF_ASYNC_WSTROBE_49 0x3000000
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#define EMIF_ASYNC_WSTROBE_50 0x3100000
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#define EMIF_ASYNC_WSTROBE_51 0x3200000
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#define EMIF_ASYNC_WSTROBE_52 0x3300000
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#define EMIF_ASYNC_WSTROBE_53 0x3400000
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#define EMIF_ASYNC_WSTROBE_54 0x3500000
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#define EMIF_ASYNC_WSTROBE_55 0x3600000
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#define EMIF_ASYNC_WSTROBE_56 0x3700000
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#define EMIF_ASYNC_WSTROBE_57 0x3800000
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#define EMIF_ASYNC_WSTROBE_58 0x3900000
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#define EMIF_ASYNC_WSTROBE_59 0x3A00000
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#define EMIF_ASYNC_WSTROBE_60 0x3B00000
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#define EMIF_ASYNC_WSTROBE_61 0x3C00000
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#define EMIF_ASYNC_WSTROBE_62 0x3D00000
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#define EMIF_ASYNC_WSTROBE_63 0x3E00000
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#define EMIF_ASYNC_WSTROBE_64 0x3F00000
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#define EMIF_ASYNC_WSETUP_1 0x00000000
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#define EMIF_ASYNC_WSETUP_2 0x04000000
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#define EMIF_ASYNC_WSETUP_3 0x08000000
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#define EMIF_ASYNC_WSETUP_4 0x0C000000
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#define EMIF_ASYNC_WSETUP_5 0x10000000
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#define EMIF_ASYNC_WSETUP_6 0x14000000
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#define EMIF_ASYNC_WSETUP_7 0x18000000
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#define EMIF_ASYNC_WSETUP_8 0x1C000000
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#define EMIF_ASYNC_WSETUP_9 0x20000000
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#define EMIF_ASYNC_WSETUP_10 0x24000000
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#define EMIF_ASYNC_WSETUP_11 0x28000000
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#define EMIF_ASYNC_WSETUP_12 0x2C000000
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#define EMIF_ASYNC_WSETUP_13 0x30000000
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#define EMIF_ASYNC_WSETUP_14 0x34000000
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#define EMIF_ASYNC_WSETUP_15 0x38000000
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#define EMIF_ASYNC_WSETUP_16 0x3C000000
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#define EMIF_ASYNC_EW_DISABLE 0x00000000
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#define EMIF_ASYNC_EW_ENABLE 0x40000000
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#define EMIF_ASYNC_SS_DISABLE 0x00000000
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#define EMIF_ASYNC_SS_ENABLE 0x80000000
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//
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// Values for ASYNC_WCCR Register
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//
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#define EMIF_ASYNC_WCCR_WP_LOW 0x00000000
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#define EMIF_ASYNC_WCCR_WP_HIGH 0x01000000
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//
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// Read mask for the registers which has reserved bits.
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//
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#define ASYNC_WCCR_RDMASK 0xF0FF00FF
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#define SDRAM_CR_RDMASK 0xE3FF7F7F
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#define SDRAM_RCR_RDMASK 0x00071FFF
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||
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#define SDRAM_TR_RDMASK 0xFF77FF70
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||
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#define SDR_EXT_TMNG_RDMASK 0x1F
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||
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#define INT_RAW_RDMASK 0x3F
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||
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#define INT_MASK_RDMASK 0x3F
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||
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#define IO_CTRL_RDMASK_RDMASK 0xFFFF
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||
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#define IO_STAT_RDMASK_RDMASK 0xF
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||
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#define NAND_FLASH_CTRL_RDMASK 0x3F3F
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||
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#define NAND_FLASH_STAT_RDMASK 0x30F0F
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||
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#define IODFT_TLECR_REG_RDMASK 0xFFFF
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||
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#define IODFT_TLGCR_REG_RDMASK 0x71FF
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||
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#define IODFT_TLAMR_REG_RDMASK 0x0FFFFFFF
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||
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#define IODFT_TLDCMR_REG_RDMASK 0x3fff3f07
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||
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#define MODEL_REL_NUM_REG_RDMASK 0xFF
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||
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#define NAND_FLASH_4BIT_ECCLR_RDMASK 0x3F
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||
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#define NAND_FLASH_4BIT_ECCx_RDMASK 0x03ff03ff
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||
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#define NAND_FLASH_ERR_ADDRx_RDMASK 0x03ff03ff
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||
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#define NAND_FLASH_ERR_VALx_RDMASK 0x03ff03ff
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||
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||
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#ifdef __cplusplus
|
||
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}
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||
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#endif /* extern "C" */
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||
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#endif // - end of F2837xD_EMIF_DEFINES_H
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||
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//
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||
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// End of file
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||
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//
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