310 lines
13 KiB
C
310 lines
13 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_cmpss.h
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//
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// TITLE: Definitions for the CMPSS registers.
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//
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//###########################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_CMPSS_H
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#define F2837xD_CMPSS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// CMPSS Individual Register Bit Definitions:
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struct COMPCTL_BITS { // bits description
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Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select
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Uint16 COMPHINV:1; // 1 High Comparator Invert Select
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Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select
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Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select
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Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable
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Uint16 rsvd1:1; // 7 Reserved
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Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select
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Uint16 COMPLINV:1; // 9 Low Comparator Invert Select
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Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select
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Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select
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Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable
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Uint16 COMPDACE:1; // 15 Comparator/DAC Enable
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};
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union COMPCTL_REG {
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Uint16 all;
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struct COMPCTL_BITS bit;
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};
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struct COMPHYSCTL_BITS { // bits description
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Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim
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Uint16 rsvd1:13; // 15:3 Reserved
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};
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union COMPHYSCTL_REG {
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Uint16 all;
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struct COMPHYSCTL_BITS bit;
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};
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struct COMPSTS_BITS { // bits description
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Uint16 COMPHSTS:1; // 0 High Comparator Status
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Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status
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Uint16 rsvd1:6; // 7:2 Reserved
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Uint16 COMPLSTS:1; // 8 Low Comparator Status
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Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status
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Uint16 rsvd2:6; // 15:10 Reserved
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};
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union COMPSTS_REG {
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Uint16 all;
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struct COMPSTS_BITS bit;
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};
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struct COMPSTSCLR_BITS { // bits description
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Uint16 rsvd1:1; // 0 Reserved
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Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear
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Uint16 HSYNCCLREN:1; // 2 High Comparator EPWMSYNCPER Clear Enable
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Uint16 rsvd2:6; // 8:3 Reserved
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Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear
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Uint16 LSYNCCLREN:1; // 10 Low Comparator EPWMSYNCPER Clear Enable
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Uint16 rsvd3:5; // 15:11 Reserved
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};
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union COMPSTSCLR_REG {
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Uint16 all;
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struct COMPSTSCLR_BITS bit;
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};
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struct COMPDACCTL_BITS { // bits description
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Uint16 DACSOURCE:1; // 0 DAC Source Control
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Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control
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Uint16 SELREF:1; // 5 DAC Reference Select
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Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select
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Uint16 SWLOADSEL:1; // 7 Software Load Select
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Uint16 rsvd1:6; // 13:8 Reserved
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Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits
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};
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union COMPDACCTL_REG {
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Uint16 all;
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struct COMPDACCTL_BITS bit;
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};
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struct DACHVALS_BITS { // bits description
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Uint16 DACVAL:12; // 11:0 DAC Value Control
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Uint16 rsvd1:4; // 15:12 Reserved
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};
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union DACHVALS_REG {
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Uint16 all;
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struct DACHVALS_BITS bit;
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};
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struct DACHVALA_BITS { // bits description
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Uint16 DACVAL:12; // 11:0 DAC Value Control
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Uint16 rsvd1:4; // 15:12 Reserved
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};
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union DACHVALA_REG {
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Uint16 all;
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struct DACHVALA_BITS bit;
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};
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struct DACLVALS_BITS { // bits description
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Uint16 DACVAL:12; // 11:0 DAC Value Control
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Uint16 rsvd1:4; // 15:12 Reserved
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};
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union DACLVALS_REG {
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Uint16 all;
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struct DACLVALS_BITS bit;
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};
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struct DACLVALA_BITS { // bits description
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Uint16 DACVAL:12; // 11:0 DAC Value Control
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Uint16 rsvd1:4; // 15:12 Reserved
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};
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union DACLVALA_REG {
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Uint16 all;
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struct DACLVALA_BITS bit;
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};
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struct RAMPDLYA_BITS { // bits description
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Uint16 DELAY:13; // 12:0 Ramp Delay Value
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Uint16 rsvd1:3; // 15:13 Reserved
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};
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union RAMPDLYA_REG {
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Uint16 all;
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struct RAMPDLYA_BITS bit;
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};
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struct RAMPDLYS_BITS { // bits description
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Uint16 DELAY:13; // 12:0 Ramp Delay Value
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Uint16 rsvd1:3; // 15:13 Reserved
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};
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union RAMPDLYS_REG {
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Uint16 all;
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struct RAMPDLYS_BITS bit;
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};
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struct CTRIPLFILCTL_BITS { // bits description
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Uint16 rsvd1:4; // 3:0 Reserved
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Uint16 SAMPWIN:5; // 8:4 Sample Window
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Uint16 THRESH:5; // 13:9 Majority Voting Threshold
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Uint16 rsvd2:1; // 14 Reserved
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Uint16 FILINIT:1; // 15 Filter Initialization Bit
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};
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union CTRIPLFILCTL_REG {
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Uint16 all;
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struct CTRIPLFILCTL_BITS bit;
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};
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struct CTRIPLFILCLKCTL_BITS { // bits description
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Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale
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Uint16 rsvd1:6; // 15:10 Reserved
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};
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union CTRIPLFILCLKCTL_REG {
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Uint16 all;
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struct CTRIPLFILCLKCTL_BITS bit;
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};
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struct CTRIPHFILCTL_BITS { // bits description
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Uint16 rsvd1:4; // 3:0 Reserved
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Uint16 SAMPWIN:5; // 8:4 Sample Window
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Uint16 THRESH:5; // 13:9 Majority Voting Threshold
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Uint16 rsvd2:1; // 14 Reserved
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Uint16 FILINIT:1; // 15 Filter Initialization Bit
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};
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union CTRIPHFILCTL_REG {
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Uint16 all;
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struct CTRIPHFILCTL_BITS bit;
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};
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struct CTRIPHFILCLKCTL_BITS { // bits description
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Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale
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Uint16 rsvd1:6; // 15:10 Reserved
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};
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union CTRIPHFILCLKCTL_REG {
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Uint16 all;
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struct CTRIPHFILCLKCTL_BITS bit;
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};
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struct COMPLOCK_BITS { // bits description
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Uint16 COMPCTL:1; // 0 COMPCTL Lock
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Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock
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Uint16 DACCTL:1; // 2 DACCTL Lock
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Uint16 CTRIP:1; // 3 CTRIP Lock
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Uint16 rsvd1:1; // 4 Reserved
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Uint16 rsvd2:11; // 15:5 Reserved
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};
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union COMPLOCK_REG {
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Uint16 all;
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struct COMPLOCK_BITS bit;
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};
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struct CMPSS_REGS {
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union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register
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union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register
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union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register
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union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register
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union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register
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Uint16 rsvd1; // Reserved
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union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register
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union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register
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Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register
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Uint16 rsvd2; // Reserved
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Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register
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Uint16 rsvd3; // Reserved
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Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register
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Uint16 rsvd4; // Reserved
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Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register
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Uint16 rsvd5; // Reserved
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Uint16 RAMPSTS; // CMPSS Ramp Status Register
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Uint16 rsvd6; // Reserved
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union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register
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union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register
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union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register
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union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register
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union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register
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union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register
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union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register
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union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register
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union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register
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};
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//---------------------------------------------------------------------------
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// CMPSS External References & Function Declarations:
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//
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#ifdef CPU1
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extern volatile struct CMPSS_REGS Cmpss1Regs;
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extern volatile struct CMPSS_REGS Cmpss2Regs;
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extern volatile struct CMPSS_REGS Cmpss3Regs;
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extern volatile struct CMPSS_REGS Cmpss4Regs;
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extern volatile struct CMPSS_REGS Cmpss5Regs;
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extern volatile struct CMPSS_REGS Cmpss6Regs;
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extern volatile struct CMPSS_REGS Cmpss7Regs;
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extern volatile struct CMPSS_REGS Cmpss8Regs;
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#endif
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#ifdef CPU2
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extern volatile struct CMPSS_REGS Cmpss1Regs;
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extern volatile struct CMPSS_REGS Cmpss2Regs;
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extern volatile struct CMPSS_REGS Cmpss3Regs;
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extern volatile struct CMPSS_REGS Cmpss4Regs;
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extern volatile struct CMPSS_REGS Cmpss5Regs;
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extern volatile struct CMPSS_REGS Cmpss6Regs;
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extern volatile struct CMPSS_REGS Cmpss7Regs;
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extern volatile struct CMPSS_REGS Cmpss8Regs;
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#endif
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif
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//===========================================================================
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// End of file.
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//===========================================================================
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