202 lines
8.2 KiB
C
202 lines
8.2 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_spi.h
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//
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// TITLE: Definitions for the SPI registers.
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//
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//###########################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_SPI_H
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#define F2837xD_SPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// SPI Individual Register Bit Definitions:
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struct SPICCR_BITS { // bits description
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Uint16 SPICHAR:4; // 3:0 Character Length Control
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Uint16 SPILBK:1; // 4 SPI Loopback
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Uint16 HS_MODE:1; // 5 High Speed mode control
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Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity
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Uint16 SPISWRESET:1; // 7 SPI Software Reset
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Uint16 rsvd1:8; // 15:8 Reserved
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};
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union SPICCR_REG {
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Uint16 all;
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struct SPICCR_BITS bit;
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};
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struct SPICTL_BITS { // bits description
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Uint16 SPIINTENA:1; // 0 SPI Interupt Enable
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Uint16 TALK:1; // 1 Master/Slave Transmit Enable
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Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control
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Uint16 CLK_PHASE:1; // 3 SPI Clock Phase
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Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable
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Uint16 rsvd1:11; // 15:5 Reserved
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};
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union SPICTL_REG {
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Uint16 all;
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struct SPICTL_BITS bit;
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};
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struct SPISTS_BITS { // bits description
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Uint16 rsvd1:5; // 4:0 Reserved
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Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag
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Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag
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Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag
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Uint16 rsvd2:8; // 15:8 Reserved
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};
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union SPISTS_REG {
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Uint16 all;
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struct SPISTS_BITS bit;
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};
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struct SPIBRR_BITS { // bits description
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Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control
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Uint16 rsvd1:9; // 15:7 Reserved
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};
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union SPIBRR_REG {
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Uint16 all;
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struct SPIBRR_BITS bit;
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};
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struct SPIFFTX_BITS { // bits description
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Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level
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Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable
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Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear
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Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag
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Uint16 TXFFST:5; // 12:8 Transmit FIFO Status
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Uint16 TXFIFO:1; // 13 TXFIFO Reset
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Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable
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Uint16 SPIRST:1; // 15 SPI Reset
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};
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union SPIFFTX_REG {
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Uint16 all;
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struct SPIFFTX_BITS bit;
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};
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struct SPIFFRX_BITS { // bits description
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Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level
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Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable
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Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear
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Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag
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Uint16 RXFFST:5; // 12:8 Receive FIFO Status
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Uint16 RXFIFORESET:1; // 13 RXFIFO Reset
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Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear
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Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag
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};
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union SPIFFRX_REG {
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Uint16 all;
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struct SPIFFRX_BITS bit;
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};
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struct SPIFFCT_BITS { // bits description
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Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits
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Uint16 rsvd1:8; // 15:8 Reserved
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};
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union SPIFFCT_REG {
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Uint16 all;
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struct SPIFFCT_BITS bit;
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};
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struct SPIPRI_BITS { // bits description
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Uint16 TRIWIRE:1; // 0 3-wire mode select bit
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Uint16 STEINV:1; // 1 SPISTE inversion bit
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Uint16 rsvd1:2; // 3:2 Reserved
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Uint16 FREE:1; // 4 Free emulation mode
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Uint16 SOFT:1; // 5 Soft emulation mode
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Uint16 rsvd2:1; // 6 Reserved
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Uint16 rsvd3:9; // 15:7 Reserved
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};
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union SPIPRI_REG {
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Uint16 all;
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struct SPIPRI_BITS bit;
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};
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struct SPI_REGS {
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union SPICCR_REG SPICCR; // SPI Configuration Control Register
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union SPICTL_REG SPICTL; // SPI Operation Control Register
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union SPISTS_REG SPISTS; // SPI Status Register
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Uint16 rsvd1; // Reserved
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union SPIBRR_REG SPIBRR; // SPI Baud Rate Register
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Uint16 rsvd2; // Reserved
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Uint16 SPIRXEMU; // SPI Emulation Buffer Register
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Uint16 SPIRXBUF; // SPI Serial Input Buffer Register
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Uint16 SPITXBUF; // SPI Serial Output Buffer Register
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Uint16 SPIDAT; // SPI Serial Data Register
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union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register
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union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register
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union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register
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Uint16 rsvd3[2]; // Reserved
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union SPIPRI_REG SPIPRI; // SPI Priority Control Register
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};
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//---------------------------------------------------------------------------
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// SPI External References & Function Declarations:
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//
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#ifdef CPU1
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extern volatile struct SPI_REGS SpiaRegs;
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extern volatile struct SPI_REGS SpibRegs;
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extern volatile struct SPI_REGS SpicRegs;
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#endif
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#ifdef CPU2
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extern volatile struct SPI_REGS SpiaRegs;
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extern volatile struct SPI_REGS SpibRegs;
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extern volatile struct SPI_REGS SpicRegs;
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#endif
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif
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//===========================================================================
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// End of file.
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//===========================================================================
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