404 lines
18 KiB
C
404 lines
18 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_upp.h
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//
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// TITLE: Definitions for the UPP registers.
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//
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//###########################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_UPP_H
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#define F2837xD_UPP_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// UPP Individual Register Bit Definitions:
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struct PERCTL_BITS { // bits description
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Uint16 FREE:1; // 0 Emulation control.
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Uint16 SOFT:1; // 1 Emulation control.
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Uint16 RTEMU:1; // 2 Realtime emulation control.
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Uint16 PEREN:1; // 3 Peripheral Enable
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Uint16 SOFTRST:1; // 4 Software Reset
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Uint16 rsvd1:2; // 6:5 Reserved
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Uint16 DMAST:1; // 7 DMA Burst transaction status
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Uint16 rsvd2:8; // 15:8 Reserved
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Uint16 rsvd3:16; // 31:16 Reserved
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};
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union PERCTL_REG {
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Uint32 all;
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struct PERCTL_BITS bit;
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};
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struct CHCTL_BITS { // bits description
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Uint16 MODE:2; // 1:0 Operating mode
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Uint16 rsvd1:1; // 2 Reserved
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Uint16 SDRTXILA:1; // 3 SDR TX Interleve mode
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Uint16 DEMUXA:1; // 4 DDR de-multiplexing mode
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Uint16 rsvd2:11; // 15:5 Reserved
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Uint16 DRA:1; // 16 Data rate
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Uint16 rsvd3:14; // 30:17 Reserved
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Uint16 rsvd4:1; // 31 Reserved
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};
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union CHCTL_REG {
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Uint32 all;
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struct CHCTL_BITS bit;
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};
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struct IFCFG_BITS { // bits description
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Uint16 STARTPOLA:1; // 0 Polarity of START(SELECT) signal
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Uint16 ENAPOLA:1; // 1 Polarity of ENABLE(WRITE) signal
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Uint16 WAITPOLA:1; // 2 Polarity of WAIT signal.
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Uint16 STARTA:1; // 3 Enable Usage of START (SELECT) signal
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Uint16 ENAA:1; // 4 Enable Usage of ENABLE (WRITE) signal
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Uint16 WAITA:1; // 5 Enable Usage of WAIT signal
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Uint16 rsvd1:2; // 7:6 Reserved
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Uint16 CLKDIVA:4; // 11:8 Clock divider for tx mode
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Uint16 CLKINVA:1; // 12 Clock inversion
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Uint16 TRISENA:1; // 13 Pin Tri-state Control
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Uint16 rsvd2:2; // 15:14 Reserved
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Uint16 rsvd3:6; // 21:16 Reserved
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Uint16 rsvd4:2; // 23:22 Reserved
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Uint16 rsvd5:6; // 29:24 Reserved
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Uint16 rsvd6:2; // 31:30 Reserved
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};
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union IFCFG_REG {
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Uint32 all;
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struct IFCFG_BITS bit;
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};
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struct IFIVAL_BITS { // bits description
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Uint16 VALA:9; // 8:0 Idle Value
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Uint16 rsvd1:7; // 15:9 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union IFIVAL_REG {
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Uint32 all;
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struct IFIVAL_BITS bit;
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};
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struct THCFG_BITS { // bits description
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Uint16 RDSIZEI:2; // 1:0 DMA Read Threshold for DMA Channel I
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Uint16 rsvd1:6; // 7:2 Reserved
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Uint16 RDSIZEQ:2; // 9:8 DMA Read Threshold for DMA Channel Q
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Uint16 rsvd2:6; // 15:10 Reserved
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Uint16 TXSIZEA:2; // 17:16 I/O Transmit Threshold Value
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Uint16 rsvd3:6; // 23:18 Reserved
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Uint16 rsvd4:2; // 25:24 Reserved
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Uint16 rsvd5:6; // 31:26 Reserved
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};
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union THCFG_REG {
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Uint32 all;
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struct THCFG_BITS bit;
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};
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struct RAWINTST_BITS { // bits description
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Uint16 DPEI:1; // 0 Interrupt raw status for DMA programming error
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Uint16 UOEI:1; // 1 Interrupt raw status for DMA under-run or over-run
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Uint16 rsvd1:1; // 2 Reserved
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Uint16 EOWI:1; // 3 Interrupt raw status for end-of window condition
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Uint16 EOLI:1; // 4 Interrupt raw status for end-of-line condition
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Uint16 rsvd2:3; // 7:5 Reserved
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Uint16 DPEQ:1; // 8 Interrupt raw status for DMA programming error
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Uint16 UOEQ:1; // 9 Interrupt raw status for DMA under-run or over-run
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Uint16 rsvd3:1; // 10 Reserved
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Uint16 EOWQ:1; // 11 Interrupt raw status for end-of window condition
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Uint16 EOLQ:1; // 12 Interrupt raw status for end-of-line condition
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Uint16 rsvd4:3; // 15:13 Reserved
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Uint16 rsvd5:16; // 31:16 Reserved
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};
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union RAWINTST_REG {
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Uint32 all;
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struct RAWINTST_BITS bit;
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};
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struct ENINTST_BITS { // bits description
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Uint16 DPEI:1; // 0 Interrupt enable status for DMA programming error
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Uint16 UOEI:1; // 1 Interrupt enable status for DMA under-run or over-run
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Uint16 rsvd1:1; // 2 Reserved
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Uint16 EOWI:1; // 3 Interrupt enable status for end-of window condition
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Uint16 EOLI:1; // 4 Interrupt enable status for end-of-line condition
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Uint16 rsvd2:3; // 7:5 Reserved
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Uint16 DPEQ:1; // 8 Interrupt enable status for DMA programming error
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Uint16 UOEQ:1; // 9 Interrupt enable status for DMA under-run or over-run
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Uint16 rsvd3:1; // 10 Reserved
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Uint16 EOWQ:1; // 11 Interrupt enable status for end-of window condition
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Uint16 EOLQ:1; // 12 Interrupt enable status for end-of-line condition
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Uint16 rsvd4:3; // 15:13 Reserved
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Uint16 rsvd5:16; // 31:16 Reserved
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};
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union ENINTST_REG {
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Uint32 all;
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struct ENINTST_BITS bit;
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};
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struct INTENSET_BITS { // bits description
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Uint16 DPEI:1; // 0 Interrupt enable for DMA programming error
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Uint16 UOEI:1; // 1 Interrupt enable for DMA under-run or over-run
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Uint16 rsvd1:1; // 2 Reserved
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Uint16 EOWI:1; // 3 Interrupt enable for end-of window condition
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Uint16 EOLI:1; // 4 Interrupt enable for end-of-line condition
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Uint16 rsvd2:3; // 7:5 Reserved
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Uint16 DPEQ:1; // 8 Interrupt enable for DMA programming error
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Uint16 UOEQ:1; // 9 Interrupt enable for DMA under-run or over-run
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Uint16 rsvd3:1; // 10 Reserved
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Uint16 EOWQ:1; // 11 Interrupt enable for end-of window condition
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Uint16 EOLQ:1; // 12 Interrupt enable for end-of-line condition
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Uint16 rsvd4:3; // 15:13 Reserved
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Uint16 rsvd5:16; // 31:16 Reserved
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};
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union INTENSET_REG {
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Uint32 all;
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struct INTENSET_BITS bit;
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};
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struct INTENCLR_BITS { // bits description
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Uint16 DPEI:1; // 0 Interrupt clear for DMA programming error
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Uint16 UOEI:1; // 1 Interrupt clear for DMA under-run or over-run
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Uint16 rsvd1:1; // 2 Reserved
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Uint16 EOWI:1; // 3 Interrupt clear for end-of window condition
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Uint16 EOLI:1; // 4 Interrupt clear for end-of-line condition
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Uint16 rsvd2:3; // 7:5 Reserved
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Uint16 DPEQ:1; // 8 Interrupt clear for DMA programming error
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Uint16 UOEQ:1; // 9 Interrupt clear for DMA under-run or over-run
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Uint16 rsvd3:1; // 10 Reserved
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Uint16 EOWQ:1; // 11 Interrupt clear for end-of window condition
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Uint16 EOLQ:1; // 12 Interrupt clear for end-of-line condition
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Uint16 rsvd4:3; // 15:13 Reserved
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Uint16 rsvd5:16; // 31:16 Reserved
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};
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union INTENCLR_REG {
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Uint32 all;
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struct INTENCLR_BITS bit;
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};
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struct CHIDESC1_BITS { // bits description
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Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel I transfer.
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Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel I transfer.
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};
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union CHIDESC1_REG {
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Uint32 all;
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struct CHIDESC1_BITS bit;
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};
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struct CHIDESC2_BITS { // bits description
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Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset.
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Uint16 rsvd1:16; // 31:16 Reserved
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};
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union CHIDESC2_REG {
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Uint32 all;
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struct CHIDESC2_BITS bit;
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};
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struct CHIST1_BITS { // bits description
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Uint16 BCNT:16; // 15:0 Current byte number.
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Uint16 LCNT:16; // 31:16 Current line number.
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};
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union CHIST1_REG {
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Uint32 all;
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struct CHIST1_BITS bit;
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};
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struct CHIST2_BITS { // bits description
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Uint16 ACT:1; // 0 Status of DMA descriptor.
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Uint16 PEND:1; // 1 Status of DMA.
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Uint16 rsvd1:2; // 3:2 Reserved
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Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel I tranfer.
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Uint16 rsvd2:8; // 15:8 Reserved
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Uint16 rsvd3:16; // 31:16 Reserved
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};
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union CHIST2_REG {
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Uint32 all;
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struct CHIST2_BITS bit;
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};
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struct CHQDESC1_BITS { // bits description
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Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel Q transfer.
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Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel Q transfer.
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};
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union CHQDESC1_REG {
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Uint32 all;
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struct CHQDESC1_BITS bit;
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};
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struct CHQDESC2_BITS { // bits description
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Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset.
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Uint16 rsvd1:16; // 31:16 Reserved
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};
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union CHQDESC2_REG {
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Uint32 all;
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struct CHQDESC2_BITS bit;
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};
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struct CHQST1_BITS { // bits description
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Uint16 BCNT:16; // 15:0 Current byte number.
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Uint16 LCNT:16; // 31:16 Current line number.
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};
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union CHQST1_REG {
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Uint32 all;
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struct CHQST1_BITS bit;
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};
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struct CHQST2_BITS { // bits description
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Uint16 ACT:1; // 0 Status of DMA descriptor.
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Uint16 PEND:1; // 1 Status of DMA.
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Uint16 rsvd1:2; // 3:2 Reserved
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Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel Q tranfer.
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Uint16 rsvd2:8; // 15:8 Reserved
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Uint16 rsvd3:16; // 31:16 Reserved
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};
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union CHQST2_REG {
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Uint32 all;
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struct CHQST2_BITS bit;
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};
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struct GINTEN_BITS { // bits description
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Uint16 GINTEN:1; // 0 Global Interrupt Enable
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Uint16 rsvd1:15; // 15:1 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union GINTEN_REG {
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Uint32 all;
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struct GINTEN_BITS bit;
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};
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struct GINTFLG_BITS { // bits description
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Uint16 GINTFLG:1; // 0 Global Interrupt Flag
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Uint16 rsvd1:15; // 15:1 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union GINTFLG_REG {
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Uint32 all;
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struct GINTFLG_BITS bit;
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};
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struct GINTCLR_BITS { // bits description
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Uint16 GINTCLR:1; // 0 Global Interrupt Clear
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Uint16 rsvd1:15; // 15:1 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union GINTCLR_REG {
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Uint32 all;
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struct GINTCLR_BITS bit;
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};
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struct DLYCTL_BITS { // bits description
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Uint16 DLYDIS:1; // 0 IO dealy control disable.
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Uint16 DLYCTL:2; // 2:1 IO delay control.
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Uint16 rsvd1:13; // 15:3 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union DLYCTL_REG {
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Uint32 all;
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struct DLYCTL_BITS bit;
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};
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struct UPP_REGS {
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Uint32 PID; // Peripheral ID Register
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union PERCTL_REG PERCTL; // Peripheral Control Register
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Uint16 rsvd1[4]; // Reserved
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union CHCTL_REG CHCTL; // General Control Register
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union IFCFG_REG IFCFG; // Interface Configuration Register
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||
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union IFIVAL_REG IFIVAL; // Interface Idle Value Register
|
||
|
|
union THCFG_REG THCFG; // Threshold Configuration Register
|
||
|
|
union RAWINTST_REG RAWINTST; // Raw Interrupt Status Register
|
||
|
|
union ENINTST_REG ENINTST; // Enable Interrupt Status Register
|
||
|
|
union INTENSET_REG INTENSET; // Interrupt Enable Set Register
|
||
|
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union INTENCLR_REG INTENCLR; // Interrupt Enable Clear Register
|
||
|
|
Uint16 rsvd2[8]; // Reserved
|
||
|
|
Uint32 CHIDESC0; // DMA Channel I Descriptor 0 Register
|
||
|
|
union CHIDESC1_REG CHIDESC1; // DMA Channel I Descriptor 1 Register
|
||
|
|
union CHIDESC2_REG CHIDESC2; // DMA Channel I Descriptor 2 Register
|
||
|
|
Uint16 rsvd3[2]; // Reserved
|
||
|
|
Uint32 CHIST0; // DMA Channel I Status 0 Register
|
||
|
|
union CHIST1_REG CHIST1; // DMA Channel I Status 1 Register
|
||
|
|
union CHIST2_REG CHIST2; // DMA Channel I Status 2 Register
|
||
|
|
Uint16 rsvd4[2]; // Reserved
|
||
|
|
Uint32 CHQDESC0; // DMA Channel Q Descriptor 0 Register
|
||
|
|
union CHQDESC1_REG CHQDESC1; // DMA Channel Q Descriptor 1 Register
|
||
|
|
union CHQDESC2_REG CHQDESC2; // DMA Channel Q Descriptor 2 Register
|
||
|
|
Uint16 rsvd5[2]; // Reserved
|
||
|
|
Uint32 CHQST0; // DMA Channel Q Status 0 Register
|
||
|
|
union CHQST1_REG CHQST1; // DMA Channel Q Status 1 Register
|
||
|
|
union CHQST2_REG CHQST2; // DMA Channel Q Status 2 Register
|
||
|
|
Uint16 rsvd6[2]; // Reserved
|
||
|
|
union GINTEN_REG GINTEN; // Global Peripheral Interrupt Enable Register
|
||
|
|
union GINTFLG_REG GINTFLG; // Global Peripheral Interrupt Flag Register
|
||
|
|
union GINTCLR_REG GINTCLR; // Global Peripheral Interrupt Clear Register
|
||
|
|
union DLYCTL_REG DLYCTL; // IO clock data skew control Register
|
||
|
|
};
|
||
|
|
|
||
|
|
//---------------------------------------------------------------------------
|
||
|
|
// UPP External References & Function Declarations:
|
||
|
|
//
|
||
|
|
#ifdef CPU1
|
||
|
|
extern volatile struct UPP_REGS UppRegs;
|
||
|
|
#endif
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif /* extern "C" */
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//===========================================================================
|
||
|
|
// End of file.
|
||
|
|
//===========================================================================
|