303 lines
18 KiB
C
303 lines
18 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_xbar.h
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//
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// TITLE: Definitions for the XBAR registers.
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//
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//###########################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_XBAR_H
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#define F2837xD_XBAR_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// XBAR Individual Register Bit Definitions:
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struct XBARFLG1_BITS { // bits description
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Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal
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Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal
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Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal
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Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal
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Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal
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Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal
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Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal
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Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal
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Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal
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Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal
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Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal
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Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal
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Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal
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Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal
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Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal
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Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal
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Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal
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Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal
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Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal
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Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal
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Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal
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Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal
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Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal
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Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal
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Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal
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Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal
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Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal
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Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal
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Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal
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Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal
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Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal
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Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal
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};
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union XBARFLG1_REG {
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Uint32 all;
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struct XBARFLG1_BITS bit;
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};
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struct XBARFLG2_BITS { // bits description
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Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal
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Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal
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Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal
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Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal
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Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal
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Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal
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Uint16 ADCSOCAO:1; // 6 Input Flag for ADCSOCAO Signal
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Uint16 ADCSOCBO:1; // 7 Input Flag for ADCSOCBO Signal
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Uint16 CLB1_OUT4:1; // 8 Input Flag for CLB1_OUT4 Signal
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Uint16 CLB1_OUT5:1; // 9 Input Flag for CLB1_OUT5 Signal
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Uint16 CLB2_OUT4:1; // 10 Input Flag for CLB2_OUT4 Signal
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Uint16 CLB2_OUT5:1; // 11 Input Flag for CLB2_OUT5 Signal
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Uint16 CLB3_OUT4:1; // 12 Input Flag for CLB3_OUT4 Signal
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Uint16 CLB3_OUT5:1; // 13 Input Flag for CLB3_OUT5 Signal
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Uint16 CLB4_OUT4:1; // 14 Input Flag for CLB4_OUT4 Signal
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Uint16 CLB4_OUT5:1; // 15 Input Flag for CLB4_OUT5 Signal
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Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal
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Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal
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Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal
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Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal
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Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal
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Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal
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Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal
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Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal
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Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal
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Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal
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Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal
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Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal
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Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal
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Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal
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Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal
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Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal
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};
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union XBARFLG2_REG {
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Uint32 all;
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struct XBARFLG2_BITS bit;
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};
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struct XBARFLG3_BITS { // bits description
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Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal
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Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal
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Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal
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Uint16 ADCDEVT1:1; // 3 Input Flag for ADCDEVT1 Signal
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Uint16 ADCDEVT2:1; // 4 Input Flag for ADCDEVT2 Signal
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Uint16 ADCDEVT3:1; // 5 Input Flag for ADCDEVT3 Signal
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Uint16 ADCDEVT4:1; // 6 Input Flag for ADCDEVT4 Signal
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Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal
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Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal
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Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal
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Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal
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Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal
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Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal
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Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal
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Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal
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Uint16 SD2FLT1_COMPL:1; // 15 Input Flag for SD2FLT1.COMPL Signal
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Uint16 SD2FLT1_COMPH:1; // 16 Input Flag for SD2FLT1.COMPH Signal
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Uint16 SD2FLT2_COMPL:1; // 17 Input Flag for SD2FLT2.COMPL Signal
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Uint16 SD2FLT2_COMPH:1; // 18 Input Flag for SD2FLT2.COMPH Signal
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Uint16 SD2FLT3_COMPL:1; // 19 Input Flag for SD2FLT3.COMPL Signal
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Uint16 SD2FLT3_COMPH:1; // 20 Input Flag for SD2FLT3.COMPH Signal
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Uint16 SD2FLT4_COMPL:1; // 21 Input Flag for SD2FLT4.COMPL Signal
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Uint16 SD2FLT4_COMPH:1; // 22 Input Flag for SD2FLT4.COMPH Signal
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Uint16 rsvd1:9; // 31:23 Reserved
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};
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union XBARFLG3_REG {
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Uint32 all;
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struct XBARFLG3_BITS bit;
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};
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struct XBARCLR1_BITS { // bits description
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Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal
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Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal
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Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal
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Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal
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Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal
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Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal
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Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal
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Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal
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Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal
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Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal
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Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal
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Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal
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Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal
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Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal
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Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal
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Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal
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Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal
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Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal
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Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal
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Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal
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Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal
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Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal
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Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal
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Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal
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Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal
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Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal
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Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal
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Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal
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Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal
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Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal
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Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal
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Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal
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};
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union XBARCLR1_REG {
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Uint32 all;
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struct XBARCLR1_BITS bit;
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};
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struct XBARCLR2_BITS { // bits description
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Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal
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Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal
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Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal
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Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal
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Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal
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Uint16 INPUT7:1; // 5 Input Flag Clear for INPUT7 Signal
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Uint16 ADCSOCAO:1; // 6 Input Flag Clear for ADCSOCAO Signal
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Uint16 ADCSOCBO:1; // 7 Input Flag Clear for ADCSOCBO Signal
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Uint16 CLB1_OUT4:1; // 8 Input Flag Clear for CLB1_OUT4 Signal
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Uint16 CLB1_OUT5:1; // 9 Input Flag Clear for CLB1_OUT5 Signal
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Uint16 CLB2_OUT4:1; // 10 Input Flag Clear for CLB2_OUT4 Signal
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Uint16 CLB2_OUT5:1; // 11 Input Flag Clear for CLB2_OUT5 Signal
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Uint16 CLB3_OUT4:1; // 12 Input Flag Clear for CLB3_OUT4 Signal
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Uint16 CLB3_OUT5:1; // 13 Input Flag Clear for CLB3_OUT5 Signal
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Uint16 CLB4_OUT4:1; // 14 Input Flag Clear for CLB4_OUT4 Signal
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Uint16 CLB4_OUT5:1; // 15 Input Flag Clear for CLB4_OUT5 Signal
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Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal
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Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal
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Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal
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Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal
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Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal
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Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal
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Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal
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Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal
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Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal
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Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal
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Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal
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Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal
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Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal
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Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal
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Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal
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Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal
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};
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union XBARCLR2_REG {
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Uint32 all;
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struct XBARCLR2_BITS bit;
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};
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struct XBARCLR3_BITS { // bits description
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Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal
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Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal
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Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal
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Uint16 ADCDEVT1:1; // 3 Input Flag Clear for ADCDEVT1 Signal
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Uint16 ADCDEVT2:1; // 4 Input Flag Clear for ADCDEVT2 Signal
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Uint16 ADCDEVT3:1; // 5 Input Flag Clear for ADCDEVT3 Signal
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Uint16 ADCDEVT4:1; // 6 Input Flag Clear for ADCDEVT4 Signal
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Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal
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Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal
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Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal
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Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal
|
||
|
|
Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal
|
||
|
|
Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal
|
||
|
|
Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal
|
||
|
|
Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal
|
||
|
|
Uint16 SD2FLT1_COMPL:1; // 15 Input Flag Clear for SD2FLT1.COMPL Signal
|
||
|
|
Uint16 SD2FLT1_COMPH:1; // 16 Input Flag Clear for SD2FLT1.COMPH Signal
|
||
|
|
Uint16 SD2FLT2_COMPL:1; // 17 Input Flag Clear for SD2FLT2.COMPL Signal
|
||
|
|
Uint16 SD2FLT2_COMPH:1; // 18 Input Flag Clear for SD2FLT2.COMPH Signal
|
||
|
|
Uint16 SD2FLT3_COMPL:1; // 19 Input Flag Clear for SD2FLT3.COMPL Signal
|
||
|
|
Uint16 SD2FLT3_COMPH:1; // 20 Input Flag Clear for SD2FLT3.COMPH Signal
|
||
|
|
Uint16 SD2FLT4_COMPL:1; // 21 Input Flag Clear for SD2FLT4.COMPL Signal
|
||
|
|
Uint16 SD2FLT4_COMPH:1; // 22 Input Flag Clear for SD2FLT4.COMPH Signal
|
||
|
|
Uint16 rsvd1:9; // 31:23 Reserved
|
||
|
|
};
|
||
|
|
|
||
|
|
union XBARCLR3_REG {
|
||
|
|
Uint32 all;
|
||
|
|
struct XBARCLR3_BITS bit;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct XBAR_REGS {
|
||
|
|
union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1
|
||
|
|
union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2
|
||
|
|
union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3
|
||
|
|
Uint16 rsvd1[2]; // Reserved
|
||
|
|
union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1
|
||
|
|
union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2
|
||
|
|
union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3
|
||
|
|
};
|
||
|
|
|
||
|
|
//---------------------------------------------------------------------------
|
||
|
|
// XBAR External References & Function Declarations:
|
||
|
|
//
|
||
|
|
#ifdef CPU1
|
||
|
|
extern volatile struct XBAR_REGS XbarRegs;
|
||
|
|
#endif
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif /* extern "C" */
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//===========================================================================
|
||
|
|
// End of file.
|
||
|
|
//===========================================================================
|