301 lines
13 KiB
C
301 lines
13 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_emif.h
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//
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// TITLE: Definitions for the EMIF registers.
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//
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//###########################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_EMIF_H
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#define F2837xD_EMIF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// EMIF Individual Register Bit Definitions:
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struct RCSR_BITS { // bits description
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Uint16 MINOR_REVISION:8; // 7:0 Minor Revision.
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Uint16 MAJOR_REVISION:8; // 15:8 Major Revision.
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Uint16 MODULE_ID:14; // 29:16 EMIF module ID.
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Uint16 FR:1; // 30 EMIF is running in full rate or half rate.
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Uint16 BE:1; // 31 EMIF endian mode.
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};
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union RCSR_REG {
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Uint32 all;
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struct RCSR_BITS bit;
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};
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struct ASYNC_WCCR_BITS { // bits description
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Uint16 MAX_EXT_WAIT:8; // 7:0 Maximum Extended Wait cycles.
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Uint16 rsvd1:8; // 15:8 Reserved
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Uint16 rsvd2:2; // 17:16 Reserved
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Uint16 rsvd3:2; // 19:18 Reserved
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Uint16 rsvd4:2; // 21:20 Reserved
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Uint16 rsvd5:2; // 23:22 Reserved
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Uint16 rsvd6:4; // 27:24 Reserved
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Uint16 WP0:1; // 28 Polarity for EMxWAIT.
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Uint16 rsvd7:1; // 29 Reserved
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Uint16 rsvd8:1; // 30 Reserved
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Uint16 rsvd9:1; // 31 Reserved
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};
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union ASYNC_WCCR_REG {
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Uint32 all;
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struct ASYNC_WCCR_BITS bit;
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};
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struct SDRAM_CR_BITS { // bits description
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Uint16 PAGESIGE:3; // 2:0 Page Size.
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Uint16 rsvd1:1; // 3 Reserved
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Uint16 IBANK:3; // 6:4 Internal Bank setup of SDRAM devices.
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Uint16 rsvd2:1; // 7 Reserved
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Uint16 BIT_11_9_LOCK:1; // 8 Bits 11 to 9 are writable only if this bit is set.
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Uint16 CL:3; // 11:9 CAS Latency.
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Uint16 rsvd3:1; // 12 Reserved
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Uint16 rsvd4:1; // 13 Reserved
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Uint16 NM:1; // 14 Narrow Mode.
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Uint16 rsvd5:1; // 15 Reserved
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Uint16 rsvd6:1; // 16 Reserved
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Uint16 rsvd7:2; // 18:17 Reserved
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Uint16 rsvd8:1; // 19 Reserved
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Uint16 rsvd9:3; // 22:20 Reserved
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Uint16 rsvd10:3; // 25:23 Reserved
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Uint16 rsvd11:3; // 28:26 Reserved
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Uint16 PDWR:1; // 29 Perform refreshes during Power Down.
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Uint16 PD:1; // 30 Power Down.
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Uint16 SR:1; // 31 Self Refresh.
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};
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union SDRAM_CR_REG {
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Uint32 all;
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struct SDRAM_CR_BITS bit;
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};
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struct SDRAM_RCR_BITS { // bits description
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Uint16 REFRESH_RATE:13; // 12:0 Refresh Rate.
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Uint16 rsvd1:3; // 15:13 Reserved
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Uint16 rsvd2:3; // 18:16 Reserved
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Uint16 rsvd3:13; // 31:19 Reserved
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};
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union SDRAM_RCR_REG {
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Uint32 all;
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struct SDRAM_RCR_BITS bit;
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};
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struct ASYNC_CS2_CR_BITS { // bits description
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Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size.
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Uint16 TA:2; // 3:2 Turn Around cycles.
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Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles.
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Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles.
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Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles.
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Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles.
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Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles.
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Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles.
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Uint16 EW:1; // 30 Extend Wait mode.
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Uint16 SS:1; // 31 Select Strobe mode.
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};
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union ASYNC_CS2_CR_REG {
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Uint32 all;
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struct ASYNC_CS2_CR_BITS bit;
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};
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struct ASYNC_CS3_CR_BITS { // bits description
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Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size.
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Uint16 TA:2; // 3:2 Turn Around cycles.
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Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles.
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Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles.
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Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles.
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Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles.
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Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles.
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Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles.
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Uint16 EW:1; // 30 Extend Wait mode.
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Uint16 SS:1; // 31 Select Strobe mode.
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};
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union ASYNC_CS3_CR_REG {
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Uint32 all;
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struct ASYNC_CS3_CR_BITS bit;
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};
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struct ASYNC_CS4_CR_BITS { // bits description
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Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size.
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Uint16 TA:2; // 3:2 Turn Around cycles.
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Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles.
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Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles.
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Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles.
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Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles.
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Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles.
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Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles.
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Uint16 EW:1; // 30 Extend Wait mode.
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Uint16 SS:1; // 31 Select Strobe mode.
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};
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union ASYNC_CS4_CR_REG {
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Uint32 all;
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struct ASYNC_CS4_CR_BITS bit;
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};
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struct SDRAM_TR_BITS { // bits description
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Uint16 rsvd1:4; // 3:0 Reserved
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Uint16 T_RRD:3; // 6:4 Activate to Activate timing for different bank.
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Uint16 rsvd2:1; // 7 Reserved
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Uint16 T_RC:4; // 11:8 Activate to Activate timing .
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Uint16 T_RAS:4; // 15:12 Activate to Precharge timing.
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Uint16 T_WR:3; // 18:16 Last Write to Precharge timing.
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Uint16 rsvd3:1; // 19 Reserved
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Uint16 T_RCD:3; // 22:20 Activate to Read/Write timing.
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Uint16 rsvd4:1; // 23 Reserved
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Uint16 T_RP:3; // 26:24 Precharge to Activate/Refresh timing.
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Uint16 T_RFC:5; // 31:27 Refresh/Load Mode to Refresh/Activate timing
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};
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union SDRAM_TR_REG {
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Uint32 all;
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struct SDRAM_TR_BITS bit;
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};
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struct SDR_EXT_TMNG_BITS { // bits description
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Uint16 T_XS:5; // 4:0 Self Refresh exit to new command timing.
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Uint16 rsvd1:11; // 15:5 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union SDR_EXT_TMNG_REG {
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Uint32 all;
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struct SDR_EXT_TMNG_BITS bit;
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};
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struct INT_RAW_BITS { // bits description
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Uint16 AT:1; // 0 Asynchronous Timeout.
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Uint16 LT:1; // 1 Line Trap.
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Uint16 WR:4; // 5:2 Wait Rise.
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Uint16 rsvd1:10; // 15:6 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union INT_RAW_REG {
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Uint32 all;
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struct INT_RAW_BITS bit;
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};
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struct INT_MSK_BITS { // bits description
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Uint16 AT_MASKED:1; // 0 Asynchronous Timeout.
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Uint16 LT_MASKED:1; // 1 Line Trap.
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Uint16 WR_MASKED:4; // 5:2 Wait Rise.
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Uint16 rsvd1:10; // 15:6 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union INT_MSK_REG {
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Uint32 all;
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struct INT_MSK_BITS bit;
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};
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struct INT_MSK_SET_BITS { // bits description
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Uint16 AT_MASK_SET:1; // 0 Asynchronous Timeout.
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Uint16 LT_MASK_SET:1; // 1 Line Trap.
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Uint16 WR_MASK_SET:4; // 5:2 Wait Rise.
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Uint16 rsvd1:10; // 15:6 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union INT_MSK_SET_REG {
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Uint32 all;
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struct INT_MSK_SET_BITS bit;
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};
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struct INT_MSK_CLR_BITS { // bits description
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Uint16 AT_MASK_CLR:1; // 0 Asynchronous Timeout.
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Uint16 LT_MASK_CLR:1; // 1 Line Trap.
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Uint16 WR_MASK_CLR:4; // 5:2 Wait Rise.
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Uint16 rsvd1:10; // 15:6 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union INT_MSK_CLR_REG {
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Uint32 all;
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struct INT_MSK_CLR_BITS bit;
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};
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struct EMIF_REGS {
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union RCSR_REG RCSR; // Revision Code and Status Register
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union ASYNC_WCCR_REG ASYNC_WCCR; // Async Wait Cycle Config Register
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union SDRAM_CR_REG SDRAM_CR; // SDRAM (EMxCS0n) Config Register
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union SDRAM_RCR_REG SDRAM_RCR; // SDRAM Refresh Control Register
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union ASYNC_CS2_CR_REG ASYNC_CS2_CR; // Async 1 (EMxCS2n) Config Register
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union ASYNC_CS3_CR_REG ASYNC_CS3_CR; // Async 2 (EMxCS3n) Config Register
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union ASYNC_CS4_CR_REG ASYNC_CS4_CR; // Async 3 (EMxCS4n) Config Register
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Uint16 rsvd1[2]; // Reserved
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union SDRAM_TR_REG SDRAM_TR; // SDRAM Timing Register
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Uint16 rsvd2[6]; // Reserved
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Uint32 TOTAL_SDRAM_AR; // Total SDRAM Accesses Register
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Uint32 TOTAL_SDRAM_ACTR; // Total SDRAM Activate Register
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Uint16 rsvd3[2]; // Reserved
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union SDR_EXT_TMNG_REG SDR_EXT_TMNG; // SDRAM SR/PD Exit Timing Register
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union INT_RAW_REG INT_RAW; // Interrupt Raw Register
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union INT_MSK_REG INT_MSK; // Interrupt Masked Register
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union INT_MSK_SET_REG INT_MSK_SET; // Interrupt Mask Set Register
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union INT_MSK_CLR_REG INT_MSK_CLR; // Interrupt Mask Clear Register
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};
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//---------------------------------------------------------------------------
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// EMIF External References & Function Declarations:
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//
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#ifdef CPU1
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extern volatile struct EMIF_REGS Emif1Regs;
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extern volatile struct EMIF_REGS Emif2Regs;
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#endif
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#ifdef CPU2
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extern volatile struct EMIF_REGS Emif1Regs;
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#endif
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif
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//===========================================================================
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// End of file.
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//===========================================================================
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