585 lines
15 KiB
C
585 lines
15 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_McBSP.c
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//
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// TITLE: F2837xD Device McBSP Initialization & Support Functions.
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//
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//###########################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//
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// Included Files
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//
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#include "F2837xD_device.h"
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#include "F2837xD_Examples.h"
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//
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// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate
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// generator (SRG) cycles required for the Mcbsp initialization routine.
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// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock
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// generator (CLKG) cycles required for the Mcbsp initialization routine.
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//
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//
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// Defines
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//
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#define CPU_SPD 200E6
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#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4)
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// for examples
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#define CLKGDV_VAL 1
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// # of CPU cycles in 2 SRG cycles-init delay
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#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ)
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// # of CPU cycles in 2 CLKG cycles-init delay
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#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL)))
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//
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// Function Prototypes
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//
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void delay_loop(void); // Delay function used for SRG initialization
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void clkg_delay_loop(void); // Delay function used for CLKG initialization
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//
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// InitMcbsp - This function initializes the McBSP to a known state.
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//
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void InitMcbspa(void)
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{
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//
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// Reset the McBSP
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// Disable all interrupts
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// Frame sync generator reset
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// Sample rate generator reset
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// Transmitter reset
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// Receiver reset
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//
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McbspaRegs.SPCR2.bit.FRST = 0;
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McbspaRegs.SPCR2.bit.GRST = 0;
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McbspaRegs.SPCR2.bit.XRST = 0;
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McbspaRegs.SPCR1.bit.RRST = 0;
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//
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// Enable loop back mode
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// This does not require external hardware
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//
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McbspaRegs.SPCR2.all = 0x0000;
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McbspaRegs.SPCR1.all = 0x8000;
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//
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// RX data delay is 1 bit
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// TX data delay is 1 bit
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//
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McbspaRegs.RCR2.bit.RDATDLY = 1;
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McbspaRegs.XCR2.bit.XDATDLY = 1;
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//
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// No clock sync for CLKG
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// Frame-synchronization period
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//
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McbspaRegs.SRGR2.bit.GSYNC = 0;
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McbspaRegs.SRGR2.bit.FPER = 320;
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//
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// Frame-synchronization pulses from
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// the sample rate generator
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//
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McbspaRegs.SRGR2.bit.FSGM = 1;
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//
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// Sample rate generator input clock is LSPCLK
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//
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McbspaRegs.SRGR2.bit.CLKSM = 1;
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McbspaRegs.PCR.bit.SCLKME = 0;
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//
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// Divide-down value for CLKG
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// Frame-synchronization pulse width
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//
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McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;
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clkg_delay_loop();
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McbspaRegs.SRGR1.bit.FWID = 1;
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//
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// CLKX is driven by the sample rate generator
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// Transmit frame synchronization generated by internal
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// sample rate generator
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//
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McbspaRegs.PCR.bit.CLKXM = 1;
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McbspaRegs.PCR.bit.FSXM = 1;
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//
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// Enable Sample rate generator and
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// wait at least 2 CLKG clock cycles
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//
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McbspaRegs.SPCR2.bit.GRST = 1;
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clkg_delay_loop();
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//
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// Release from reset
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// RX, TX and frame sync generator
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//
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McbspaRegs.SPCR2.bit.XRST = 1;
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McbspaRegs.SPCR1.bit.RRST = 1;
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McbspaRegs.SPCR2.bit.FRST = 1;
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}
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//
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// InitMcbspaInt - Enable TX and RX interrupts
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//
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void InitMcbspaInt(void)
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{
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// Reset TX and RX
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// Enable interrupts for TX and RX
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// Release TX and RX
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McbspaRegs.SPCR2.bit.XRST = 0;
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McbspaRegs.SPCR1.bit.RRST = 0;
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McbspaRegs.MFFINT.bit.XINT = 1;
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McbspaRegs.MFFINT.bit.RINT = 1;
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McbspaRegs.SPCR2.bit.XRST = 1;
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McbspaRegs.SPCR1.bit.RRST = 1;
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}
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//
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// InitMcbspa8bit - McBSP uses an 8-bit word for both TX and RX
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//
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void InitMcbspa8bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1 = 0;
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McbspaRegs.XCR1.bit.XWDLEN1 = 0;
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}
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//
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// InitMcbspa12bit - McBSP uses an 12-bit word for both TX and RX
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//
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void InitMcbspa12bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1 = 1;
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McbspaRegs.XCR1.bit.XWDLEN1 = 1;
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}
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//
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// InitMcbspa16bit - McBSP uses an 16-bit word for both TX and RX
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//
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void InitMcbspa16bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1 = 2;
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McbspaRegs.XCR1.bit.XWDLEN1 = 2;
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}
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//
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// InitMcbspa20bit - McBSP uses an 20-bit word for both TX and RX
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//
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void InitMcbspa20bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1 = 3;
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McbspaRegs.XCR1.bit.XWDLEN1 = 3;
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}
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//
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// InitMcbspa24bit - McBSP uses an 24-bit word for both TX and RX
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//
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void InitMcbspa24bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1 = 4;
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McbspaRegs.XCR1.bit.XWDLEN1 = 4;
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}
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//
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// InitMcbspa32bit - McBSP uses an 32-bit word for both TX and RX
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//
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void InitMcbspa32bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1 = 5;
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McbspaRegs.XCR1.bit.XWDLEN1 = 5;
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}
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//
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// InitMcbspaGpio - Assign GPIO pins to the McBSP peripheral
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// (Note: This function must be called from CPU1.)
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//
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void InitMcbspaGpio(void)
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{
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#ifdef CPU1
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EALLOW;
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//
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// This specifies which of the possible GPIO pins will be
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// McBSPA functional pins. Comment out unwanted connections.
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// Set qualification for selected input pins to asynchronous only
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// This will select asynchronous (no qualification) for the selected pins.
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//
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//
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// MDXA
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// GPIO20
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// GPIO84
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//
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GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2;
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//GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 3;
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//GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3;
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//
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// MDRA
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// GPIO21 with asynchronous qualification
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// GPIO85 with asynchronous qualification
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//
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GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2;
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GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3;
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//GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 3;
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//GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3;
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//GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3;
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//
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// MCLKXA
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// GPIO22 with asynchronous qualification
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// GPIO86 with asynchronous qualification
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//
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GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2;
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//GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3;
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//GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 3;
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//GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3;
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//GpioCtrlRegs.GPCQSEL2.bit.GPIO86 = 3;
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//
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// MCLKRA
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// Select one of the following
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// GPIO7 with asynchronous qualification
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// GPIO58 with asynchronous qualification
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//
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GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2;
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GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3;
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//GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1;
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//GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3;
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//
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// MFSXA
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// GPIO23 with asynchronous qualification
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// GPIO87 with asynchronous qualification
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//
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GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2;
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//GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3;
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//GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 3;
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//GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3;
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//GpioCtrlRegs.GPCQSEL2.bit.GPIO87 = 3;
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//
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// MFSRA
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// Select one of the following
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// GPIO5 with asynchronous qualification
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// GPIO59 with asynchronous qualification
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//
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GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2;
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GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3;
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//GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1;
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//GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3;
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EDIS;
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#endif
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}
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//
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// InitMcbspb - McBSPB initialization routine for examples
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//
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void InitMcbspb(void)
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{
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//
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// Reset the McBSP
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// Disable all interrupts
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// Frame sync generator reset
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// Sample rate generator reset
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// Transmitter reset
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// Receiver reset
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//
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McbspbRegs.SPCR2.bit.FRST = 0;
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McbspbRegs.SPCR2.bit.GRST = 0;
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McbspbRegs.SPCR2.bit.XRST = 0;
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McbspbRegs.SPCR1.bit.RRST = 0;
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//
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// Enable loop back mode
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// This does not require external hardware
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//
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McbspbRegs.SPCR2.all = 0x0000;
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McbspbRegs.SPCR1.all = 0x8000;
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//
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// RX data delay is 1 bit
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// TX data delay is 1 bit
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//
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McbspbRegs.RCR2.bit.RDATDLY = 1;
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McbspbRegs.XCR2.bit.XDATDLY = 1;
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//
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// No clock sync for CLKG
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// Frame-synchronization period
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//
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McbspbRegs.SRGR2.bit.GSYNC = 0;
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McbspbRegs.SRGR2.bit.FPER = 320;
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//
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// Frame-synchronization pulses from
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// the sample rate generator
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//
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McbspbRegs.SRGR2.bit.FSGM = 1;
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//
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// Sample rate generator input clock is LSPCLK
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//
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McbspbRegs.SRGR2.bit.CLKSM = 1;
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McbspbRegs.PCR.bit.SCLKME = 0;
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//
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// Divide-down value for CLKG
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// Frame-synchronization pulse width
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//
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McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;
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clkg_delay_loop();
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McbspbRegs.SRGR1.bit.FWID = 1;
|
||
|
|
|
||
|
|
//
|
||
|
|
// CLKX is driven by the sample rate generator
|
||
|
|
// Transmit frame synchronization generated by internal
|
||
|
|
// sample rate generator
|
||
|
|
//
|
||
|
|
McbspbRegs.PCR.bit.CLKXM = 1;
|
||
|
|
McbspbRegs.PCR.bit.FSXM = 1;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Enable Sample rate generator and
|
||
|
|
// wait at least 2 CLKG clock cycles
|
||
|
|
//
|
||
|
|
McbspbRegs.SPCR2.bit.GRST = 1;
|
||
|
|
clkg_delay_loop();
|
||
|
|
|
||
|
|
//
|
||
|
|
// Release from reset
|
||
|
|
// RX, TX and frame sync generator
|
||
|
|
//
|
||
|
|
McbspbRegs.SPCR2.bit.XRST = 1;
|
||
|
|
McbspbRegs.SPCR1.bit.RRST = 1;
|
||
|
|
McbspbRegs.SPCR2.bit.FRST = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// InitMcbspbInt - Enable TX and RX interrupts
|
||
|
|
//
|
||
|
|
void InitMcbspbInt(void)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Reset TX and RX
|
||
|
|
// Enable interrupts for TX and RX
|
||
|
|
// Release TX and RX
|
||
|
|
//
|
||
|
|
McbspbRegs.SPCR2.bit.XRST = 0;
|
||
|
|
McbspbRegs.SPCR1.bit.RRST = 0;
|
||
|
|
McbspbRegs.MFFINT.bit.XINT = 1;
|
||
|
|
McbspbRegs.MFFINT.bit.RINT = 1;
|
||
|
|
McbspbRegs.SPCR2.bit.XRST = 1;
|
||
|
|
McbspbRegs.SPCR1.bit.RRST = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// InitMcbspb8bit - McBSPB uses an 8-bit word for both TX and RX
|
||
|
|
//
|
||
|
|
void InitMcbspb8bit(void)
|
||
|
|
{
|
||
|
|
McbspbRegs.RCR1.bit.RWDLEN1 = 0;
|
||
|
|
McbspbRegs.XCR1.bit.XWDLEN1 = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// IniMcbspb12bit - McBSPB uses an 12-bit word for both TX and RX
|
||
|
|
//
|
||
|
|
void IniMcbspb12bit(void)
|
||
|
|
{
|
||
|
|
McbspbRegs.RCR1.bit.RWDLEN1 = 1;
|
||
|
|
McbspbRegs.XCR1.bit.XWDLEN1 = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// InitMcbspb16bit - McBSPB uses an 16-bit word for both TX and RX
|
||
|
|
//
|
||
|
|
void InitMcbspb16bit(void)
|
||
|
|
{
|
||
|
|
McbspbRegs.RCR1.bit.RWDLEN1 = 2;
|
||
|
|
McbspbRegs.XCR1.bit.XWDLEN1 = 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// InitMcbspb20bit - McBSPB uses an 20-bit word for both TX and RX
|
||
|
|
//
|
||
|
|
void InitMcbspb20bit(void)
|
||
|
|
{
|
||
|
|
McbspbRegs.RCR1.bit.RWDLEN1 = 3;
|
||
|
|
McbspbRegs.XCR1.bit.XWDLEN1 = 3;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// InitMcbspb24bit - McBSPB uses an 24-bit word for both TX and RX
|
||
|
|
//
|
||
|
|
void InitMcbspb24bit(void)
|
||
|
|
{
|
||
|
|
McbspbRegs.RCR1.bit.RWDLEN1 = 4;
|
||
|
|
McbspbRegs.XCR1.bit.XWDLEN1 = 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// InitMcbspb32bit - McBSPB uses an 32-bit word for both TX and RX
|
||
|
|
//
|
||
|
|
void InitMcbspb32bit(void)
|
||
|
|
{
|
||
|
|
McbspbRegs.RCR1.bit.RWDLEN1 = 5;
|
||
|
|
McbspbRegs.XCR1.bit.XWDLEN1 = 5;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// InitMcbspbGpio - Assign GPIO pins to the McBSP peripheral
|
||
|
|
// (Note: This function must be called from CPU1.)
|
||
|
|
//
|
||
|
|
void InitMcbspbGpio(void)
|
||
|
|
{
|
||
|
|
#ifdef CPU1
|
||
|
|
EALLOW;
|
||
|
|
|
||
|
|
//
|
||
|
|
// This specifies which of the possible GPIO pins will be
|
||
|
|
// McBSPB functional pins. Comment out unwanted connections.
|
||
|
|
// Set qualification for selected input pins to asynchronous only
|
||
|
|
// This will select asynchronous (no qualification) for the selected pins.
|
||
|
|
//
|
||
|
|
|
||
|
|
//
|
||
|
|
// Select one of the following for MDXB
|
||
|
|
// GPIO24
|
||
|
|
// GPIO84
|
||
|
|
//
|
||
|
|
//GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3;
|
||
|
|
GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 1;
|
||
|
|
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 2;
|
||
|
|
|
||
|
|
//
|
||
|
|
// MDRB
|
||
|
|
// GPIO13 with asynchronous qualification
|
||
|
|
// GPIO25 with asynchronous qualification
|
||
|
|
// GPIO85 with asynchronous qualification
|
||
|
|
//
|
||
|
|
//GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3;
|
||
|
|
//GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3;
|
||
|
|
//GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3;
|
||
|
|
//GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3;
|
||
|
|
GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 1;
|
||
|
|
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 2;
|
||
|
|
GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3;
|
||
|
|
|
||
|
|
//
|
||
|
|
// MCLKXB
|
||
|
|
// GPIO14 with asynchronous qualification
|
||
|
|
// GPIO26 with asynchronous qualification
|
||
|
|
// GPIO86 with asynchronous qualification
|
||
|
|
//
|
||
|
|
//GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3;
|
||
|
|
//GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3;
|
||
|
|
//GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3;
|
||
|
|
//GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3;
|
||
|
|
GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 1;
|
||
|
|
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 2;
|
||
|
|
GpioCtrlRegs.GPCQSEL2.bit.GPIO86= 3;
|
||
|
|
|
||
|
|
//
|
||
|
|
// MCLKRB
|
||
|
|
// Select one of the following
|
||
|
|
// GPIO3 with asynchronous qualification
|
||
|
|
// GPIO60 with asynchronous qualification
|
||
|
|
//
|
||
|
|
//GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3;
|
||
|
|
//GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3;
|
||
|
|
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1;
|
||
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3;
|
||
|
|
|
||
|
|
//
|
||
|
|
// MFSXB
|
||
|
|
// GPIO15 with asynchronous qualification
|
||
|
|
// GPIO27 with asynchronous qualification
|
||
|
|
// GPIO87 with asynchronous qualification
|
||
|
|
//
|
||
|
|
//GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3;
|
||
|
|
//GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3;
|
||
|
|
//GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3;
|
||
|
|
//GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3;
|
||
|
|
GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 1;
|
||
|
|
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 2;
|
||
|
|
GpioCtrlRegs.GPCQSEL2.bit.GPIO87= 3;
|
||
|
|
|
||
|
|
//
|
||
|
|
// MFSRB
|
||
|
|
// Select one of the following
|
||
|
|
// GPIO1 with asynchronous qualification
|
||
|
|
// GPIO61 with asynchronous qualification
|
||
|
|
//
|
||
|
|
//GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3;
|
||
|
|
//GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3;
|
||
|
|
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1;
|
||
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3;
|
||
|
|
|
||
|
|
EDIS;
|
||
|
|
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// delay_loop - Delay function (at least 2 SRG cycles)
|
||
|
|
// Required in McBSP initialization
|
||
|
|
//
|
||
|
|
void delay_loop(void)
|
||
|
|
{
|
||
|
|
long i;
|
||
|
|
for (i = 0; i < MCBSP_INIT_DELAY; i++) {}
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// clkg_delay_loop - Delay function (at least 2 CLKG cycles)
|
||
|
|
// Required in McBSP init
|
||
|
|
//
|
||
|
|
void clkg_delay_loop(void)
|
||
|
|
{
|
||
|
|
long i;
|
||
|
|
for (i = 0; i < MCBSP_CLKG_DELAY; i++) {}
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// End of file
|
||
|
|
//
|