324 lines
14 KiB
C
324 lines
14 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_mcbsp.h
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//
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// TITLE: Definitions for the MCBSP registers.
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//
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//###########################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_MCBSP_H
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#define F2837xD_MCBSP_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// MCBSP Individual Register Bit Definitions:
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struct DRR2_BITS { // bits description
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Uint16 HWLB:8; // 7:0 High word low byte
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Uint16 HWHB:8; // 15:8 High word high byte
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};
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union DRR2_REG {
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Uint16 all;
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struct DRR2_BITS bit;
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};
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struct DRR1_BITS { // bits description
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Uint16 LWLB:8; // 7:0 Low word low byte
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Uint16 LWHB:8; // 15:8 Low word high byte
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};
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union DRR1_REG {
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Uint16 all;
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struct DRR1_BITS bit;
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};
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struct DXR2_BITS { // bits description
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Uint16 HWLB:8; // 7:0 High word low byte
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Uint16 HWHB:8; // 15:8 High word high byte
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};
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union DXR2_REG {
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Uint16 all;
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struct DXR2_BITS bit;
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};
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struct DXR1_BITS { // bits description
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Uint16 LWLB:8; // 7:0 Low word low byte
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Uint16 LWHB:8; // 15:8 Low word high byte
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};
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union DXR1_REG {
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Uint16 all;
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struct DXR1_BITS bit;
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};
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struct SPCR2_BITS { // bits description
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Uint16 XRST:1; // 0 Transmitter reset
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Uint16 XRDY:1; // 1 Transmitter ready
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Uint16 XEMPTY:1; // 2 Transmitter empty
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Uint16 XSYNCERR:1; // 3 Transmit sync error INT flag
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Uint16 XINTM:2; // 5:4 Transmit Interupt mode bits
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Uint16 GRST:1; // 6 Sample rate generator reset
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Uint16 FRST:1; // 7 Frame sync logic reset
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Uint16 SOFT:1; // 8 SOFT bit
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Uint16 FREE:1; // 9 FREE bit
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Uint16 rsvd1:6; // 15:10 Reserved
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};
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union SPCR2_REG {
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Uint16 all;
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struct SPCR2_BITS bit;
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};
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struct SPCR1_BITS { // bits description
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Uint16 RRST:1; // 0 Receiver reset
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Uint16 RRDY:1; // 1 Receiver ready
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Uint16 RFULL:1; // 2 Receiver full
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Uint16 RSYNCERR:1; // 3 Receive sync error INT flag
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Uint16 RINTM:2; // 5:4 Receive Interupt mode bits
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Uint16 rsvd1:1; // 6 Reserved
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Uint16 DXENA:1; // 7 DX delay enable
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Uint16 rsvd2:3; // 10:8 Reserved
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Uint16 CLKSTP:2; // 12:11 Clock stop mode
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Uint16 RJUST:2; // 14:13 Rx sign extension and justification mode
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Uint16 DLB:1; // 15 Digital loopback
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};
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union SPCR1_REG {
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Uint16 all;
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struct SPCR1_BITS bit;
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};
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struct RCR2_BITS { // bits description
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Uint16 RDATDLY:2; // 1:0 Receive data delay
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Uint16 RFIG:1; // 2 Receive frame sync ignore
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Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects
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Uint16 RWDLEN2:3; // 7:5 Receive word length 2
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Uint16 RFRLEN2:7; // 14:8 Receive Frame length 2
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Uint16 RPHASE:1; // 15 Receive Phase
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};
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union RCR2_REG {
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Uint16 all;
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struct RCR2_BITS bit;
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};
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struct RCR1_BITS { // bits description
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Uint16 rsvd1:5; // 4:0 Reserved
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Uint16 RWDLEN1:3; // 7:5 Receive word length 1
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Uint16 RFRLEN1:7; // 14:8 Receive Frame length 1
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Uint16 rsvd2:1; // 15 Reserved
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};
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union RCR1_REG {
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Uint16 all;
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struct RCR1_BITS bit;
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};
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struct XCR2_BITS { // bits description
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Uint16 XDATDLY:2; // 1:0 Transmit data delay
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Uint16 XFIG:1; // 2 Transmit frame sync ignore
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Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects
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Uint16 XWDLEN2:3; // 7:5 Transmit word length 2
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Uint16 XFRLEN2:7; // 14:8 Transmit Frame length 2
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Uint16 XPHASE:1; // 15 Transmit Phase
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};
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union XCR2_REG {
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Uint16 all;
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struct XCR2_BITS bit;
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};
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struct XCR1_BITS { // bits description
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Uint16 rsvd1:5; // 4:0 Reserved
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Uint16 XWDLEN1:3; // 7:5 Transmit word length 1
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Uint16 XFRLEN1:7; // 14:8 Transmit Frame length 1
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Uint16 rsvd2:1; // 15 Reserved
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};
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union XCR1_REG {
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Uint16 all;
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struct XCR1_BITS bit;
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};
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struct SRGR2_BITS { // bits description
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Uint16 FPER:12; // 11:0 Frame-sync period
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Uint16 FSGM:1; // 12 Frame sync generator mode
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Uint16 CLKSM:1; // 13 Sample rate generator mode
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Uint16 rsvd1:1; // 14 Reserved
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Uint16 GSYNC:1; // 15 CLKG sync
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};
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union SRGR2_REG {
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Uint16 all;
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struct SRGR2_BITS bit;
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};
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struct SRGR1_BITS { // bits description
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Uint16 CLKGDV:8; // 7:0 CLKG divider
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Uint16 FWID:8; // 15:8 Frame width
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};
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union SRGR1_REG {
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Uint16 all;
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struct SRGR1_BITS bit;
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};
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struct MCR2_BITS { // bits description
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Uint16 XMCM:2; // 1:0 Transmit data delay
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Uint16 XCBLK:3; // 4:2 Transmit frame sync ignore
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Uint16 XPABLK:2; // 6:5 Transmit Companding Mode selects
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Uint16 XPBBLK:2; // 8:7 Transmit word length 2
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Uint16 XMCME:1; // 9 Transmit Frame length 2
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Uint16 rsvd1:6; // 15:10 Reserved
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};
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union MCR2_REG {
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Uint16 all;
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struct MCR2_BITS bit;
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};
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struct MCR1_BITS { // bits description
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Uint16 RMCM:1; // 0 Receive multichannel mode
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Uint16 rsvd1:1; // 1 Reserved
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Uint16 RCBLK:3; // 4:2 eceive current block
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Uint16 RPABLK:2; // 6:5 Receive partition A Block
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Uint16 RPBBLK:2; // 8:7 Receive partition B Block
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Uint16 RMCME:1; // 9 Receive multi-channel enhance mode
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Uint16 rsvd2:6; // 15:10 Reserved
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};
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union MCR1_REG {
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Uint16 all;
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struct MCR1_BITS bit;
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};
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struct PCR_BITS { // bits description
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Uint16 CLKRP:1; // 0 Receive Clock polarity
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Uint16 CLKXP:1; // 1 Transmit clock polarity
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Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
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Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
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Uint16 rsvd1:1; // 4 Reserved
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Uint16 rsvd2:1; // 5 Reserved
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Uint16 rsvd3:1; // 6 Reserved
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Uint16 SCLKME:1; // 7 Sample clock mode selection
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Uint16 CLKRM:1; // 8 Receiver Clock Mode
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Uint16 CLKXM:1; // 9 Transmit Clock Mode.
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Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
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Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
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Uint16 rsvd4:4; // 15:12 Reserved
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};
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union PCR_REG {
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Uint16 all;
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struct PCR_BITS bit;
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};
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struct MFFINT_BITS { // bits description
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Uint16 XINT:1; // 0 Enable for Receive Interrupt
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Uint16 rsvd1:1; // 1 Reserved
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Uint16 RINT:1; // 2 Enable for transmit Interrupt
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Uint16 rsvd2:13; // 15:3 Reserved
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};
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union MFFINT_REG {
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Uint16 all;
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struct MFFINT_BITS bit;
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};
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struct McBSP_REGS {
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union DRR2_REG DRR2; // Data receive register bits 31-16
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union DRR1_REG DRR1; // Data receive register bits 15-0
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union DXR2_REG DXR2; // Data transmit register bits 31-16
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union DXR1_REG DXR1; // Data transmit register bits 15-0
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union SPCR2_REG SPCR2; // Serial port control register 2
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union SPCR1_REG SPCR1; // Serial port control register 1
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union RCR2_REG RCR2; // Receive Control register 2
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union RCR1_REG RCR1; // Receive Control register 1
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union XCR2_REG XCR2; // Transmit Control register 2
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union XCR1_REG XCR1; // Transmit Control register 1
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union SRGR2_REG SRGR2; // Sample rate generator register 2
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union SRGR1_REG SRGR1; // Sample rate generator register 1
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union MCR2_REG MCR2; // Multi-channel control register 2
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union MCR1_REG MCR1; // Multi-channel control register 1
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Uint16 RCERA; // Receive channel enable partition A
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Uint16 RCERB; // Receive channel enable partition B
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Uint16 XCERA; // Transmit channel enable partition A
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Uint16 XCERB; // Transmit channel enable partition B
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union PCR_REG PCR; // Pin Control register
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Uint16 RCERC; // Receive channel enable partition C
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Uint16 RCERD; // Receive channel enable partition D
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Uint16 XCERC; // Transmit channel enable partition C
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Uint16 XCERD; // Transmit channel enable partition D
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Uint16 RCERE; // Receive channel enable partition E
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Uint16 RCERF; // Receive channel enable partition F
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Uint16 XCERE; // Transmit channel enable partition E
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Uint16 XCERF; // Transmit channel enable partition F
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Uint16 RCERG; // Receive channel enable partition G
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Uint16 RCERH; // Receive channel enable partition H
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Uint16 XCERG; // Transmit channel enable partition G
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Uint16 XCERH; // Transmit channel enable partition H
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Uint16 rsvd1[4]; // Reserved
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union MFFINT_REG MFFINT; // Interrupt enable
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};
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//---------------------------------------------------------------------------
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// MCBSP External References & Function Declarations:
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//
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#ifdef CPU1
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extern volatile struct McBSP_REGS McbspaRegs;
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extern volatile struct McBSP_REGS McbspbRegs;
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#endif
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#ifdef CPU2
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extern volatile struct McBSP_REGS McbspaRegs;
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extern volatile struct McBSP_REGS McbspbRegs;
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#endif
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif
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//===========================================================================
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// End of file.
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//===========================================================================
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