267 lines
10 KiB
C
267 lines
10 KiB
C
//###########################################################################
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//
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// FILE: F2837xD_sci.h
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//
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// TITLE: Definitions for the SCI registers.
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//
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//###########################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_SCI_H
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#define F2837xD_SCI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// SCI Individual Register Bit Definitions:
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struct SCICCR_BITS { // bits description
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Uint16 SCICHAR:3; // 2:0 Character length control
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Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
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Uint16 LOOPBKENA:1; // 4 Loop Back enable
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Uint16 PARITYENA:1; // 5 Parity enable
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Uint16 PARITY:1; // 6 Even or Odd Parity
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Uint16 STOPBITS:1; // 7 Number of Stop Bits
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Uint16 rsvd1:8; // 15:8 Reserved
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};
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union SCICCR_REG {
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Uint16 all;
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struct SCICCR_BITS bit;
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};
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struct SCICTL1_BITS { // bits description
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Uint16 RXENA:1; // 0 SCI receiver enable
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Uint16 TXENA:1; // 1 SCI transmitter enable
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Uint16 SLEEP:1; // 2 SCI sleep
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Uint16 TXWAKE:1; // 3 Transmitter wakeup method
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Uint16 rsvd1:1; // 4 Reserved
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Uint16 SWRESET:1; // 5 Software reset
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Uint16 RXERRINTENA:1; // 6 Receive error interrupt enable
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Uint16 rsvd2:9; // 15:7 Reserved
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};
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union SCICTL1_REG {
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Uint16 all;
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struct SCICTL1_BITS bit;
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};
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struct SCIHBAUD_BITS { // bits description
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Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD
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Uint16 rsvd1:8; // 15:8 Reserved
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};
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union SCIHBAUD_REG {
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Uint16 all;
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struct SCIHBAUD_BITS bit;
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};
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struct SCILBAUD_BITS { // bits description
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Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD
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Uint16 rsvd1:8; // 15:8 Reserved
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};
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union SCILBAUD_REG {
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Uint16 all;
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struct SCILBAUD_BITS bit;
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};
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struct SCICTL2_BITS { // bits description
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Uint16 TXINTENA:1; // 0 Transmit __interrupt enable
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Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
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Uint16 rsvd1:4; // 5:2 Reserved
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Uint16 TXEMPTY:1; // 6 Transmitter empty flag
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Uint16 TXRDY:1; // 7 Transmitter ready flag
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Uint16 rsvd2:8; // 15:8 Reserved
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};
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union SCICTL2_REG {
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Uint16 all;
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struct SCICTL2_BITS bit;
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};
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struct SCIRXST_BITS { // bits description
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Uint16 rsvd1:1; // 0 Reserved
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Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
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Uint16 PE:1; // 2 Parity error flag
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Uint16 OE:1; // 3 Overrun error flag
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Uint16 FE:1; // 4 Framing error flag
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Uint16 BRKDT:1; // 5 Break-detect flag
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Uint16 RXRDY:1; // 6 Receiver ready flag
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Uint16 RXERROR:1; // 7 Receiver error flag
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Uint16 rsvd2:8; // 15:8 Reserved
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};
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union SCIRXST_REG {
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Uint16 all;
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struct SCIRXST_BITS bit;
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};
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struct SCIRXEMU_BITS { // bits description
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Uint16 ERXDT:8; // 7:0 Receive emulation buffer data
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Uint16 rsvd1:8; // 15:8 Reserved
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};
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union SCIRXEMU_REG {
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Uint16 all;
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struct SCIRXEMU_BITS bit;
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};
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struct SCIRXBUF_BITS { // bits description
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Uint16 SAR:8; // 7:0 Receive Character bits
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Uint16 rsvd1:6; // 13:8 Reserved
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Uint16 SCIFFPE:1; // 14 Receiver error flag
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Uint16 SCIFFFE:1; // 15 Receiver error flag
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};
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union SCIRXBUF_REG {
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Uint16 all;
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struct SCIRXBUF_BITS bit;
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};
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struct SCITXBUF_BITS { // bits description
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Uint16 TXDT:8; // 7:0 Transmit data buffer
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Uint16 rsvd1:8; // 15:8 Reserved
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};
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union SCITXBUF_REG {
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Uint16 all;
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struct SCITXBUF_BITS bit;
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};
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struct SCIFFTX_BITS { // bits description
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Uint16 TXFFIL:5; // 4:0 Interrupt level
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Uint16 TXFFIENA:1; // 5 Interrupt enable
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Uint16 TXFFINTCLR:1; // 6 Clear INT flag
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Uint16 TXFFINT:1; // 7 INT flag
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Uint16 TXFFST:5; // 12:8 FIFO status
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Uint16 TXFIFORESET:1; // 13 FIFO reset
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Uint16 SCIFFENA:1; // 14 Enhancement enable
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Uint16 SCIRST:1; // 15 SCI reset rx/tx channels
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};
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union SCIFFTX_REG {
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Uint16 all;
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struct SCIFFTX_BITS bit;
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};
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struct SCIFFRX_BITS { // bits description
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Uint16 RXFFIL:5; // 4:0 Interrupt level
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Uint16 RXFFIENA:1; // 5 Interrupt enable
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Uint16 RXFFINTCLR:1; // 6 Clear INT flag
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Uint16 RXFFINT:1; // 7 INT flag
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Uint16 RXFFST:5; // 12:8 FIFO status
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Uint16 RXFIFORESET:1; // 13 FIFO reset
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Uint16 RXFFOVRCLR:1; // 14 Clear overflow
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Uint16 RXFFOVF:1; // 15 FIFO overflow
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};
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union SCIFFRX_REG {
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Uint16 all;
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struct SCIFFRX_BITS bit;
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};
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struct SCIFFCT_BITS { // bits description
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Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
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Uint16 rsvd1:5; // 12:8 Reserved
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Uint16 CDC:1; // 13 Auto baud mode enable
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Uint16 ABDCLR:1; // 14 Auto baud clear
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Uint16 ABD:1; // 15 Auto baud detect
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};
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union SCIFFCT_REG {
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Uint16 all;
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struct SCIFFCT_BITS bit;
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};
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struct SCIPRI_BITS { // bits description
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Uint16 rsvd1:3; // 2:0 Reserved
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Uint16 FREESOFT:2; // 4:3 Emulation modes
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Uint16 rsvd2:3; // 7:5 Reserved
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Uint16 rsvd3:8; // 15:8 Reserved
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};
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union SCIPRI_REG {
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Uint16 all;
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struct SCIPRI_BITS bit;
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};
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struct SCI_REGS {
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union SCICCR_REG SCICCR; // Communications control register
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union SCICTL1_REG SCICTL1; // Control register 1
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union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register
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union SCILBAUD_REG SCILBAUD; // Baud rate (low) register
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union SCICTL2_REG SCICTL2; // Control register 2
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union SCIRXST_REG SCIRXST; // Receive status register
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union SCIRXEMU_REG SCIRXEMU; // Receive emulation buffer register
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union SCIRXBUF_REG SCIRXBUF; // Receive data buffer
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Uint16 rsvd1; // Reserved
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union SCITXBUF_REG SCITXBUF; // Transmit data buffer
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union SCIFFTX_REG SCIFFTX; // FIFO transmit register
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union SCIFFRX_REG SCIFFRX; // FIFO receive register
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union SCIFFCT_REG SCIFFCT; // FIFO control register
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Uint16 rsvd2[2]; // Reserved
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union SCIPRI_REG SCIPRI; // SCI priority control
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};
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//---------------------------------------------------------------------------
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// SCI External References & Function Declarations:
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//
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#ifdef CPU1
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extern volatile struct SCI_REGS SciaRegs;
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extern volatile struct SCI_REGS ScibRegs;
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extern volatile struct SCI_REGS ScicRegs;
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extern volatile struct SCI_REGS ScidRegs;
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#endif
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#ifdef CPU2
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extern volatile struct SCI_REGS SciaRegs;
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extern volatile struct SCI_REGS ScibRegs;
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extern volatile struct SCI_REGS ScicRegs;
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extern volatile struct SCI_REGS ScidRegs;
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#endif
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif
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//===========================================================================
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// End of file.
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//===========================================================================
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