1101 lines
33 KiB
C
1101 lines
33 KiB
C
//###########################################################################
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//
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// FILE: F2837xD_DMA.c
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//
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// TITLE: F2837xD Device DMA Initialization & Support Functions.
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//
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//###########################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//
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// Included Files
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//
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#include "F2837xD_device.h"
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#include "F2837xD_Examples.h"
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//
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// DMAInitialize - This function initializes the DMA to a known state.
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//
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void DMAInitialize(void)
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{
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EALLOW;
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//
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// Perform a hard reset on DMA
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//
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DmaRegs.DMACTRL.bit.HARDRESET = 1;
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__asm (" nop"); // one NOP required after HARDRESET
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//
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// Allow DMA to run free on emulation suspend
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//
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DmaRegs.DEBUGCTRL.bit.FREE = 1;
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EDIS;
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}
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//
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// DMACH1AddrConfig - DMA Channel 1 Address Configuration
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//
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void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
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{
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EALLOW;
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//
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// Set up SOURCE address:
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//
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DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to
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// beginning of
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// source buffer
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DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
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//
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// Set up DESTINATION address:
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//
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DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to
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// beginning of
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// destination buffer
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DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
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EDIS;
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}
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//
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// DMACH1BurstConfig - DMA Channel 1 Burst size configuration
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//
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void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
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{
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EALLOW;
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//
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// Set up BURST registers:
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//
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DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1)
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// x-ferred in a burst.
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DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between
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// each word x-ferred.
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DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between
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// each word x-ferred.
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EDIS;
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}
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//
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// DMACH1TransferConfig - DMA Channel 1 Transfer size configuration
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//
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void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
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{
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EALLOW;
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//
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// Set up TRANSFER registers:
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//
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DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
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// DMA interrupt will occur after
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// completed transfer.
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DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored
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// when WRAP occurs.
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DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored
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// when WRAP occurs.
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EDIS;
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}
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//
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// DMACH1WrapConfig - DMA Channel 1 Wrap size configuration
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//
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void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
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int16 deswstep)
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{
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EALLOW;
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//
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// Set up WRAP registers:
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//
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DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
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DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap
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DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after
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// N bursts.
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DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap
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EDIS;
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}
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//
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// DMACH1ModeConfig - DMA Channel 1 Mode configuration
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//
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void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
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Uint16 cont, Uint16 synce, Uint16 syncsel,
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Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
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Uint16 chinte)
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{
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EALLOW;
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//
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// Set up MODE Register:
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// persel - Source select
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// PERINTSEL - Should be hard coded to channel, above now selects source
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// PERINTE - Peripheral interrupt enable
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// ONESHOT - Oneshot enable
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// CONTINUOUS - Continuous enable
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// OVRINTE - Enable/disable the overflow interrupt
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// DATASIZE - 16-bit/32-bit data size transfers
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// CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
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// CHINTE - Channel Interrupt to CPU enable
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//
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DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = persel;
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DmaRegs.CH1.MODE.bit.PERINTSEL = 1;
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DmaRegs.CH1.MODE.bit.PERINTE = perinte;
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DmaRegs.CH1.MODE.bit.ONESHOT = oneshot;
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DmaRegs.CH1.MODE.bit.CONTINUOUS = cont;
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DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte;
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DmaRegs.CH1.MODE.bit.DATASIZE = datasize;
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DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode;
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DmaRegs.CH1.MODE.bit.CHINTE = chinte;
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//
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// Clear any spurious flags: interrupt and sync error flags
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//
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DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;
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DmaRegs.CH1.CONTROL.bit.ERRCLR = 1;
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//
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// Initialize PIE vector for CPU interrupt:
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// Enable DMA CH1 interrupt in PIE
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//
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PieCtrlRegs.PIEIER7.bit.INTx1 = 1;
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EDIS;
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}
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//
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// StartDMACH1 - This function starts DMA Channel 1.
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//
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void StartDMACH1(void)
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{
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EALLOW;
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DmaRegs.CH1.CONTROL.bit.RUN = 1;
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EDIS;
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}
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//
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// DMACH2AddrConfig - DMA Channel 2 Address Configuration
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//
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void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
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{
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EALLOW;
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//
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// Set up SOURCE address:
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//
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DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to
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// beginning of
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// source buffer.
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DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
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//
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// Set up DESTINATION address:
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//
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DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
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// of destination
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// buffer.
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DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
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EDIS;
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}
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//
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// DMACH2BurstConfig - DMA Channel 2 Burst size configuration
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//
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void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
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{
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EALLOW;
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//
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// Set up BURST registers:
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//
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DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in
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// a burst.
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DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between
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// each word x-ferred.
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DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each
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// word x-ferred.
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EDIS;
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}
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//
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// DMACH2TransferConfig - DMA Channel 2 Transfer size Configuration
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//
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void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
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{
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EALLOW;
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//
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// Set up TRANSFER registers:
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//
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DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
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// DMA interrupt will occur after
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// completed transfer.
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DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when
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// WRAP occurs.
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DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when
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// WRAP occurs.
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EDIS;
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}
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//
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// DMACH2WrapConfig - DMA Channel 2 Wrap size configuration
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//
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void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
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int16 deswstep)
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{
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EALLOW;
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//
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// Set up WRAP registers:
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//
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DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
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DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap
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DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after
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// N bursts.
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DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap
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EDIS;
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}
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//
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// DMACH2ModeConfig - DMA Channel 2 Mode configuration
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//
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void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
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Uint16 cont, Uint16 synce, Uint16 syncsel,
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Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
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Uint16 chinte)
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{
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EALLOW;
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//
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// Set up MODE Register:
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// persel - Source select
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// PERINTSEL - Should be hard coded to channel, above now selects source
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// PERINTE - Peripheral interrupt enable
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// ONESHOT - Oneshot enable
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// CONTINUOUS - Continuous enable
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// OVRINTE - Enable/disable the overflow interrupt
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// DATASIZE - 16-bit/32-bit data size transfers
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// CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
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// CHINTE - Channel Interrupt to CPU enable
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//
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DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = persel;
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DmaRegs.CH2.MODE.bit.PERINTSEL = 2;
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DmaRegs.CH2.MODE.bit.PERINTE = perinte;
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DmaRegs.CH2.MODE.bit.ONESHOT = oneshot;
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DmaRegs.CH2.MODE.bit.CONTINUOUS = cont;
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DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte;
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DmaRegs.CH2.MODE.bit.DATASIZE = datasize;
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DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode;
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DmaRegs.CH2.MODE.bit.CHINTE = chinte;
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//
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// Clear any spurious flags: Interrupt flags and sync error flags
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//
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DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1;
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DmaRegs.CH2.CONTROL.bit.ERRCLR = 1;
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//
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// Initialize PIE vector for CPU interrupt:
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// Enable DMA CH2 interrupt in PIE
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//
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PieCtrlRegs.PIEIER7.bit.INTx2 = 1;
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EDIS;
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}
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//
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// StartDMACH2 - This function starts DMA Channel 2.
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//
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void StartDMACH2(void)
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{
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EALLOW;
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DmaRegs.CH2.CONTROL.bit.RUN = 1;
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EDIS;
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}
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//
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// DMACH3AddrConfig - DMA Channel 3 Address configuration
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//
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void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
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{
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EALLOW;
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//
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// Set up SOURCE address:
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//
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DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
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// of source buffer.
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DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
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//
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// Set up DESTINATION address:
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//
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DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
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// of destination
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// buffer.
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DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
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EDIS;
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}
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//
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// DMACH3BurstConfig - DMA Channel 3 burst size configuration
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//
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void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
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{
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EALLOW;
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//
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// Set up BURST registers:
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//
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DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in
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// a burst.
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DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between
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// each word x-ferred.
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DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each
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// word x-ferred.
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EDIS;
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}
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//
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// DMACH3TransferConfig - DMA channel 3 transfer size configuration
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//
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void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
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{
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EALLOW;
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//
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// Set up TRANSFER registers:
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//
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DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
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// DMA interrupt will occur after
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// completed transfer.
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DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when
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// WRAP occurs.
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DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when
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// WRAP occurs.
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EDIS;
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}
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//
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// DMACH3WrapConfig - DMA Channel 3 wrap size configuration
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//
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void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
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int16 deswstep)
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{
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EALLOW;
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//
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// Set up WRAP registers:
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//
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DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
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DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap
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DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N
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// bursts.
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DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap
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EDIS;
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}
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//
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// DMACH3ModeConfig - DMA Channel 3 mode configuration
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//
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void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
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Uint16 cont, Uint16 synce, Uint16 syncsel,
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Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
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Uint16 chinte)
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{
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EALLOW;
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//
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// Set up MODE Register:
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// persel - Source select
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// PERINTSEL - Should be hard coded to channel, above now selects source
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// PERINTE - Peripheral interrupt enable
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// ONESHOT - Oneshot enable
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// CONTINUOUS - Continuous enable
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// OVRINTE - Enable/disable the overflow interrupt
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// DATASIZE - 16-bit/32-bit data size transfers
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// CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
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// CHINTE - Channel Interrupt to CPU enable
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//
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DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH3 = persel;
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DmaRegs.CH3.MODE.bit.PERINTSEL = 3;
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DmaRegs.CH3.MODE.bit.PERINTE = perinte;
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DmaRegs.CH3.MODE.bit.ONESHOT = oneshot;
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DmaRegs.CH3.MODE.bit.CONTINUOUS = cont;
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DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte;
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DmaRegs.CH3.MODE.bit.DATASIZE = datasize;
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DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode;
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DmaRegs.CH3.MODE.bit.CHINTE = chinte;
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//
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// Clear any spurious flags: interrupt flags and sync error flags
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//
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DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1;
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DmaRegs.CH3.CONTROL.bit.ERRCLR = 1;
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//
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// Initialize PIE vector for CPU interrupt:
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// Enable DMA CH3 interrupt in PIE
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//
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PieCtrlRegs.PIEIER7.bit.INTx3 = 1;
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EDIS;
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}
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//
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// StartDMACH3 - This function starts DMA Channel 3.
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//
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void StartDMACH3(void)
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{
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EALLOW;
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DmaRegs.CH3.CONTROL.bit.RUN = 1;
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EDIS;
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}
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//
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// DMACH4AddrConfig - DMA Channel 4 address configuration
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//
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void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
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{
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EALLOW;
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//
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// Set up SOURCE address:
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//
|
|
DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
|
|
// of source buffer.
|
|
DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
|
|
|
//
|
|
// Set up DESTINATION address:
|
|
//
|
|
DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
|
|
// of destination
|
|
// buffer.
|
|
DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH4BurstConfig - DMA Channel 4 burst size configuration
|
|
//
|
|
void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up BURST registers:
|
|
//
|
|
DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in
|
|
// a burst.
|
|
DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between
|
|
// each word x-ferred.
|
|
DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each
|
|
// word x-ferred.
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH4TransferConfig - DMA channel 4 transfer size configuration
|
|
//
|
|
void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up TRANSFER registers:
|
|
//
|
|
DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
|
|
// DMA interrupt will occur after
|
|
// completed transfer.
|
|
DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when
|
|
// WRAP occurs.
|
|
DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when
|
|
// WRAP occurs.
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH4WrapConfig - DMA channel 4 wrap size configuration
|
|
//
|
|
void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
|
int16 deswstep)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up WRAP registers:
|
|
//
|
|
DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
|
DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
|
|
|
DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after
|
|
// N bursts.
|
|
DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH4ModeConfig - DMA Channel 4 mode configuration
|
|
//
|
|
void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
|
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
|
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
|
Uint16 chinte)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up MODE Register:
|
|
// persel - Source select
|
|
// PERINTSEL - Should be hard coded to channel, above now selects source
|
|
// PERINTE - Peripheral interrupt enable
|
|
// ONESHOT - Oneshot enable
|
|
// CONTINUOUS - Continuous enable
|
|
// OVRINTE - Enable/disable the overflow interrupt
|
|
// DATASIZE - 16-bit/32-bit data size transfers
|
|
// CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
|
|
// CHINTE - Channel Interrupt to CPU enable
|
|
//
|
|
DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH4 = persel;
|
|
DmaRegs.CH4.MODE.bit.PERINTSEL = 4;
|
|
DmaRegs.CH4.MODE.bit.PERINTE = perinte;
|
|
DmaRegs.CH4.MODE.bit.ONESHOT = oneshot;
|
|
DmaRegs.CH4.MODE.bit.CONTINUOUS = cont;
|
|
DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte;
|
|
DmaRegs.CH4.MODE.bit.DATASIZE = datasize;
|
|
DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode;
|
|
DmaRegs.CH4.MODE.bit.CHINTE = chinte;
|
|
|
|
//
|
|
// Clear any spurious flags: Interrupt flags and sync error flags
|
|
//
|
|
DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1;
|
|
DmaRegs.CH4.CONTROL.bit.ERRCLR = 1;
|
|
|
|
//
|
|
// Initialize PIE vector for CPU interrupt:
|
|
// Enable DMA CH4 interrupt in PIE
|
|
//
|
|
PieCtrlRegs.PIEIER7.bit.INTx4 = 1;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// StartDMACH4 - This function starts DMA Channel 4.
|
|
//
|
|
void StartDMACH4(void)
|
|
{
|
|
EALLOW;
|
|
DmaRegs.CH4.CONTROL.bit.RUN = 1;
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH5AddrConfig - DMA channel 5 address configuration
|
|
//
|
|
void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up SOURCE address:
|
|
//
|
|
DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
|
|
// of source buffer
|
|
DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
|
|
|
//
|
|
// Set up DESTINATION address:
|
|
//
|
|
DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
|
|
// of destination
|
|
// buffer.
|
|
DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH5BurstConfig - DMA Channel 5 burst size configuration
|
|
//
|
|
void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up BURST registers:
|
|
//
|
|
DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in
|
|
// a burst.
|
|
DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between
|
|
// each word x-ferred.
|
|
DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each
|
|
// word x-ferred.
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH5TransferConfig - DMA channel 5 transfer size configuration
|
|
//
|
|
void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up TRANSFER registers:
|
|
//
|
|
DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
|
|
// DMA interrupt will occur after
|
|
// completed transfer.
|
|
DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when
|
|
// WRAP occurs.
|
|
DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when
|
|
// WRAP occurs.
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH5WrapConfig - DMA Channel 5 wrap size configuration
|
|
//
|
|
void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
|
int16 deswstep)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up WRAP registers:
|
|
//
|
|
DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
|
DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
|
|
|
DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after
|
|
// N bursts.
|
|
DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH5ModeConfig - DMA Channel 5 mode configuration
|
|
//
|
|
void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
|
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
|
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
|
Uint16 chinte)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up MODE Register:
|
|
// persel - Source select
|
|
// PERINTSEL - Should be hard coded to channel, above now selects source
|
|
// PERINTE - Peripheral interrupt enable
|
|
// ONESHOT - Oneshot enable
|
|
// CONTINUOUS - Continuous enable
|
|
// OVRINTE - Enable/disable the overflow interrupt
|
|
// DATASIZE - 16-bit/32-bit data size transfers
|
|
// CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
|
|
// CHINTE - Channel Interrupt to CPU enable
|
|
//
|
|
DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH5 = persel;
|
|
DmaRegs.CH5.MODE.bit.PERINTSEL = 5;
|
|
DmaRegs.CH5.MODE.bit.PERINTE = perinte;
|
|
DmaRegs.CH5.MODE.bit.ONESHOT = oneshot;
|
|
DmaRegs.CH5.MODE.bit.CONTINUOUS = cont;
|
|
DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte;
|
|
DmaRegs.CH5.MODE.bit.DATASIZE = datasize;
|
|
DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode;
|
|
DmaRegs.CH5.MODE.bit.CHINTE = chinte;
|
|
|
|
//
|
|
// Clear any spurious flags: Interrupt flags and sync error flags
|
|
//
|
|
DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1;
|
|
DmaRegs.CH5.CONTROL.bit.ERRCLR = 1;
|
|
|
|
//
|
|
// Initialize PIE vector for CPU interrupt:
|
|
// Enable DMA CH5 interrupt in PIE
|
|
//
|
|
PieCtrlRegs.PIEIER7.bit.INTx5 = 1;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// StartDMACH5 - This function starts DMA Channel 5.
|
|
//
|
|
void StartDMACH5(void)
|
|
{
|
|
EALLOW;
|
|
DmaRegs.CH5.CONTROL.bit.RUN = 1;
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH6AddrConfig - DMA Channel 6 address configuration
|
|
//
|
|
void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up SOURCE address:
|
|
//
|
|
DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
|
|
// of source buffer.
|
|
DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
|
|
|
//
|
|
// Set up DESTINATION address:
|
|
//
|
|
DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
|
|
// of destination
|
|
// buffer.
|
|
DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH6BurstConfig - DMA Channel 6 burst size configuration
|
|
//
|
|
void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up BURST registers:
|
|
//
|
|
DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in
|
|
// a burst.
|
|
DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between
|
|
// each word x-ferred.
|
|
DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each
|
|
// word x-ferred.
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH6TransferConfig - DMA channel 6 transfer size configuration
|
|
//
|
|
void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up TRANSFER registers:
|
|
//
|
|
DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
|
|
// DMA interrupt will occur after
|
|
// completed transfer.
|
|
DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when
|
|
// WRAP occurs.
|
|
DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when
|
|
// WRAP occurs.
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH6WrapConfig - DMA Channel 6 wrap size configuration
|
|
//
|
|
void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
|
int16 deswstep)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up WRAP registers:
|
|
//
|
|
DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
|
DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
|
|
|
DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N
|
|
// bursts.
|
|
DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH6ModeConfig - DMA Channel 6 mode configuration
|
|
//
|
|
void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
|
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
|
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
|
Uint16 chinte)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up MODE Register:
|
|
// persel - Source select
|
|
// PERINTSEL - Should be hard coded to channel, above now selects source
|
|
// PERINTE - Peripheral interrupt enable
|
|
// ONESHOT - Oneshot enable
|
|
// CONTINUOUS - Continuous enable
|
|
// OVRINTE - Enable/disable the overflow interrupt
|
|
// DATASIZE - 16-bit/32-bit data size transfers
|
|
// CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
|
|
// CHINTE - Channel Interrupt to CPU enable
|
|
//
|
|
DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH6 = persel;
|
|
DmaRegs.CH6.MODE.bit.PERINTSEL = 6;
|
|
DmaRegs.CH6.MODE.bit.PERINTE = perinte;
|
|
DmaRegs.CH6.MODE.bit.ONESHOT = oneshot;
|
|
DmaRegs.CH6.MODE.bit.CONTINUOUS = cont;
|
|
DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte;
|
|
DmaRegs.CH6.MODE.bit.DATASIZE = datasize;
|
|
DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode;
|
|
DmaRegs.CH6.MODE.bit.CHINTE = chinte;
|
|
|
|
//
|
|
// Clear any spurious flags: Interrupt flags and sync error flags
|
|
//
|
|
DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1;
|
|
DmaRegs.CH6.CONTROL.bit.ERRCLR = 1;
|
|
|
|
//
|
|
// Initialize PIE vector for CPU interrupt:
|
|
// Enable DMA CH6 interrupt in PIE
|
|
//
|
|
PieCtrlRegs.PIEIER7.bit.INTx6 = 1;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// StartDMACH6 - This function starts DMA Channel 6.
|
|
//
|
|
void StartDMACH6(void)
|
|
{
|
|
EALLOW;
|
|
DmaRegs.CH6.CONTROL.bit.RUN = 1;
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// NOTE:
|
|
// Following functions are required for EMIF as the address is out of
|
|
// 22bit range
|
|
//
|
|
|
|
//
|
|
// DMACH1AddrConfig32bit - DMA Channel 1 address configuration for 32bit
|
|
//
|
|
void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
|
volatile Uint32 *DMA_Source)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up SOURCE address:
|
|
//
|
|
DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
|
|
// of source buffer
|
|
DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
|
|
|
//
|
|
// Set up DESTINATION address:
|
|
//
|
|
DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
|
|
// of destination
|
|
// buffer
|
|
DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH2AddrConfig32bit - DMA Channel 2 address configuration for 32bit
|
|
//
|
|
void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
|
volatile Uint32 *DMA_Source)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up SOURCE address:
|
|
//
|
|
DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
|
|
// of source buffer
|
|
DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
|
|
|
//
|
|
// Set up DESTINATION address:
|
|
//
|
|
DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
|
|
// of destination
|
|
// buffer
|
|
DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH3AddrConfig32bit - DMA Channel 3 address configuration for 32bit
|
|
//
|
|
void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
|
volatile Uint32 *DMA_Source)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up SOURCE address:
|
|
//
|
|
DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
|
|
// of source buffer
|
|
DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
|
|
|
//
|
|
// Set up DESTINATION address:
|
|
//
|
|
DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
|
|
// of destination
|
|
// buffer.
|
|
DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH4AddrConfig32bit - DMA Channel 4 address configuration for 32bit
|
|
//
|
|
void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
|
volatile Uint32 *DMA_Source)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up SOURCE address:
|
|
//
|
|
DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
|
|
// of source buffer
|
|
DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
|
|
|
//
|
|
// Set up DESTINATION address:
|
|
//
|
|
DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
|
|
// of destination
|
|
// buffer
|
|
DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH5AddrConfig32bit - DMA Channel 5 address configuration for 32bit
|
|
//
|
|
void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
|
volatile Uint32 *DMA_Source)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up SOURCE address:
|
|
//
|
|
DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
|
|
// of source buffer
|
|
DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
|
|
|
//
|
|
// Set up DESTINATION address:
|
|
//
|
|
DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
|
|
// of destination
|
|
// buffer
|
|
DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// DMACH6AddrConfig32bit - DMA Channel 6 address configuration for 32bit
|
|
//
|
|
void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
|
volatile Uint32 *DMA_Source)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up SOURCE address:
|
|
//
|
|
DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
|
|
// of source buffer
|
|
DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
|
|
|
//
|
|
// Set up DESTINATION address:
|
|
//
|
|
DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
|
|
// of destination
|
|
// buffer
|
|
DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//
|
|
// End of file
|
|
//
|