307 lines
20 KiB
C
307 lines
20 KiB
C
//###########################################################################
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//
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// FILE: F2837xD_pievect.h
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//
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// TITLE: F2837xD Device PIE Vector Table Definitions
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//
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//###########################################################################
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// $
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_PIE_VECT_H
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#define F2837xD_PIE_VECT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// PIE Interrupt Vector Table Definition:
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// Create a user type called PINT (pointer to interrupt):
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typedef __interrupt void (*PINT)(void);
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// Define Vector Table:
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struct PIE_VECT_TABLE {
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PINT PIE1_RESERVED_INT; // Reserved
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PINT PIE2_RESERVED_INT; // Reserved
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PINT PIE3_RESERVED_INT; // Reserved
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PINT PIE4_RESERVED_INT; // Reserved
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PINT PIE5_RESERVED_INT; // Reserved
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PINT PIE6_RESERVED_INT; // Reserved
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PINT PIE7_RESERVED_INT; // Reserved
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PINT PIE8_RESERVED_INT; // Reserved
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PINT PIE9_RESERVED_INT; // Reserved
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PINT PIE10_RESERVED_INT; // Reserved
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PINT PIE11_RESERVED_INT; // Reserved
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PINT PIE12_RESERVED_INT; // Reserved
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PINT PIE13_RESERVED_INT; // Reserved
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PINT TIMER1_INT; // CPU Timer 1 Interrupt
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PINT TIMER2_INT; // CPU Timer 2 Interrupt
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PINT DATALOG_INT; // Datalogging Interrupt
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PINT RTOS_INT; // RTOS Interrupt
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PINT EMU_INT; // Emulation Interrupt
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PINT NMI_INT; // Non-Maskable Interrupt
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PINT ILLEGAL_INT; // Illegal Operation Trap
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PINT USER1_INT; // User Defined Trap 1
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PINT USER2_INT; // User Defined Trap 2
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PINT USER3_INT; // User Defined Trap 3
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PINT USER4_INT; // User Defined Trap 4
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PINT USER5_INT; // User Defined Trap 5
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PINT USER6_INT; // User Defined Trap 6
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PINT USER7_INT; // User Defined Trap 7
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PINT USER8_INT; // User Defined Trap 8
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PINT USER9_INT; // User Defined Trap 9
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PINT USER10_INT; // User Defined Trap 10
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PINT USER11_INT; // User Defined Trap 11
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PINT USER12_INT; // User Defined Trap 12
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PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1
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PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1
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PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1
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PINT XINT1_INT; // 1.4 - XINT1 Interrupt
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PINT XINT2_INT; // 1.5 - XINT2 Interrupt
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PINT ADCD1_INT; // 1.6 - ADCD Interrupt 1
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PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt
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PINT WAKE_INT; // 1.8 - Standby and Halt Wakeup Interrupt
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PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt
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PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt
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PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt
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PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt
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PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt
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PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt
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PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt
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PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt
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PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt
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PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt
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PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt
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PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt
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PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt
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PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt
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PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt
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PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt
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PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt
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PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt
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PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt
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PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt
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PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt
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PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt
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PINT PIE14_RESERVED_INT; // 4.7 - Reserved
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PINT PIE15_RESERVED_INT; // 4.8 - Reserved
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PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt
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PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt
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PINT EQEP3_INT; // 5.3 - eQEP3 Interrupt
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PINT PIE16_RESERVED_INT; // 5.4 - Reserved
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PINT PIE17_RESERVED_INT; // 5.5 - Reserved
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PINT PIE18_RESERVED_INT; // 5.6 - Reserved
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PINT PIE19_RESERVED_INT; // 5.7 - Reserved
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PINT PIE20_RESERVED_INT; // 5.8 - Reserved
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PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt
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PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt
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PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt
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PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt
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PINT MCBSPA_RX_INT; // 6.5 - McBSPA Receive Interrupt
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PINT MCBSPA_TX_INT; // 6.6 - McBSPA Transmit Interrupt
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PINT MCBSPB_RX_INT; // 6.7 - McBSPB Receive Interrupt
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PINT MCBSPB_TX_INT; // 6.8 - McBSPB Transmit Interrupt
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PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt
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PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt
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PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt
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PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt
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PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt
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PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt
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PINT PIE21_RESERVED_INT; // 7.7 - Reserved
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PINT PIE22_RESERVED_INT; // 7.8 - Reserved
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PINT I2CA_INT; // 8.1 - I2CA Interrupt 1
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PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2
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PINT I2CB_INT; // 8.3 - I2CB Interrupt 1
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PINT I2CB_FIFO_INT; // 8.4 - I2CB Interrupt 2
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PINT SCIC_RX_INT; // 8.5 - SCIC Receive Interrupt
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PINT SCIC_TX_INT; // 8.6 - SCIC Transmit Interrupt
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PINT SCID_RX_INT; // 8.7 - SCID Receive Interrupt
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PINT SCID_TX_INT; // 8.8 - SCID Transmit Interrupt
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PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt
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PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt
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PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt
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PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt
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PINT CANA0_INT; // 9.5 - CANA Interrupt 0
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PINT CANA1_INT; // 9.6 - CANA Interrupt 1
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PINT CANB0_INT; // 9.7 - CANB Interrupt 0
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PINT CANB1_INT; // 9.8 - CANB Interrupt 1
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PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt
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PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2
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PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3
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PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4
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PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt
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PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2
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PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3
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PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4
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PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1
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PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2
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PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3
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PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4
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PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5
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PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6
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PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7
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PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8
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PINT XINT3_INT; // 12.1 - XINT3 Interrupt
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PINT XINT4_INT; // 12.2 - XINT4 Interrupt
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PINT XINT5_INT; // 12.3 - XINT5 Interrupt
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PINT PIE23_RESERVED_INT; // 12.4 - Reserved
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PINT PIE24_RESERVED_INT; // 12.5 - Reserved
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PINT VCU_INT; // 12.6 - VCU Interrupt
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PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt
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PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt
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PINT PIE25_RESERVED_INT; // 1.9 - Reserved
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PINT PIE26_RESERVED_INT; // 1.10 - Reserved
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PINT PIE27_RESERVED_INT; // 1.11 - Reserved
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PINT PIE28_RESERVED_INT; // 1.12 - Reserved
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PINT IPC0_INT; // 1.13 - IPC Interrupt 0
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PINT IPC1_INT; // 1.14 - IPC Interrupt 1
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PINT IPC2_INT; // 1.15 - IPC Interrupt 2
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PINT IPC3_INT; // 1.16 - IPC Interrupt 3
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PINT EPWM9_TZ_INT; // 2.9 - ePWM9 Trip Zone Interrupt
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PINT EPWM10_TZ_INT; // 2.10 - ePWM10 Trip Zone Interrupt
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PINT EPWM11_TZ_INT; // 2.11 - ePWM11 Trip Zone Interrupt
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PINT EPWM12_TZ_INT; // 2.12 - ePWM12 Trip Zone Interrupt
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PINT PIE29_RESERVED_INT; // 2.13 - Reserved
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PINT PIE30_RESERVED_INT; // 2.14 - Reserved
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PINT PIE31_RESERVED_INT; // 2.15 - Reserved
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PINT PIE32_RESERVED_INT; // 2.16 - Reserved
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PINT EPWM9_INT; // 3.9 - ePWM9 Interrupt
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PINT EPWM10_INT; // 3.10 - ePWM10 Interrupt
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PINT EPWM11_INT; // 3.11 - ePWM11 Interrupt
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PINT EPWM12_INT; // 3.12 - ePWM12 Interrupt
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PINT PIE33_RESERVED_INT; // 3.13 - Reserved
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PINT PIE34_RESERVED_INT; // 3.14 - Reserved
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PINT PIE35_RESERVED_INT; // 3.15 - Reserved
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PINT PIE36_RESERVED_INT; // 3.16 - Reserved
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PINT PIE37_RESERVED_INT; // 4.9 - Reserved
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PINT PIE38_RESERVED_INT; // 4.10 - Reserved
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PINT PIE39_RESERVED_INT; // 4.11 - Reserved
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PINT PIE40_RESERVED_INT; // 4.12 - Reserved
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PINT PIE41_RESERVED_INT; // 4.13 - Reserved
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PINT PIE42_RESERVED_INT; // 4.14 - Reserved
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PINT PIE43_RESERVED_INT; // 4.15 - Reserved
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PINT PIE44_RESERVED_INT; // 4.16 - Reserved
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PINT SD1_INT; // 5.9 - SD1 Interrupt
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PINT SD2_INT; // 5.10 - SD2 Interrupt
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PINT PIE45_RESERVED_INT; // 5.11 - Reserved
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PINT PIE46_RESERVED_INT; // 5.12 - Reserved
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PINT PIE47_RESERVED_INT; // 5.13 - Reserved
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PINT PIE48_RESERVED_INT; // 5.14 - Reserved
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PINT PIE49_RESERVED_INT; // 5.15 - Reserved
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PINT PIE50_RESERVED_INT; // 5.16 - Reserved
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PINT SPIC_RX_INT; // 6.9 - SPIC Receive Interrupt
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PINT SPIC_TX_INT; // 6.10 - SPIC Transmit Interrupt
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PINT PIE51_RESERVED_INT; // 6.11 - Reserved
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PINT PIE52_RESERVED_INT; // 6.12 - Reserved
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PINT PIE53_RESERVED_INT; // 6.13 - Reserved
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PINT PIE54_RESERVED_INT; // 6.14 - Reserved
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PINT PIE55_RESERVED_INT; // 6.15 - Reserved
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PINT PIE56_RESERVED_INT; // 6.16 - Reserved
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PINT PIE57_RESERVED_INT; // 7.9 - Reserved
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PINT PIE58_RESERVED_INT; // 7.10 - Reserved
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PINT PIE59_RESERVED_INT; // 7.11 - Reserved
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PINT PIE60_RESERVED_INT; // 7.12 - Reserved
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PINT PIE61_RESERVED_INT; // 7.13 - Reserved
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PINT PIE62_RESERVED_INT; // 7.14 - Reserved
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PINT PIE63_RESERVED_INT; // 7.15 - Reserved
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PINT PIE64_RESERVED_INT; // 7.16 - Reserved
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PINT PIE65_RESERVED_INT; // 8.9 - Reserved
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PINT PIE66_RESERVED_INT; // 8.10 - Reserved
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PINT PIE67_RESERVED_INT; // 8.11 - Reserved
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PINT PIE68_RESERVED_INT; // 8.12 - Reserved
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PINT PIE69_RESERVED_INT; // 8.13 - Reserved
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PINT PIE70_RESERVED_INT; // 8.14 - Reserved
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#ifdef CPU1
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PINT UPPA_INT; // 8.15 - uPPA Interrupt
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PINT PIE72_RESERVED_INT; // 8.16 - Reserved
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#elif defined(CPU2)
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PINT PIE71_RESERVED_INT; // 8.15 - Reserved
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PINT PIE72_RESERVED_INT; // 8.16 - Reserved
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#endif
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PINT PIE73_RESERVED_INT; // 9.9 - Reserved
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PINT PIE74_RESERVED_INT; // 9.10 - Reserved
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PINT PIE75_RESERVED_INT; // 9.11 - Reserved
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PINT PIE76_RESERVED_INT; // 9.12 - Reserved
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PINT PIE77_RESERVED_INT; // 9.13 - Reserved
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PINT PIE78_RESERVED_INT; // 9.14 - Reserved
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#ifdef CPU1
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PINT USBA_INT; // 9.15 - USBA Interrupt
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#elif defined(CPU2)
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PINT PIE79_RESERVED_INT; // 9.15 - Reserved
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#endif
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PINT PIE80_RESERVED_INT; // 9.16 - Reserved
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PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt
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PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2
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PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3
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PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4
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PINT ADCD_EVT_INT; // 10.13 - ADCD Event Interrupt
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PINT ADCD2_INT; // 10.14 - ADCD Interrupt 2
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PINT ADCD3_INT; // 10.15 - ADCD Interrupt 3
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PINT ADCD4_INT; // 10.16 - ADCD Interrupt 4
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PINT PIE81_RESERVED_INT; // 11.9 - Reserved
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PINT PIE82_RESERVED_INT; // 11.10 - Reserved
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PINT PIE83_RESERVED_INT; // 11.11 - Reserved
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PINT PIE84_RESERVED_INT; // 11.12 - Reserved
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PINT PIE85_RESERVED_INT; // 11.13 - Reserved
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PINT PIE86_RESERVED_INT; // 11.14 - Reserved
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PINT PIE87_RESERVED_INT; // 11.15 - Reserved
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PINT PIE88_RESERVED_INT; // 11.16 - Reserved
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PINT EMIF_ERROR_INT; // 12.9 - EMIF Error Interrupt
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PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt
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PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt
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PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt
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PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt
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PINT AUX_PLL_SLIP_INT; // 12.14 - Auxiliary PLL Slip Interrupt
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PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt
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PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt
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};
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//---------------------------------------------------------------------------
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// PieVect External References & Function Declarations:
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//
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extern volatile struct PIE_VECT_TABLE PieVectTable;
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of F2837xD_PIEVECT_H definition
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//===========================================================================
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// End of file.
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//===========================================================================
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