221 lines
9.9 KiB
C
221 lines
9.9 KiB
C
//###########################################################################
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//
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// FILE: F2837xD_dma.h
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//
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// TITLE: Definitions for the DMA registers.
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//
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//###########################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_DMA_H
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#define F2837xD_DMA_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// DMA Individual Register Bit Definitions:
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struct MODE_BITS { // bits description
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Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select
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Uint16 rsvd1:2; // 6:5 Reserved
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Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable
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Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable
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Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode
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Uint16 ONESHOT:1; // 10 One Shot Mode Bit
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Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit
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Uint16 rsvd2:1; // 12 Reserved
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Uint16 rsvd3:1; // 13 Reserved
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Uint16 DATASIZE:1; // 14 Data Size Mode Bit
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Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit
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};
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union MODE_REG {
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Uint16 all;
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struct MODE_BITS bit;
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};
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struct CONTROL_BITS { // bits description
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Uint16 RUN:1; // 0 Run Bit
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Uint16 HALT:1; // 1 Halt Bit
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Uint16 SOFTRESET:1; // 2 Soft Reset Bit
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Uint16 PERINTFRC:1; // 3 Interrupt Force Bit
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Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit
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Uint16 rsvd1:1; // 5 Reserved
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Uint16 rsvd2:1; // 6 Reserved
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Uint16 ERRCLR:1; // 7 Error Clear Bit
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Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit
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Uint16 rsvd3:1; // 9 Reserved
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Uint16 rsvd4:1; // 10 Reserved
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Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit
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Uint16 BURSTSTS:1; // 12 Burst Status Bit
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Uint16 RUNSTS:1; // 13 Run Status Bit
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Uint16 OVRFLG:1; // 14 Overflow Flag Bit
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Uint16 rsvd5:1; // 15 Reserved
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};
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union CONTROL_REG {
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Uint16 all;
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struct CONTROL_BITS bit;
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};
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struct BURST_SIZE_BITS { // bits description
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Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size
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Uint16 rsvd1:11; // 15:5 Reserved
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};
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union BURST_SIZE_REG {
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Uint16 all;
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struct BURST_SIZE_BITS bit;
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};
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struct BURST_COUNT_BITS { // bits description
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Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Size
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Uint16 rsvd1:11; // 15:5 Reserved
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};
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union BURST_COUNT_REG {
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Uint16 all;
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struct BURST_COUNT_BITS bit;
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};
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struct CH_REGS {
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union MODE_REG MODE; // Mode Register
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union CONTROL_REG CONTROL; // Control Register
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union BURST_SIZE_REG BURST_SIZE; // Burst Size Register
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union BURST_COUNT_REG BURST_COUNT; // Burst Count Register
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int16 SRC_BURST_STEP; // Source Burst Step Register
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int16 DST_BURST_STEP; // Destination Burst Step Register
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Uint16 TRANSFER_SIZE; // Transfer Size Register
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Uint16 TRANSFER_COUNT; // Transfer Count Register
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int16 SRC_TRANSFER_STEP; // Source Transfer Step Register
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int16 DST_TRANSFER_STEP; // Destination Transfer Step Register
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Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register
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Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register
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int16 SRC_WRAP_STEP; // Source Wrap Step Register
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Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register
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Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register
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int16 DST_WRAP_STEP; // Destination Wrap Step Register
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Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register
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Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register
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Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register
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Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register
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Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register
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Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register
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Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register
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Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register
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};
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struct DMACTRL_BITS { // bits description
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Uint16 HARDRESET:1; // 0 Hard Reset Bit
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Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit
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Uint16 rsvd1:14; // 15:2 Reserved
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};
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union DMACTRL_REG {
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Uint16 all;
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struct DMACTRL_BITS bit;
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};
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struct DEBUGCTRL_BITS { // bits description
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Uint16 rsvd1:15; // 14:0 Reserved
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Uint16 FREE:1; // 15 Debug Mode Bit
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};
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union DEBUGCTRL_REG {
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Uint16 all;
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struct DEBUGCTRL_BITS bit;
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};
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struct PRIORITYCTRL1_BITS { // bits description
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Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit
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Uint16 rsvd1:15; // 15:1 Reserved
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};
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union PRIORITYCTRL1_REG {
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Uint16 all;
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struct PRIORITYCTRL1_BITS bit;
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};
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struct PRIORITYSTAT_BITS { // bits description
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Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits
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Uint16 rsvd1:1; // 3 Reserved
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Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits
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Uint16 rsvd2:9; // 15:7 Reserved
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};
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union PRIORITYSTAT_REG {
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Uint16 all;
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struct PRIORITYSTAT_BITS bit;
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};
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struct DMA_REGS {
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union DMACTRL_REG DMACTRL; // DMA Control Register
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union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register
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Uint16 rsvd1[2]; // Reserved
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union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register
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Uint16 rsvd2; // Reserved
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union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register
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Uint16 rsvd3[25]; // Reserved
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struct CH_REGS CH1; // DMA Channel 1 Registers
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struct CH_REGS CH2; // DMA Channel 2 Registers
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struct CH_REGS CH3; // DMA Channel 3 Registers
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struct CH_REGS CH4; // DMA Channel 4 Registers
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struct CH_REGS CH5; // DMA Channel 5 Registers
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struct CH_REGS CH6; // DMA Channel 6 Registers
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};
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//---------------------------------------------------------------------------
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// DMA External References & Function Declarations:
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//
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#ifdef CPU1
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extern volatile struct DMA_REGS DmaRegs;
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#endif
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#ifdef CPU2
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extern volatile struct DMA_REGS DmaRegs;
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#endif
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif
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//===========================================================================
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// End of file.
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//===========================================================================
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