134 lines
5.3 KiB
C
134 lines
5.3 KiB
C
//#############################################################################
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//
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// FILE: F2837xD_Can_defines.h
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//
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// TITLE: Common defines used in CAN Test Cases
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//
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//#############################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2022 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//#############################################################################
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#ifndef F2837xD_CAN_DEFINES_H
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#define F2837xD_CAN_DEFINES_H
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#ifndef _DUAL_HEADERS
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#ifdef __cplusplus
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extern "C" {
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#endif
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//
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// Defines
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//
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//
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// Reset Values
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//
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#define CAN_RESET_VALUE_ZERO 0x00000000
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#define CAN_CTL_RESET_VALUE 0x00001401
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#define CAN_ES_RESET_VALUE 0x00000007
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#define CAN_BTR_RESET_VALUE 0x00002301
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#define CAN_REL_RESET_VALUE 0xA3170504
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#define CAN_RAM_INIT_RESET_VALUE 0x00000005
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#define CAN_IF_CMD_RESET_VALUE 0x00000001
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#define CAN_IF_MASK_RESET_VALUE 0xFFFFFFFF
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//
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// Register value when Peripheral Clock is Disabled
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//
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#define CAN_MODULE_CLK_DISABLE_VALUE 0x00000000
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//
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// Bit field definition of CAN_CTL register.
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//
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#define CAN_CTL_INIT 0x00000001 // Initialization
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#define CAN_CTL_IE0 0x00000002 // Interrupt Enable 0
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#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
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#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
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#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
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#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
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#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
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#define CAN_CTL_IDS 0x00000100 // Interruption Debug Support Enable
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#define CAN_CTL_ABO 0x00000200 // Auto-Bus On Enable
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#define CAN_CTL_PMD_S 10
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#define CAN_CTL_PMD_M 0x00003C00 // Parity/SECDED Enable
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#define CAN_CTL_SWR 0x00008000 // Software Reset Enable
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#define CAN_CTL_INITDBG 0x00010000 // Debug Mode Status
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#define CAN_CTL_IE1 0x00020000 // Interrupt Enable 1
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#define CAN_CTL_PDR 0x01000000 // Power Down Mode Request
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#define CAN_CTL_WUBA 0x02000000 // Wake Up on Bus Activity
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//
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// Bit field definition of CAN_IF1_CMD register.
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//
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#define CAN_IF1_CMD_MESSNUM_S 0
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#define CAN_IF1_CMD_MESSNUM_M 0x000000FF // Message Number
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#define CAN_IF1_CMD_BUSY 0x00008000 // Busy Flag
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#define CAN_IF1_CMD_DATAB 0x00010000 // Access Data B
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#define CAN_IF1_CMD_DATAA 0x00020000 // Access Data A
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#define CAN_IF1_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit
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#define CAN_IF1_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit
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#define CAN_IF1_CMD_CONTROL 0x00100000 // Access Control Bits
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#define CAN_IF1_CMD_ARB 0x00200000 // Access Arbitration Bits
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#define CAN_IF1_CMD_MASK 0x00400000 // Access Mask Bits
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#define CAN_IF1_CMD_WR_RD 0x00800000 // Write and Read
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//
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// Bit field definition of CAN_IF2_CMD register.
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//
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#define CAN_IF2_CMD_MESSNUM_S 0
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#define CAN_IF2_CMD_MESSNUM_M 0x000000FF // Message Number
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#define CAN_IF2_CMD_BUSY 0x00008000 // Busy Flag
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#define CAN_IF2_CMD_DATAB 0x00010000 // Access Data B
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#define CAN_IF2_CMD_DATAA 0x00020000 // Access Data A
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#define CAN_IF2_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit
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#define CAN_IF2_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit
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#define CAN_IF2_CMD_CONTROL 0x00100000 // Access Control Bits
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#define CAN_IF2_CMD_ARB 0x00200000 // Access Arbitration Bits
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#define CAN_IF2_CMD_MASK 0x00400000 // Access Mask Bits
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#define CAN_IF2_CMD_WR_RD 0x00800000 // Write and Read
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // - end of _DUAL_HEADERS
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#endif // - end of F2837xD_CAN_DEFINES_H
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//
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// End of file
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//
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