1159 lines
36 KiB
C
1159 lines
36 KiB
C
//###########################################################################
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//
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// FILE: dma.h
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//
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// TITLE: C28x DMA driver.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef DMA_H
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#define DMA_H
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//*****************************************************************************
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//
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// If building with a C++ compiler, make all of the definitions in this header
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// have a C binding.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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//! \addtogroup dma_api DMA
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//! \brief This module is used for DMA configurations.
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//! @{
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//
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//*****************************************************************************
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#include <stdbool.h>
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#include <stdint.h>
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#include "inc/hw_dma.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_sysctl.h"
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#include "inc/hw_types.h"
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#include "cpu.h"
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#include "debug.h"
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//*****************************************************************************
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//
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// Values that can be passed to DMA_configMode() as the config parameter.
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//
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//*****************************************************************************
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//! Only one burst transfer performed per trigger.
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#define DMA_CFG_ONESHOT_DISABLE 0U
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//! Burst transfers occur without additional event triggers after the first.
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#define DMA_CFG_ONESHOT_ENABLE DMA_MODE_ONESHOT
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//! DMA channel will be disabled at the end of a transfer.
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#define DMA_CFG_CONTINUOUS_DISABLE 0U
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//! DMA reinitializes when the transfer count is zero and waits for a trigger.
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#define DMA_CFG_CONTINUOUS_ENABLE DMA_MODE_CONTINUOUS
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//! DMA transfers 16 bits at a time.
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#define DMA_CFG_SIZE_16BIT 0U
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//! DMA transfers 32 bits at a time.
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#define DMA_CFG_SIZE_32BIT DMA_MODE_DATASIZE
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//*****************************************************************************
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//
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//! Values that can be passed to DMA_configMode() as the \e trigger parameter.
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//
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//*****************************************************************************
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typedef enum
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{
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DMA_TRIGGER_SOFTWARE = 0,
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DMA_TRIGGER_ADCA1 = 1,
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DMA_TRIGGER_ADCA2 = 2,
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DMA_TRIGGER_ADCA3 = 3,
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DMA_TRIGGER_ADCA4 = 4,
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DMA_TRIGGER_ADCAEVT = 5,
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DMA_TRIGGER_ADCB1 = 6,
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DMA_TRIGGER_ADCB2 = 7,
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DMA_TRIGGER_ADCB3 = 8,
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DMA_TRIGGER_ADCB4 = 9,
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DMA_TRIGGER_ADCBEVT = 10,
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DMA_TRIGGER_ADCC1 = 11,
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DMA_TRIGGER_ADCC2 = 12,
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DMA_TRIGGER_ADCC3 = 13,
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DMA_TRIGGER_ADCC4 = 14,
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DMA_TRIGGER_ADCCEVT = 15,
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DMA_TRIGGER_ADCD1 = 16,
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DMA_TRIGGER_ADCD2 = 17,
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DMA_TRIGGER_ADCD3 = 18,
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DMA_TRIGGER_ADCD4 = 19,
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DMA_TRIGGER_ADCDEVT = 20,
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DMA_TRIGGER_XINT1 = 29,
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DMA_TRIGGER_XINT2 = 30,
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DMA_TRIGGER_XINT3 = 31,
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DMA_TRIGGER_XINT4 = 32,
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DMA_TRIGGER_XINT5 = 33,
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DMA_TRIGGER_EPWM1SOCA = 36,
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DMA_TRIGGER_EPWM1SOCB = 37,
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DMA_TRIGGER_EPWM2SOCA = 38,
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DMA_TRIGGER_EPWM2SOCB = 39,
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DMA_TRIGGER_EPWM3SOCA = 40,
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DMA_TRIGGER_EPWM3SOCB = 41,
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DMA_TRIGGER_EPWM4SOCA = 42,
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DMA_TRIGGER_EPWM4SOCB = 43,
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DMA_TRIGGER_EPWM5SOCA = 44,
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DMA_TRIGGER_EPWM5SOCB = 45,
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DMA_TRIGGER_EPWM6SOCA = 46,
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DMA_TRIGGER_EPWM6SOCB = 47,
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DMA_TRIGGER_EPWM7SOCA = 48,
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DMA_TRIGGER_EPWM7SOCB = 49,
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DMA_TRIGGER_EPWM8SOCA = 50,
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DMA_TRIGGER_EPWM8SOCB = 51,
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DMA_TRIGGER_EPWM9SOCA = 52,
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DMA_TRIGGER_EPWM9SOCB = 53,
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DMA_TRIGGER_EPWM10SOCA = 54,
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DMA_TRIGGER_EPWM10SOCB = 55,
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DMA_TRIGGER_EPWM11SOCA = 56,
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DMA_TRIGGER_EPWM11SOCB = 57,
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DMA_TRIGGER_EPWM12SOCA = 58,
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DMA_TRIGGER_EPWM12SOCB = 59,
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DMA_TRIGGER_TINT0 = 68,
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DMA_TRIGGER_TINT1 = 69,
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DMA_TRIGGER_TINT2 = 70,
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DMA_TRIGGER_MCBSPAMXEVT = 71,
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DMA_TRIGGER_MCBSPAMREVT = 72,
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DMA_TRIGGER_MCBSPBMXEVT = 73,
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DMA_TRIGGER_MCBSPBMREVT = 74,
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DMA_TRIGGER_SDFM1FLT1 = 95,
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DMA_TRIGGER_SDFM1FLT2 = 96,
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DMA_TRIGGER_SDFM1FLT3 = 97,
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DMA_TRIGGER_SDFM1FLT4 = 98,
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DMA_TRIGGER_SDFM2FLT1 = 99,
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DMA_TRIGGER_SDFM2FLT2 = 100,
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DMA_TRIGGER_SDFM2FLT3 = 101,
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DMA_TRIGGER_SDFM2FLT4 = 102,
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DMA_TRIGGER_SPIATX = 109,
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DMA_TRIGGER_SPIARX = 110,
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DMA_TRIGGER_SPIBTX = 111,
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DMA_TRIGGER_SPIBRX = 112,
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DMA_TRIGGER_SPICTX = 113,
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DMA_TRIGGER_SPICRX = 114,
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DMA_TRIGGER_CLB1INT = 127,
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DMA_TRIGGER_CLB2INT = 128,
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DMA_TRIGGER_CLB3INT = 129,
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DMA_TRIGGER_CLB4INT = 130,
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} DMA_Trigger;
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//*****************************************************************************
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//
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//! Values that can be passed to DMA_setInterruptMode() as the \e mode
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//! parameter.
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//
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//*****************************************************************************
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typedef enum
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{
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//! DMA interrupt is generated at the beginning of a transfer
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DMA_INT_AT_BEGINNING,
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//! DMA interrupt is generated at the end of a transfer
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DMA_INT_AT_END
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} DMA_InterruptMode;
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//*****************************************************************************
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//
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//! Values that can be passed to DMA_setEmulationMode() as the \e mode
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//! parameter.
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//
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//*****************************************************************************
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typedef enum
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{
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//! Transmission stops after current read-write access is completed
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DMA_EMULATION_STOP,
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//! Continue DMA operation regardless of emulation suspend
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DMA_EMULATION_FREE_RUN
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} DMA_EmulationMode;
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//*****************************************************************************
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//
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//! Values that can be passed to DMA_configChannel() as the
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//! configure parameter.
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//
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//*****************************************************************************
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typedef struct
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{
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DMA_Trigger transferTrigger; //DMA transfer triggers
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DMA_InterruptMode interruptMode; //Channel interrupt mode
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bool enableInterrupt; //Enable/Disable interrupt mode
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uint32_t configSize; //Data bus width (16 or 32 bits)
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uint32_t transferMode; //Burst transfer mode
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uint32_t reinitMode; //DMA reinitialization mode
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uint32_t burstSize; //Number of words transferred per burst
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uint32_t transferSize; //Number of bursts per transfer
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//! Number of bursts to be transferred before a wrap of the source address
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//! occurs.
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uint32_t srcWrapSize;
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//! Number of bursts to be transferred before a wrap of the destination
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//! address occurs.
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uint32_t destWrapSize;
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uint32_t destAddr; //destination address
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uint32_t srcAddr; //source address
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//! Amount to inc or dec the source address after each word of a burst
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int16_t srcBurstStep;
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//! Amount to inc or dec the destination address after each word of a burst
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int16_t destBurstStep;
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//! Amount to inc or dec the source address after each burst of a transfer
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int16_t srcTransferStep;
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//! Amount to inc or dec the destination address after each burst of a
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//! transfer
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int16_t destTransferStep;
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//! Amount to inc or dec the source address when the wrap occurs
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int16_t srcWrapStep;
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//! Amount to inc or dec the destination address when the wrap occurs
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int16_t destWrapStep;
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} DMA_ConfigParams;
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//*****************************************************************************
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//
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// Prototypes for the APIs.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \internal
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//! Checks an DMA channel base address.
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//!
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//! \param base specifies the DMA channel base address.
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//!
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//! This function determines if a DMA channel base address is valid.
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//!
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//! \return Returns \b true if the base address is valid and \b false
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//! otherwise.
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//
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//*****************************************************************************
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#ifdef DEBUG
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static inline bool
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DMA_isBaseValid(uint32_t base)
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{
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return((base == DMA_CH1_BASE) || (base == DMA_CH2_BASE) ||
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(base == DMA_CH3_BASE) || (base == DMA_CH4_BASE) ||
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(base == DMA_CH5_BASE) || (base == DMA_CH6_BASE));
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}
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#endif
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//*****************************************************************************
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//
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//! Initializes the DMA controller to a known state.
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//!
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//! This function configures does a hard reset of the DMA controller in order
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//! to put it into a known state. The function also sets the DMA to run free
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//! during an emulation suspend (see the field DEBUGCTRL.FREE for more info).
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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DMA_initController(void)
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{
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EALLOW;
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//
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// Set the hard reset bit. One NOP is required after HARDRESET.
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//
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HWREGH(DMA_BASE + DMA_O_CTRL) |= DMA_CTRL_HARDRESET;
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NOP;
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EDIS;
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}
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//*****************************************************************************
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//
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//! Channel Soft Reset
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//!
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//! \param base is the base address of the DMA channel control registers.
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//!
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//! This function does a soft reset to place the channel into its default state
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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DMA_triggerSoftReset(uint32_t base)
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{
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EALLOW;
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//
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// Set the soft reset bit. One NOP is required after SOFTRESET.
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//
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HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_SOFTRESET;
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NOP;
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EDIS;
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}
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//*****************************************************************************
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//
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//! Sets DMA emulation mode.
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//!
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//! \param mode is the emulation mode to be selected.
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//!
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//! This function sets the behavior of the DMA operation when an emulation
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//! suspend occurs. The \e mode parameter can be one of the following:
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//!
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//! - \b DMA_EMULATION_STOP - DMA runs until the current read-write access is
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//! completed.
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//! - \b DMA_EMULATION_FREE_RUN - DMA operation continues regardless of a
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//! the suspend.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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DMA_setEmulationMode(DMA_EmulationMode mode)
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{
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EALLOW;
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//
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// Set emulation mode
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//
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if(mode == DMA_EMULATION_STOP)
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{
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HWREGH(DMA_BASE + DMA_O_DEBUGCTRL) &= ~DMA_DEBUGCTRL_FREE;
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}
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else
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{
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HWREGH(DMA_BASE + DMA_O_DEBUGCTRL) |= DMA_DEBUGCTRL_FREE;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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//! Enables peripherals to trigger a DMA transfer.
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//!
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//! \param base is the base address of the DMA channel control registers.
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//!
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//! This function enables the selected peripheral trigger to start a DMA
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//! transfer on the specified channel.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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DMA_enableTrigger(uint32_t base)
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{
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//
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// Check the arguments.
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//
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ASSERT(DMA_isBaseValid(base));
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//
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// Set the peripheral interrupt trigger enable bit.
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//
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EALLOW;
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HWREGH(base + DMA_O_MODE) |= DMA_MODE_PERINTE;
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EDIS;
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}
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//*****************************************************************************
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//
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//! Disables peripherals from triggering a DMA transfer.
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//!
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//! \param base is the base address of the DMA channel control registers.
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//!
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//! This function disables the selected peripheral trigger from starting a DMA
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//! transfer on the specified channel. This also disables the use of the
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//! software force using the DMA_forceTrigger() API.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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DMA_disableTrigger(uint32_t base)
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{
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//
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// Check the arguments.
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//
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ASSERT(DMA_isBaseValid(base));
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//
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// Clear the peripheral interrupt trigger enable bit.
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//
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EALLOW;
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HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_PERINTE;
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EDIS;
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}
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//*****************************************************************************
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//
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//! Force a peripheral trigger to a DMA channel.
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//!
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//! \param base is the base address of the DMA channel control registers.
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//!
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//! This function sets the peripheral trigger flag and if triggering a DMA
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//! burst is enabled (see DMA_enableTrigger()), a DMA burst transfer will be
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//! forced.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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DMA_forceTrigger(uint32_t base)
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{
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//
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// Check the arguments.
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//
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ASSERT(DMA_isBaseValid(base));
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//
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// Set the peripheral interrupt trigger force bit.
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//
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EALLOW;
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HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_PERINTFRC;
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EDIS;
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}
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//*****************************************************************************
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//
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//! Clears a DMA channel's peripheral trigger flag.
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//!
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//! \param base is the base address of the DMA channel control registers.
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//!
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//! This function clears the peripheral trigger flag. Normally, you would use
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//! this function when initializing the DMA for the first time. The flag is
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//! cleared automatically when the DMA starts the first burst of a transfer.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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DMA_clearTriggerFlag(uint32_t base)
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{
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//
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// Check the arguments.
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//
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ASSERT(DMA_isBaseValid(base));
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//
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// Write a one to the clear bit to clear the peripheral trigger flag.
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//
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EALLOW;
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HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_PERINTCLR;
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EDIS;
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}
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//*****************************************************************************
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//
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//! Gets the status of a DMA channel's Transfer Status Flag.
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//!
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//! \param base is the base address of the DMA channel control registers.
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//!
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//! This function returns \b true if the Transfer Status Flag is set, which
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//! means a DMA transfer has begun.
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//! This flag is cleared when TRANSFER_COUNT reaches zero, or when the
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//! HARDRESET or SOFTRESET bit is set.
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//!
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//! \return Returns \b true if the Transfer Status Flag is set. Returns \b false
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//! otherwise.
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//
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//*****************************************************************************
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static inline bool
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DMA_getTransferStatusFlag(uint32_t base)
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{
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//
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// Check the arguments.
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//
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ASSERT(DMA_isBaseValid(base));
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//
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// Read the Transfer Status Flag and return appropriately.
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//
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return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_TRANSFERSTS) != 0U);
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}
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//*****************************************************************************
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//
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//! Gets the status of a DMA channel's Burst Status Flag.
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//!
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//! \param base is the base address of the DMA channel control registers.
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//!
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//! This function returns \b true if the Burst Status Flag is set, which
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//! means a DMA burst has begun.
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//! This flag is cleared when BURST_COUNT reaches zero, or when the
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//! HARDRESET or SOFTRESET bit is set.
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//!
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//! \return Returns \b true if the Burst Status Flag is set. Returns \b false
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//! otherwise.
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//
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//*****************************************************************************
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static inline bool
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DMA_getBurstStatusFlag(uint32_t base)
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{
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//
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// Check the arguments.
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//
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ASSERT(DMA_isBaseValid(base));
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|
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//
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// Read the Burst Status Flag and return appropriately.
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//
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return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_BURSTSTS) != 0U);
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}
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|
|
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//*****************************************************************************
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//
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|
//! Gets the status of a DMA channel's Run Status Flag.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//!
|
|
//! This function returns \b true if the Run Status Flag is set, which
|
|
//! means the DMA channel is enabled.
|
|
//! This flag is cleared when a transfer completes (TRANSFER_COUNT = 0) and
|
|
//! continuous mode is disabled, or when the HARDRESET, SOFTRESET, or HALT bit
|
|
//! is set.
|
|
//!
|
|
//! \return Returns \b true if the channel is enabled. Returns \b false
|
|
//! otherwise.
|
|
//
|
|
//*****************************************************************************
|
|
static inline bool
|
|
DMA_getRunStatusFlag(uint32_t base)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
//
|
|
// Read the Run Status Flag and return appropriately.
|
|
//
|
|
return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_RUNSTS) != 0U);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the status of a DMA channel's Overflow Flag.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//!
|
|
//! This function returns \b true if the Overflow Flag is set, which
|
|
//! means peripheral event trigger was received while Peripheral Event Trigger
|
|
//! Flag was already set.
|
|
//! This flag can be cleared by writing to ERRCLR bit, using the function
|
|
//! DMA_clearErrorFlag().
|
|
//!
|
|
//! \return Returns \b true if the channel is enabled. Returns \b false
|
|
//! otherwise.
|
|
//
|
|
//*****************************************************************************
|
|
static inline bool
|
|
DMA_getOverflowFlag(uint32_t base)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
//
|
|
// Read the Overflow Flag and return appropriately.
|
|
//
|
|
return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_OVRFLG) != 0U);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the status of a DMA channel's peripheral trigger flag.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//!
|
|
//! This function returns \b true if a peripheral trigger event has occurred
|
|
//! The flag is automatically cleared when the first burst transfer begins, but
|
|
//! if needed, it can be cleared using DMA_clearTriggerFlag().
|
|
//!
|
|
//! \return Returns \b true if a peripheral trigger event has occurred and its
|
|
//! flag is set. Returns \b false otherwise.
|
|
//
|
|
//*****************************************************************************
|
|
static inline bool
|
|
DMA_getTriggerFlagStatus(uint32_t base)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
//
|
|
// Read the peripheral trigger flag and return appropriately.
|
|
//
|
|
return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_PERINTFLG) != 0U);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Starts a DMA channel.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//!
|
|
//! This function starts the DMA running, typically after you have configured
|
|
//! it. It will wait for the first trigger event to start operation. To halt
|
|
//! the channel use DMA_stopChannel().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
DMA_startChannel(uint32_t base)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
//
|
|
// Set the run bit.
|
|
//
|
|
EALLOW;
|
|
HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_RUN;
|
|
EDIS;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Halts a DMA channel.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//!
|
|
//! This function halts the DMA at its current state and any current read-write
|
|
//! access is completed. To start the channel again use DMA_startChannel().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
DMA_stopChannel(uint32_t base)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
//
|
|
// Set the halt bit.
|
|
//
|
|
EALLOW;
|
|
HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_HALT;
|
|
EDIS;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables a DMA channel interrupt source.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//!
|
|
//! This function enables the indicated DMA channel interrupt source.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
DMA_enableInterrupt(uint32_t base)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
//
|
|
// Enable the specified DMA channel interrupt.
|
|
//
|
|
EALLOW;
|
|
HWREGH(base + DMA_O_MODE) |= DMA_MODE_CHINTE;
|
|
EDIS;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables a DMA channel interrupt source.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//!
|
|
//! This function disables the indicated DMA channel interrupt source.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
DMA_disableInterrupt(uint32_t base)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
//
|
|
// Disable the specified DMA channel interrupt.
|
|
//
|
|
EALLOW;
|
|
HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_CHINTE;
|
|
EDIS;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables the DMA channel overrun interrupt.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//!
|
|
//! This function enables the indicated DMA channel's ability to generate an
|
|
//! interrupt upon the detection of an overrun. An overrun is when a peripheral
|
|
//! event trigger is received by the DMA before a previous trigger on that
|
|
//! channel had been serviced and its flag had been cleared.
|
|
//!
|
|
//! Note that this is the same interrupt signal as the interrupt that gets
|
|
//! generated at the beginning/end of a transfer. That interrupt must first be
|
|
//! enabled using DMA_enableInterrupt() in order for the overrun interrupt to
|
|
//! be generated.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
DMA_enableOverrunInterrupt(uint32_t base)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
//
|
|
// Enable the specified DMA channel interrupt.
|
|
//
|
|
EALLOW;
|
|
HWREGH(base + DMA_O_MODE) |= DMA_MODE_OVRINTE;
|
|
EDIS;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables the DMA channel overrun interrupt.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//!
|
|
//! This function disables the indicated DMA channel's ability to generate an
|
|
//! interrupt upon the detection of an overrun.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
DMA_disableOverrunInterrupt(uint32_t base)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
//
|
|
// Disable the specified DMA channel interrupt.
|
|
//
|
|
EALLOW;
|
|
HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_OVRINTE;
|
|
EDIS;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears the DMA channel error flags.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//!
|
|
//! This function clears both the DMA channel's sync error flag and its
|
|
//! overrun error flag.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
DMA_clearErrorFlag(uint32_t base)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
//
|
|
// Write to the error clear bit.
|
|
//
|
|
EALLOW;
|
|
HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_ERRCLR;
|
|
EDIS;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the interrupt generation mode of a DMA channel interrupt.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//! \param mode is a flag to indicate the channel interrupt mode.
|
|
//!
|
|
//! This function sets the channel interrupt mode. When the \e mode parameter
|
|
//! is \b DMA_INT_AT_END, the DMA channel interrupt will be generated at the
|
|
//! end of the transfer. If \b DMA_INT_AT_BEGINNING, the interrupt will be
|
|
//! generated at the beginning of a new transfer. Generating at the beginning
|
|
//! of a new transfer is the default behavior.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
DMA_setInterruptMode(uint32_t base, DMA_InterruptMode mode)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
EALLOW;
|
|
|
|
//
|
|
// Write the selected interrupt generation mode to the register.
|
|
//
|
|
if(mode == DMA_INT_AT_END)
|
|
{
|
|
HWREGH(base + DMA_O_MODE) |= DMA_MODE_CHINTMODE;
|
|
}
|
|
else
|
|
{
|
|
HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_CHINTMODE;
|
|
}
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the DMA channel priority mode.
|
|
//!
|
|
//! \param ch1IsHighPri is a flag to indicate the channel interrupt mode.
|
|
//!
|
|
//! This function sets the channel interrupt mode. When the \e ch1IsHighPri
|
|
//! parameter is \b false, the DMA channels are serviced in round-robin mode.
|
|
//! This is the default behavior.
|
|
//!
|
|
//! If \b true, channel 1 will be given higher priority than the other
|
|
//! channels. This means that if a channel 1 trigger occurs, the current word
|
|
//! transfer on any other channel is completed and channel 1 is serviced for
|
|
//! the complete burst count. The lower-priority channel's interrupted transfer
|
|
//! will then resume.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
DMA_setPriorityMode(bool ch1IsHighPri)
|
|
{
|
|
EALLOW;
|
|
|
|
//
|
|
// Write the selected priority mode to the register.
|
|
//
|
|
if(ch1IsHighPri)
|
|
{
|
|
HWREGH(DMA_BASE + DMA_O_PRIORITYCTRL1) |=
|
|
DMA_PRIORITYCTRL1_CH1PRIORITY;
|
|
}
|
|
else
|
|
{
|
|
HWREGH(DMA_BASE + DMA_O_PRIORITYCTRL1) &=
|
|
~DMA_PRIORITYCTRL1_CH1PRIORITY;
|
|
}
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Configures the source address for the DMA channel
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//! \param *srcAddr is a source address.
|
|
//!
|
|
//! This function configures the source address of a DMA
|
|
//! channel.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
DMA_configSourceAddress(uint32_t base, const void *srcAddr)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up SOURCE address.
|
|
//
|
|
HWREG(base + DMA_O_SRC_BEG_ADDR_SHADOW) = (uint32_t)srcAddr;
|
|
HWREG(base + DMA_O_SRC_ADDR_SHADOW) = (uint32_t)srcAddr;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Configures the destination address for the DMA channel
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//! \param *destAddr is the destination address.
|
|
//!
|
|
//! This function configures the destinaton address of a DMA
|
|
//! channel.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
DMA_configDestAddress(uint32_t base, const void *destAddr)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(DMA_isBaseValid(base));
|
|
|
|
EALLOW;
|
|
|
|
//
|
|
// Set up DESTINATION address.
|
|
//
|
|
HWREG(base + DMA_O_DST_BEG_ADDR_SHADOW) = (uint32_t)destAddr;
|
|
HWREG(base + DMA_O_DST_ADDR_SHADOW) = (uint32_t)destAddr;
|
|
|
|
EDIS;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Setup DMA to transfer data on the specified channel.
|
|
//!
|
|
//! \param base is Base address of the DMA channel control register
|
|
//! \param *transfParams configuration parameter
|
|
//! Refer struct #DMA_ConfigParams
|
|
//!
|
|
//! This function configures the DMA transfer on the specified channel.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
extern void
|
|
DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Configures the DMA channel
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//! \param *destAddr is the destination address.
|
|
//! \param *srcAddr is a source address.
|
|
//!
|
|
//! This function configures the source and destination addresses of a DMA
|
|
//! channel. The parameters are pointers to the data to be transferred.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
extern void
|
|
DMA_configAddresses(uint32_t base, const void *destAddr, const void *srcAddr);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Configures the DMA channel's burst settings.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//! \param size is the number of words transferred per burst.
|
|
//! \param srcStep is the amount to increment or decrement the source address
|
|
//! after each word of a burst.
|
|
//! \param destStep is the amount to increment or decrement the destination
|
|
//! address after each word of a burst.
|
|
//!
|
|
//! This function configures the size of each burst and the address step size.
|
|
//!
|
|
//! The \e size parameter is the number of words that will be transferred
|
|
//! during a single burst. Possible amounts range from 1 word to 32 words.
|
|
//!
|
|
//! The \e srcStep and \e destStep parameters specify the address step that
|
|
//! should be added to the source and destination addresses after each
|
|
//! transferred word of a burst. Only signed values from -4096 to 4095 are
|
|
//! valid.
|
|
//!
|
|
//! \note Note that regardless of what data size (configured by
|
|
//! DMA_configMode()) is used, parameters are in terms of 16-bits words.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
extern void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep,
|
|
int16_t destStep);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Configures the DMA channel's transfer settings.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//! \param transferSize is the number of bursts per transfer.
|
|
//! \param srcStep is the amount to increment or decrement the source address
|
|
//! after each burst of a transfer unless a wrap occurs.
|
|
//! \param destStep is the amount to increment or decrement the destination
|
|
//! address after each burst of a transfer unless a wrap occurs.
|
|
//!
|
|
//! This function configures the transfer size and the address step that is
|
|
//! made after each burst.
|
|
//!
|
|
//! The \e transferSize parameter is the number of bursts per transfer. If DMA
|
|
//! channel interrupts are enabled, they will occur after this number of bursts
|
|
//! have completed. The maximum number of bursts is 65536.
|
|
//!
|
|
//! The \e srcStep and \e destStep parameters specify the address step that
|
|
//! should be added to the source and destination addresses after each
|
|
//! transferred burst of a transfer. Only signed values from -4096 to 4095 are
|
|
//! valid. If a wrap occurs, these step values will be ignored. Wrapping is
|
|
//! configured with DMA_configWrap().
|
|
//!
|
|
//! \note Note that regardless of what data size (configured by
|
|
//! DMA_configMode()) is used, parameters are in terms of 16-bits words.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
extern void
|
|
DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep,
|
|
int16_t destStep);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Configures the DMA channel's wrap settings.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//! \param srcWrapSize is the number of bursts to be transferred before a wrap
|
|
//! of the source address occurs.
|
|
//! \param srcStep is the amount to increment or decrement the source address
|
|
//! after each burst of a transfer unless a wrap occurs.
|
|
//! \param destWrapSize is the number of bursts to be transferred before a wrap
|
|
//! of the destination address occurs.
|
|
//! \param destStep is the amount to increment or decrement the destination
|
|
//! address after each burst of a transfer unless a wrap occurs.
|
|
//!
|
|
//! This function configures the DMA channel's wrap settings.
|
|
//!
|
|
//! The \e srcWrapSize and \e destWrapSize parameters are the number of bursts
|
|
//! that are to be transferred before their respective addresses are wrapped.
|
|
//! The maximum wrap size is 65536 bursts.
|
|
//!
|
|
//! The \e srcStep and \e destStep parameters specify the address step that
|
|
//! should be added to the source and destination addresses when the wrap
|
|
//! occurs. Only signed values from -4096 to 4095 are valid.
|
|
//!
|
|
//! \note Note that regardless of what data size (configured by
|
|
//! DMA_configMode()) is used, parameters are in terms of 16-bits words.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
extern void
|
|
DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep,
|
|
uint32_t destWrapSize, int16_t destStep);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Configures the DMA channel trigger and mode.
|
|
//!
|
|
//! \param base is the base address of the DMA channel control registers.
|
|
//! \param trigger is the interrupt source that triggers a DMA transfer.
|
|
//! \param config is a bit field of several configuration selections.
|
|
//!
|
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//! This function configures the DMA channel's trigger and mode.
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//!
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//! The \e trigger parameter is the interrupt source that will trigger the
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//! start of a DMA transfer.
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//!
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//! The \e config parameter is the logical OR of the following values:
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//! - \b DMA_CFG_ONESHOT_DISABLE or \b DMA_CFG_ONESHOT_ENABLE. If enabled,
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//! the subsequent burst transfers occur without additional event triggers
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//! after the first event trigger. If disabled, only one burst transfer is
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//! performed per event trigger.
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//! - \b DMA_CFG_CONTINUOUS_DISABLE or \b DMA_CFG_CONTINUOUS_ENABLE. If enabled
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//! the DMA reinitializes when the transfer count is zero and waits for the
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//! next interrupt event trigger. If disabled, the DMA stops and clears the
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|
//! run status bit.
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//! - \b DMA_CFG_SIZE_16BIT or \b DMA_CFG_SIZE_32BIT. This setting selects
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//! whether the databus width is 16 or 32 bits.
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|
//!
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//! \return None.
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//
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//*****************************************************************************
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extern void
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|
DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config);
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|
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//*****************************************************************************
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|
//
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|
// Close the Doxygen group.
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|
//! @}
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|
//
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|
//*****************************************************************************
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|
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//*****************************************************************************
|
|
//
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|
// Mark the end of the C bindings section for C++ compilers.
|
|
//
|
|
//*****************************************************************************
|
|
#ifdef __cplusplus
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|
}
|
|
#endif
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|
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#endif // DMA_H
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