111 lines
5.1 KiB
C
111 lines
5.1 KiB
C
//###########################################################################
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//
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// FILE: hw_cputimer.h
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//
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// TITLE: Definitions for the CPUTIMER registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_CPUTIMER_H
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#define HW_CPUTIMER_H
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//*************************************************************************************************
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//
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// The following are defines for the CPUTIMER register offsets
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//
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//*************************************************************************************************
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#define CPUTIMER_O_TIM 0x0U // CPU-Timer, Counter Register
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#define CPUTIMER_O_PRD 0x2U // CPU-Timer, Period Register
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#define CPUTIMER_O_TCR 0x4U // CPU-Timer, Control Register
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#define CPUTIMER_O_TPR 0x6U // CPU-Timer, Prescale Register
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#define CPUTIMER_O_TPRH 0x7U // CPU-Timer, Prescale Register High
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the TIM register
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//
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//*************************************************************************************************
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#define CPUTIMER_TIM_LSW_S 0U
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#define CPUTIMER_TIM_LSW_M 0xFFFFU // CPU-Timer Counter Registers
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#define CPUTIMER_TIM_MSW_S 16U
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#define CPUTIMER_TIM_MSW_M 0xFFFF0000U // CPU-Timer Counter Registers High
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the PRD register
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//
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//*************************************************************************************************
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#define CPUTIMER_PRD_LSW_S 0U
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#define CPUTIMER_PRD_LSW_M 0xFFFFU // CPU-Timer Period Registers
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#define CPUTIMER_PRD_MSW_S 16U
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#define CPUTIMER_PRD_MSW_M 0xFFFF0000U // CPU-Timer Period Registers High
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the TCR register
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//
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//*************************************************************************************************
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#define CPUTIMER_TCR_TSS 0x10U // CPU-Timer stop status bit.
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#define CPUTIMER_TCR_TRB 0x20U // Timer reload
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#define CPUTIMER_TCR_SOFT 0x400U // Emulation modes
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#define CPUTIMER_TCR_FREE 0x800U // Emulation modes
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#define CPUTIMER_TCR_TIE 0x4000U // CPU-Timer Interrupt Enable.
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#define CPUTIMER_TCR_TIF 0x8000U // CPU-Timer Interrupt Flag.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the TPR register
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//
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//*************************************************************************************************
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#define CPUTIMER_TPR_TDDR_S 0U
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#define CPUTIMER_TPR_TDDR_M 0xFFU // CPU-Timer Divide-Down.
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#define CPUTIMER_TPR_PSC_S 8U
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#define CPUTIMER_TPR_PSC_M 0xFF00U // CPU-Timer Prescale Counter.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the TPRH register
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//
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//*************************************************************************************************
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#define CPUTIMER_TPRH_TDDRH_S 0U
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#define CPUTIMER_TPRH_TDDRH_M 0xFFU // CPU-Timer Divide-Down.
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#define CPUTIMER_TPRH_PSCH_S 8U
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#define CPUTIMER_TPRH_PSCH_M 0xFF00U // CPU-Timer Prescale Counter.
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#endif
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