156 lines
8.3 KiB
C
156 lines
8.3 KiB
C
//###########################################################################
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//
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// FILE: hw_ecap.h
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//
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// TITLE: Definitions for the ECAP registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_ECAP_H
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#define HW_ECAP_H
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//*************************************************************************************************
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//
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// The following are defines for the ECAP register offsets
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//
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//*************************************************************************************************
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#define ECAP_O_TSCTR 0x0U // Time-Stamp Counter
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#define ECAP_O_CTRPHS 0x2U // Counter Phase Offset Value Register
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#define ECAP_O_CAP1 0x4U // Capture 1 Register
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#define ECAP_O_CAP2 0x6U // Capture 2 Register
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#define ECAP_O_CAP3 0x8U // Capture 3 Register
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#define ECAP_O_CAP4 0xAU // Capture 4 Register
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#define ECAP_O_ECCTL1 0x14U // Capture Control Register 1
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#define ECAP_O_ECCTL2 0x15U // Capture Control Register 2
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#define ECAP_O_ECEINT 0x16U // Capture Interrupt Enable Register
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#define ECAP_O_ECFLG 0x17U // Capture Interrupt Flag Register
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#define ECAP_O_ECCLR 0x18U // Capture Interrupt Clear Register
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#define ECAP_O_ECFRC 0x19U // Capture Interrupt Force Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ECCTL1 register
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//
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//*************************************************************************************************
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#define ECAP_ECCTL1_CAP1POL 0x1U // Capture Event 1 Polarity select
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#define ECAP_ECCTL1_CTRRST1 0x2U // Counter Reset on Capture Event 1
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#define ECAP_ECCTL1_CAP2POL 0x4U // Capture Event 2 Polarity select
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#define ECAP_ECCTL1_CTRRST2 0x8U // Counter Reset on Capture Event 2
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#define ECAP_ECCTL1_CAP3POL 0x10U // Capture Event 3 Polarity select
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#define ECAP_ECCTL1_CTRRST3 0x20U // Counter Reset on Capture Event 3
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#define ECAP_ECCTL1_CAP4POL 0x40U // Capture Event 4 Polarity select
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#define ECAP_ECCTL1_CTRRST4 0x80U // Counter Reset on Capture Event 4
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#define ECAP_ECCTL1_CAPLDEN 0x100U // Enable Loading CAP1-4 regs on a Cap Event
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#define ECAP_ECCTL1_PRESCALE_S 9U
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#define ECAP_ECCTL1_PRESCALE_M 0x3E00U // Event Filter prescale select
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#define ECAP_ECCTL1_FREE_SOFT_S 14U
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#define ECAP_ECCTL1_FREE_SOFT_M 0xC000U // Emulation mode
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ECCTL2 register
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//
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//*************************************************************************************************
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#define ECAP_ECCTL2_CONT_ONESHT 0x1U // Continuous or one-shot
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#define ECAP_ECCTL2_STOP_WRAP_S 1U
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#define ECAP_ECCTL2_STOP_WRAP_M 0x6U // Stop value for one-shot, Wrap for continuous
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#define ECAP_ECCTL2_REARM 0x8U // One-shot re-arm
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#define ECAP_ECCTL2_TSCTRSTOP 0x10U // TSCNT counter stop
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#define ECAP_ECCTL2_SYNCI_EN 0x20U // Counter sync-in select
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#define ECAP_ECCTL2_SYNCO_SEL_S 6U
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#define ECAP_ECCTL2_SYNCO_SEL_M 0xC0U // Sync-out mode
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#define ECAP_ECCTL2_SWSYNC 0x100U // SW forced counter sync
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#define ECAP_ECCTL2_CAP_APWM 0x200U // CAP/APWM operating mode select
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#define ECAP_ECCTL2_APWMPOL 0x400U // APWM output polarity select
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ECEINT register
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//
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//*************************************************************************************************
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#define ECAP_ECEINT_CEVT1 0x2U // Capture Event 1 Interrupt Enable
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#define ECAP_ECEINT_CEVT2 0x4U // Capture Event 2 Interrupt Enable
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#define ECAP_ECEINT_CEVT3 0x8U // Capture Event 3 Interrupt Enable
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#define ECAP_ECEINT_CEVT4 0x10U // Capture Event 4 Interrupt Enable
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#define ECAP_ECEINT_CTROVF 0x20U // Counter Overflow Interrupt Enable
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#define ECAP_ECEINT_CTR_EQ_PRD 0x40U // Period Equal Interrupt Enable
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#define ECAP_ECEINT_CTR_EQ_CMP 0x80U // Compare Equal Interrupt Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ECFLG register
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//
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//*************************************************************************************************
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#define ECAP_ECFLG_INT 0x1U // Global Flag
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#define ECAP_ECFLG_CEVT1 0x2U // Capture Event 1 Interrupt Flag
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#define ECAP_ECFLG_CEVT2 0x4U // Capture Event 2 Interrupt Flag
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#define ECAP_ECFLG_CEVT3 0x8U // Capture Event 3 Interrupt Flag
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#define ECAP_ECFLG_CEVT4 0x10U // Capture Event 4 Interrupt Flag
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#define ECAP_ECFLG_CTROVF 0x20U // Counter Overflow Interrupt Flag
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#define ECAP_ECFLG_CTR_PRD 0x40U // Period Equal Interrupt Flag
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#define ECAP_ECFLG_CTR_CMP 0x80U // Compare Equal Interrupt Flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ECCLR register
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//
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//*************************************************************************************************
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#define ECAP_ECCLR_INT 0x1U // ECAP Global Interrupt Status Clear
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#define ECAP_ECCLR_CEVT1 0x2U // Capture Event 1 Status Clear
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#define ECAP_ECCLR_CEVT2 0x4U // Capture Event 2 Status Clear
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#define ECAP_ECCLR_CEVT3 0x8U // Capture Event 3 Status Clear
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#define ECAP_ECCLR_CEVT4 0x10U // Capture Event 4 Status Clear
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#define ECAP_ECCLR_CTROVF 0x20U // Counter Overflow Status Clear
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#define ECAP_ECCLR_CTR_PRD 0x40U // Period Equal Status Clear
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#define ECAP_ECCLR_CTR_CMP 0x80U // Compare Equal Status Clear
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ECFRC register
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//
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//*************************************************************************************************
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#define ECAP_ECFRC_CEVT1 0x2U // Capture Event 1 Force Interrupt
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#define ECAP_ECFRC_CEVT2 0x4U // Capture Event 2 Force Interrupt
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#define ECAP_ECFRC_CEVT3 0x8U // Capture Event 3 Force Interrupt
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#define ECAP_ECFRC_CEVT4 0x10U // Capture Event 4 Force Interrupt
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#define ECAP_ECFRC_CTROVF 0x20U // Counter Overflow Force Interrupt
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#define ECAP_ECFRC_CTR_PRD 0x40U // Period Equal Force Interrupt
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#define ECAP_ECFRC_CTR_CMP 0x80U // Compare Equal Force Interrupt
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#endif
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