285 lines
15 KiB
C
285 lines
15 KiB
C
//###########################################################################
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//
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// FILE: hw_flash.h
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//
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// TITLE: Definitions for the FLASH registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_FLASH_H
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#define HW_FLASH_H
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//*************************************************************************************************
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//
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// The following are defines for the FLASH register offsets
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//
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//*************************************************************************************************
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#define FLASH_O_FRDCNTL 0x0U // Flash Read Control Register
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#define FLASH_O_FBAC 0x1EU // Flash Bank Access Control Register
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#define FLASH_O_FBFALLBACK 0x20U // Flash Bank Fallback Power Register
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#define FLASH_O_FBPRDY 0x22U // Flash Bank Pump Ready Register
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#define FLASH_O_FPAC1 0x24U // Flash Pump Access Control Register 1
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#define FLASH_O_FMSTAT 0x2AU // Flash Module Status Register
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#define FLASH_O_FRD_INTF_CTRL 0x180U // Flash Read Interface Control Register
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#define FLASH_O_ECC_ENABLE 0x0U // ECC Enable
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#define FLASH_O_SINGLE_ERR_ADDR_LOW 0x2U // Single Error Address Low
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#define FLASH_O_SINGLE_ERR_ADDR_HIGH 0x4U // Single Error Address High
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#define FLASH_O_UNC_ERR_ADDR_LOW 0x6U // Uncorrectable Error Address Low
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#define FLASH_O_UNC_ERR_ADDR_HIGH 0x8U // Uncorrectable Error Address High
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#define FLASH_O_ERR_STATUS 0xAU // Error Status
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#define FLASH_O_ERR_POS 0xCU // Error Position
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#define FLASH_O_ERR_STATUS_CLR 0xEU // Error Status Clear
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#define FLASH_O_ERR_CNT 0x10U // Error Control
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#define FLASH_O_ERR_THRESHOLD 0x12U // Error Threshold
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#define FLASH_O_ERR_INTFLG 0x14U // Error Interrupt Flag
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#define FLASH_O_ERR_INTCLR 0x16U // Error Interrupt Flag Clear
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#define FLASH_O_FDATAH_TEST 0x18U // Data High Test
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#define FLASH_O_FDATAL_TEST 0x1AU // Data Low Test
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#define FLASH_O_FADDR_TEST 0x1CU // ECC Test Address
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#define FLASH_O_FECC_TEST 0x1EU // ECC Test Address
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#define FLASH_O_FECC_CTRL 0x20U // ECC Control
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#define FLASH_O_FOUTH_TEST 0x22U // Test Data Out High
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#define FLASH_O_FOUTL_TEST 0x24U // Test Data Out Low
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#define FLASH_O_FECC_STATUS 0x26U // ECC Status
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#define FLASH_O_PUMPREQUEST 0x0U // Flash programming semaphore PUMP request register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the FRDCNTL register
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//
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//*************************************************************************************************
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#define FLASH_FRDCNTL_RWAIT_S 8U
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#define FLASH_FRDCNTL_RWAIT_M 0xF00U // Random Read Waitstate
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the FBAC register
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//
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//*************************************************************************************************
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#define FLASH_FBAC_VREADST_S 0U
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#define FLASH_FBAC_VREADST_M 0xFFU // VREAD Setup Time Count
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the FBFALLBACK register
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//
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//*************************************************************************************************
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#define FLASH_FBFALLBACK_BNKPWR0_S 0U
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#define FLASH_FBFALLBACK_BNKPWR0_M 0x3U // Bank Power Mode
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the FBPRDY register
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//
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//*************************************************************************************************
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#define FLASH_FBPRDY_BANKRDY 0x1U // Flash Bank Active Power State
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#define FLASH_FBPRDY_PUMPRDY 0x8000U // Flash Pump Active Power Mode
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the FPAC1 register
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//
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//*************************************************************************************************
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#define FLASH_FPAC1_PMPPWR 0x1U // Charge Pump Fallback Power Mode
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#define FLASH_FPAC1_PSLEEP_S 16U
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#define FLASH_FPAC1_PSLEEP_M 0xFFF0000U // Pump Sleep Down Count
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the FMSTAT register
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//
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//*************************************************************************************************
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#define FLASH_FMSTAT_PSUSP 0x2U // Program Suspend.
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#define FLASH_FMSTAT_ESUSP 0x4U // Erase Suspend.
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#define FLASH_FMSTAT_VOLTSTAT 0x8U // Flash Pump Power Status
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#define FLASH_FMSTAT_CSTAT 0x10U // Command Fail Status
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#define FLASH_FMSTAT_INVDAT 0x20U // Invalid Data
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#define FLASH_FMSTAT_PGM 0x40U // Program Operation Status
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#define FLASH_FMSTAT_ERS 0x80U // Erase Operation Status
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#define FLASH_FMSTAT_BUSY 0x100U // Busy Bit
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#define FLASH_FMSTAT_EV 0x400U // Erase Verify Status
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#define FLASH_FMSTAT_PGV 0x1000U // Programming Verify Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the FRD_INTF_CTRL register
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//
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//*************************************************************************************************
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#define FLASH_FRD_INTF_CTRL_PREFETCH_EN 0x1U // Prefetch Enable
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#define FLASH_FRD_INTF_CTRL_DATA_CACHE_EN 0x2U // Data Cache Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ECC_ENABLE register
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//
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//*************************************************************************************************
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#define FLASH_ECC_ENABLE_ENABLE_S 0U
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#define FLASH_ECC_ENABLE_ENABLE_M 0xFU // Enable ECC
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ERR_STATUS register
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//
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//*************************************************************************************************
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#define FLASH_ERR_STATUS_FAIL_0_L 0x1U // Lower 64bits Single Bit Error Corrected Value 0
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#define FLASH_ERR_STATUS_FAIL_1_L 0x2U // Lower 64bits Single Bit Error Corrected Value 1
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#define FLASH_ERR_STATUS_UNC_ERR_L 0x4U // Lower 64 bits Uncorrectable error occurred
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#define FLASH_ERR_STATUS_FAIL_0_H 0x10000U // Upper 64bits Single Bit Error Corrected Value 0
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#define FLASH_ERR_STATUS_FAIL_1_H 0x20000U // Upper 64bits Single Bit Error Corrected Value 1
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#define FLASH_ERR_STATUS_UNC_ERR_H 0x40000U // Upper 64 bits Uncorrectable error occurred
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ERR_POS register
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//
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//*************************************************************************************************
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#define FLASH_ERR_POS_ERR_POS_L_S 0U
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#define FLASH_ERR_POS_ERR_POS_L_M 0x3FU // Bit Position of Single bit Error in lower 64
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// bits
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#define FLASH_ERR_POS_ERR_TYPE_L 0x100U // Error Type in lower 64 bits
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#define FLASH_ERR_POS_ERR_POS_H_S 16U
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#define FLASH_ERR_POS_ERR_POS_H_M 0x3F0000U // Bit Position of Single bit Error in upper 64
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// bits
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#define FLASH_ERR_POS_ERR_TYPE_H 0x1000000U // Error Type in upper 64 bits
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ERR_STATUS_CLR register
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//
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//*************************************************************************************************
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#define FLASH_ERR_STATUS_CLR_FAIL_0_L_CLR 0x1U // Lower 64bits Single Bit Error Corrected
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// Value 0 Clear
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#define FLASH_ERR_STATUS_CLR_FAIL_1_L_CLR 0x2U // Lower 64bits Single Bit Error Corrected
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// Value 1 Clear
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#define FLASH_ERR_STATUS_CLR_UNC_ERR_L_CLR 0x4U // Lower 64 bits Uncorrectable error
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// occurred Clear
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#define FLASH_ERR_STATUS_CLR_FAIL_0_H_CLR 0x10000U // Upper 64bits Single Bit Error Corrected
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// Value 0 Clear
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#define FLASH_ERR_STATUS_CLR_FAIL_1_H_CLR 0x20000U // Upper 64bits Single Bit Error Corrected
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// Value 1 Clear
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#define FLASH_ERR_STATUS_CLR_UNC_ERR_H_CLR 0x40000U // Upper 64 bits Uncorrectable error
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// occurred Clear
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ERR_CNT register
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//
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//*************************************************************************************************
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#define FLASH_ERR_CNT_ERR_CNT_S 0U
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#define FLASH_ERR_CNT_ERR_CNT_M 0xFFFFU // Error counter
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ERR_THRESHOLD register
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//
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//*************************************************************************************************
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#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_S 0U
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#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_M 0xFFFFU // Error Threshold
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ERR_INTFLG register
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//
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//*************************************************************************************************
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#define FLASH_ERR_INTFLG_SINGLE_ERR_INTFLG 0x1U // Single Error Interrupt Flag
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#define FLASH_ERR_INTFLG_UNC_ERR_INTFLG 0x2U // Uncorrectable Interrupt Flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ERR_INTCLR register
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//
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//*************************************************************************************************
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#define FLASH_ERR_INTCLR_SINGLE_ERR_INTCLR 0x1U // Single Error Interrupt Flag Clear
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#define FLASH_ERR_INTCLR_UNC_ERR_INTCLR 0x2U // Uncorrectable Interrupt Flag Clear
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the FADDR_TEST register
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//
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//*************************************************************************************************
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#define FLASH_FADDR_TEST_ADDRL_S 3U
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#define FLASH_FADDR_TEST_ADDRL_M 0xFFF8U // ECC Address Low
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#define FLASH_FADDR_TEST_ADDRH_S 16U
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#define FLASH_FADDR_TEST_ADDRH_M 0x3F0000U // ECC Address High
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the FECC_TEST register
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//
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//*************************************************************************************************
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#define FLASH_FECC_TEST_ECC_S 0U
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#define FLASH_FECC_TEST_ECC_M 0xFFU // ECC Control Bits
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the FECC_CTRL register
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//
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//*************************************************************************************************
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#define FLASH_FECC_CTRL_ECC_TEST_EN 0x1U // Enable ECC Test Logic
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#define FLASH_FECC_CTRL_ECC_SELECT 0x2U // ECC Bit Select
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#define FLASH_FECC_CTRL_DO_ECC_CALC 0x4U // Enable ECC Calculation
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the FECC_STATUS register
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//
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//*************************************************************************************************
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#define FLASH_FECC_STATUS_SINGLE_ERR 0x1U // Test Result is Single Bit Error
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#define FLASH_FECC_STATUS_UNC_ERR 0x2U // Test Result is Uncorrectable Error
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#define FLASH_FECC_STATUS_DATA_ERR_POS_S 2U
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#define FLASH_FECC_STATUS_DATA_ERR_POS_M 0xFCU // Holds Bit Position of Error
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#define FLASH_FECC_STATUS_ERR_TYPE 0x100U // Holds Bit Position of 8 Check Bits of Error
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the PUMPREQUEST register
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//
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//*************************************************************************************************
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#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_S 0U
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#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_M 0x3U // Flash Pump Request Semaphore between
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// CPU1 and CPU2
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#define FLASH_PUMPREQUEST_KEY_S 16U
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#define FLASH_PUMPREQUEST_KEY_M 0xFFFF0000U // Key Qualifier for writes to this
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// register
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#endif
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