205 lines
9.1 KiB
C
205 lines
9.1 KiB
C
//###########################################################################
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//
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// FILE: hw_memmap.h
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//
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// TITLE: Macros defining the memory map of the C28x.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_MEMMAP_H
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#define HW_MEMMAP_H
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//*****************************************************************************
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//
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// The following are defines for the base address of the memories and
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// peripherals.
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//
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//*****************************************************************************
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#define M0_RAM_BASE 0x00000000U
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#define M1_RAM_BASE 0x00000400U
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#define ADCARESULT_BASE 0x00000B00U
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#define ADCBRESULT_BASE 0x00000B20U
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#define ADCCRESULT_BASE 0x00000B40U
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#define ADCDRESULT_BASE 0x00000B60U
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#define CPUTIMER0_BASE 0x00000C00U
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#define CPUTIMER1_BASE 0x00000C08U
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#define CPUTIMER2_BASE 0x00000C10U
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#define PIECTRL_BASE 0x00000CE0U
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#define PIEVECTTABLE_BASE 0x00000D00U
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#define DMA_BASE 0x00001000U
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#define DMA_CH1_BASE 0x00001020U
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#define DMA_CH2_BASE 0x00001040U
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#define DMA_CH3_BASE 0x00001060U
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#define DMA_CH4_BASE 0x00001080U
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#define DMA_CH5_BASE 0x000010A0U
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#define DMA_CH6_BASE 0x000010C0U
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#define CLA1_BASE 0x00001400U
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#define CLATOCPU_RAM_BASE 0x00001480U
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#define CPUTOCLA_RAM_BASE 0x00001500U
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#define CLB1_BASE 0x00003000U
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#define CLB1_LOGICCFG_BASE 0x00003000U
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#define CLB1_LOGICCTL_BASE 0x00003100U
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#define CLB1_DATAEXCH_BASE 0x00003200U
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#define CLB2_BASE 0x00003400U
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#define CLB2_LOGICCFG_BASE 0x00003400U
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#define CLB2_LOGICCTL_BASE 0x00003500U
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#define CLB2_DATAEXCH_BASE 0x00003600U
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#define CLB3_BASE 0x00003800U
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#define CLB3_LOGICCFG_BASE 0x00003800U
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#define CLB3_LOGICCTL_BASE 0x00003900U
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#define CLB3_DATAEXCH_BASE 0x00003A00U
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#define CLB4_BASE 0x00003C00U
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#define CLB4_LOGICCFG_BASE 0x00003C00U
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#define CLB4_LOGICCTL_BASE 0x00003D00U
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#define CLB4_DATAEXCH_BASE 0x00003E00U
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#define EPWM1_BASE 0x00004000U
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#define EPWM2_BASE 0x00004100U
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#define EPWM3_BASE 0x00004200U
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#define EPWM4_BASE 0x00004300U
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#define EPWM5_BASE 0x00004400U
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#define EPWM6_BASE 0x00004500U
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#define EPWM7_BASE 0x00004600U
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#define EPWM8_BASE 0x00004700U
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#define EPWM9_BASE 0x00004800U
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#define EPWM10_BASE 0x00004900U
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#define EPWM11_BASE 0x00004A00U
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#define EPWM12_BASE 0x00004B00U
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#define ECAP1_BASE 0x00005000U
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#define ECAP2_BASE 0x00005020U
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#define ECAP3_BASE 0x00005040U
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#define ECAP4_BASE 0x00005060U
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#define ECAP5_BASE 0x00005080U
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#define ECAP6_BASE 0x000050A0U
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#define EQEP1_BASE 0x00005100U
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#define EQEP2_BASE 0x00005140U
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#define EQEP3_BASE 0x00005180U
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#define DACA_BASE 0x00005C00U
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#define DACB_BASE 0x00005C10U
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#define DACC_BASE 0x00005C20U
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#define CMPSS1_BASE 0x00005C80U
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#define CMPSS2_BASE 0x00005CA0U
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#define CMPSS3_BASE 0x00005CC0U
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#define CMPSS4_BASE 0x00005CE0U
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#define CMPSS5_BASE 0x00005D00U
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#define CMPSS6_BASE 0x00005D20U
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#define CMPSS7_BASE 0x00005D40U
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#define CMPSS8_BASE 0x00005D60U
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#define SDFM1_BASE 0x00005E00U
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#define SDFM2_BASE 0x00005E80U
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#define MCBSPA_BASE 0x00006000U
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#define MCBSPB_BASE 0x00006040U
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#define SPIA_BASE 0x00006100U
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#define SPIB_BASE 0x00006110U
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#define SPIC_BASE 0x00006120U
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#define UPP_BASE 0x00006200U
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#define UPP_TX_MSG_RAM_BASE 0x00006C00U
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#define UPP_RX_MSG_RAM_BASE 0x00006E00U
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#define WD_BASE 0x00007000U
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#define NMI_BASE 0x00007060U
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#define XINT_BASE 0x00007070U
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#define SCIA_BASE 0x00007200U
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#define SCIB_BASE 0x00007210U
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#define SCIC_BASE 0x00007220U
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#define SCID_BASE 0x00007230U
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#define I2CA_BASE 0x00007300U
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#define I2CB_BASE 0x00007340U
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#define ADCA_BASE 0x00007400U
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#define ADCB_BASE 0x00007480U
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#define ADCC_BASE 0x00007500U
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#define ADCD_BASE 0x00007580U
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#define INPUTXBAR_BASE 0x00007900U
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#define XBAR_BASE 0x00007920U
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#define SYNCSOC_BASE 0x00007940U
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#define DMACLASRCSEL_BASE 0x00007980U
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#define EPWMXBAR_BASE 0x00007A00U
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#define CLBXBAR_BASE 0x00007A40U
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#define OUTPUTXBAR_BASE 0x00007A80U
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#define GPIOCTRL_BASE 0x00007C00U
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#define GPIODATA_BASE 0x00007F00U
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#define LS0_RAM_BASE 0x00008000U
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#define LS1_RAM_BASE 0x00008800U
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#define LS2_RAM_BASE 0x00009000U
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#define LS3_RAM_BASE 0x00009800U
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#define LS4_RAM_BASE 0x0000A000U
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#define LS5_RAM_BASE 0x0000A800U
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#define D0_RAM_BASE 0x0000B000U
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#define D1_RAM_BASE 0x0000B800U
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#define GS0_RAM_BASE 0x0000C000U
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#define GS1_RAM_BASE 0x0000D000U
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#define GS2_RAM_BASE 0x0000E000U
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#define GS3_RAM_BASE 0x0000F000U
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#define GS4_RAM_BASE 0x00010000U
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#define GS5_RAM_BASE 0x00011000U
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#define GS6_RAM_BASE 0x00012000U
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#define GS7_RAM_BASE 0x00013000U
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#define GS8_RAM_BASE 0x00014000U
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#define GS9_RAM_BASE 0x00015000U
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#define GS10_RAM_BASE 0x00016000U
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#define GS11_RAM_BASE 0x00017000U
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#define GS12_RAM_BASE 0x00018000U
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#define GS13_RAM_BASE 0x00019000U
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#define GS14_RAM_BASE 0x0001A000U
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#define GS15_RAM_BASE 0x0001B000U
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#define CPU2_TO_CPU1_MSG_RAM_BASE 0x0003F800U
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#define CPU1_TO_CPU2_MSG_RAM_BASE 0x0003FC00U
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#define USBA_BASE 0x00040000U
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#define EMIF1_BASE 0x00047000U
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#define EMIF2_BASE 0x00047800U
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#define CANA_BASE 0x00048000U
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#define CANA_MSG_RAM_BASE 0x00049000U
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#define CANB_BASE 0x0004A000U
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#define CANB_MSG_RAM_BASE 0x0004B000U
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#define IPC_BASE 0x00050000U
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#define FLASHPUMPSEMAPHORE_BASE 0x00050024U
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#define DEVCFG_BASE 0x0005D000U
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#define ANALOGSUBSYS_BASE 0x0005D180U
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#define CLKCFG_BASE 0x0005D200U
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#define CPUSYS_BASE 0x0005D300U
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#define ROMPREFETCH_BASE 0x0005E608U
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#define DCSM_Z1_BASE 0x0005F000U
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#define DCSM_Z2_BASE 0x0005F040U
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#define DCSMCOMMON_BASE 0x0005F070U
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#define MEMCFG_BASE 0x0005F400U
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#define EMIF1CONFIG_BASE 0x0005F480U
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#define EMIF2CONFIG_BASE 0x0005F4A0U
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#define ACCESSPROTECTION_BASE 0x0005F4C0U
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#define MEMORYERROR_BASE 0x0005F500U
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#define ROMWAITSTATE_BASE 0x0005F540U
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#define FLASH0CTRL_BASE 0x0005F800U
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#define FLASH0ECC_BASE 0x0005FB00U
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#define DCSM_Z1OTP_BASE 0x00078000U
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#define DCSM_Z2OTP_BASE 0x00078200U
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#endif
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