424 lines
11 KiB
C
424 lines
11 KiB
C
//###########################################################################
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//
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// FILE: interrupt.c
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//
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// TITLE: C28x Interrupt (PIE) driver.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#include "interrupt.h"
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//*****************************************************************************
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//
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//! \internal
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//! Clears the IFR flag in the CPU.
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//!
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//! \param group specifies the interrupt group to be cleared.
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//!
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//! This function clears the IFR flag. This switch is needed because the
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//! clearing of the IFR can only be done with a constant.
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//
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//*****************************************************************************
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static void Interrupt_clearIFR(uint16_t group)
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{
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switch(group)
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{
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case 0x0001U:
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IFR &= ~(uint16_t)0x0001U;
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break;
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case 0x0002U:
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IFR &= ~(uint16_t)0x0002U;
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break;
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case 0x0004U:
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IFR &= ~(uint16_t)0x0004U;
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break;
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case 0x0008U:
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IFR &= ~(uint16_t)0x0008U;
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break;
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case 0x0010U:
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IFR &= ~(uint16_t)0x0010U;
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break;
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case 0x0020U:
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IFR &= ~(uint16_t)0x0020U;
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break;
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case 0x0040U:
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IFR &= ~(uint16_t)0x0040U;
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break;
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case 0x0080U:
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IFR &= ~(uint16_t)0x0080U;
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break;
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case 0x0100U:
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IFR &= ~(uint16_t)0x0100U;
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break;
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case 0x0200U:
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IFR &= ~(uint16_t)0x0200U;
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break;
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case 0x0400U:
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IFR &= ~(uint16_t)0x0400U;
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break;
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case 0x0800U:
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IFR &= ~(uint16_t)0x0800U;
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break;
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case 0x1000U:
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IFR &= ~(uint16_t)0x1000U;
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break;
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case 0x2000U:
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IFR &= ~(uint16_t)0x2000U;
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break;
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case 0x4000U:
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IFR &= ~(uint16_t)0x4000U;
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break;
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case 0x8000U:
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IFR &= ~(uint16_t)0x8000U;
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break;
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default:
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//
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// Invalid group mask.
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//
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ASSERT((bool)false);
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break;
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}
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}
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//*****************************************************************************
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//
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// Interrupt_initModule
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//
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//*****************************************************************************
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void
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Interrupt_initModule(void)
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{
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//
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// Disable and clear all interrupts at the CPU
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//
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(void)Interrupt_disableGlobal();
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IER = 0x0000U;
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IFR = 0x0000U;
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//
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// Clear all PIEIER registers
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//
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HWREGH(PIECTRL_BASE + PIE_O_IER1) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IER2) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IER3) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IER4) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IER5) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IER6) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IER7) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IER8) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IER9) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IER10) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IER11) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IER12) = 0U;
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//
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// Clear all PIEIFR registers
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//
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HWREGH(PIECTRL_BASE + PIE_O_IFR1) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IFR2) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IFR3) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IFR4) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IFR5) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IFR6) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IFR7) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IFR8) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IFR9) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IFR10) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IFR11) = 0U;
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HWREGH(PIECTRL_BASE + PIE_O_IFR12) = 0U;
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//
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// Enable vector fetching from PIE block
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//
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HWREGH(PIECTRL_BASE + PIE_O_CTRL) |= PIE_CTRL_ENPIE;
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}
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//*****************************************************************************
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//
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//! The default interrupt handler.
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//!
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//! \return None.
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//
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//*****************************************************************************
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__interrupt void Interrupt_defaultHandler(void)
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{
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uint16_t pieVect;
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uint16_t vectID;
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//
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// Calculate the vector ID. If the vector is in the lower PIE, it's the
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// offset of the vector that was fetched (bits 7:1 of PIECTRL.PIEVECT)
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// divided by two.
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//
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pieVect = HWREGH(PIECTRL_BASE + PIE_O_CTRL);
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vectID = (pieVect & 0xFEU) >> 1U;
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//
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// If the vector is in the upper PIE, the vector ID is 128 or higher.
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//
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if(pieVect >= 0x0E00U)
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{
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vectID += 128U;
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}
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//
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// Something has gone wrong. An interrupt without a proper registered
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// handler function has occurred. To help you debug the issue, local
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// variable vectID contains the vector ID of the interrupt that occurred.
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//
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ESTOP0;
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for(;;)
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{
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;
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}
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}
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//*****************************************************************************
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//
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//! The default illegal instruction trap interrupt handler.
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//!
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//! \return None.
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//
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//*****************************************************************************
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__interrupt void Interrupt_illegalOperationHandler(void)
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{
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//
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// Something has gone wrong. The CPU has tried to execute an illegal
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// instruction, generating an illegal instruction trap (ITRAP).
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//
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ESTOP0;
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for(;;)
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{
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;
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}
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}
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//*****************************************************************************
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//
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//! The default non-maskable interrupt handler.
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//!
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//! \return None.
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//
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//*****************************************************************************
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__interrupt void Interrupt_nmiHandler(void)
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{
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//
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// A non-maskable interrupt has occurred, indicating that a hardware error
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// has occurred in the system. You can use SysCtl_getNMIFlagStatus() to
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// to read the NMIFLG register and determine what caused the NMI.
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//
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ESTOP0;
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for(;;)
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{
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;
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}
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}
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//*****************************************************************************
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//
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// Interrupt_initVectorTable
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//
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//*****************************************************************************
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void
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Interrupt_initVectorTable(void)
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{
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uint16_t i;
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EALLOW;
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//
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// We skip the first three locations because they are initialized by Boot
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// ROM with boot variables.
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//
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for(i = 3U; i < 224U; i++)
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{
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HWREG(PIEVECTTABLE_BASE + (2U * i)) =
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(uint32_t)Interrupt_defaultHandler;
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}
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//
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// NMI and ITRAP get their own handlers.
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//
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HWREG(PIEVECTTABLE_BASE + ((INT_NMI >> 16U) * 2U)) =
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(uint32_t)Interrupt_nmiHandler;
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HWREG(PIEVECTTABLE_BASE + ((INT_ILLEGAL >> 16U) * 2U)) =
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(uint32_t)Interrupt_illegalOperationHandler;
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EDIS;
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}
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//*****************************************************************************
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//
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//Interrupt_enable
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//
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//*****************************************************************************
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void
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Interrupt_enable(uint32_t interruptNumber)
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{
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bool intsDisabled;
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uint16_t intGroup;
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uint16_t groupMask;
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uint16_t vectID;
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vectID = (uint16_t)(interruptNumber >> 16U);
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//
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// Globally disable interrupts but save status
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//
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intsDisabled = Interrupt_disableGlobal();
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//
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// PIE Interrupts
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//
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if(vectID >= 0x20U)
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{
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intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U);
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groupMask = (uint16_t)1U << intGroup;
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HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) |=
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(uint16_t)1U << ((interruptNumber & 0xFFU) - 1U);
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//
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// Enable PIE Group Interrupt
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//
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IER |= groupMask;
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}
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//
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// INT13, INT14, DLOGINT, & RTOSINT
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//
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else if((vectID >= 0x0DU) && (vectID <= 0x10U))
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{
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IER |= (uint16_t)1U << (vectID - 1U);
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}
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else
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{
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//
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// Other interrupts
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//
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}
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//
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// Re-enable interrupts if they were enabled
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//
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if(!intsDisabled)
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{
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(void)Interrupt_enableGlobal();
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}
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}
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//*****************************************************************************
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//
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// Interrupt_disable
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//
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//*****************************************************************************
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void
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Interrupt_disable(uint32_t interruptNumber)
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{
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bool intsDisabled;
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uint16_t intGroup;
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uint16_t groupMask;
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uint16_t vectID;
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vectID = (uint16_t)(interruptNumber >> 16U);
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intsDisabled = Interrupt_disableGlobal();
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//
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// PIE Interrupts
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//
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if(vectID >= 0x20U)
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{
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intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U);
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groupMask = (uint16_t)1U << intGroup;
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//
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// Disable individual PIE interrupt
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//
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HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) &=
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~(1U << ((interruptNumber & 0xFFUL) - 1U));
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//
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// Wait for any pending interrupts to get to the CPU
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//
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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Interrupt_clearIFR(groupMask);
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//
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// Acknowledge any interrupts
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//
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HWREGH(PIECTRL_BASE + PIE_O_ACK) = groupMask;
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}
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//
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// INT13, INT14, DLOGINT, & RTOSINT
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//
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else if((vectID >= 0x0DU) && (vectID <= 0x10U))
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{
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IER &= ~((uint16_t)1U << (vectID - 1U));
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//
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// Wait for any pending interrupts to get to the CPU
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//
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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Interrupt_clearIFR((uint16_t)1U << (vectID - 1U));
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}
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else
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{
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//
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// Other interrupts
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//
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}
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//
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// Re-enable interrupts if they were enabled
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//
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if(!intsDisabled)
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{
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(void)Interrupt_enableGlobal();
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}
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}
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