700 lines
22 KiB
C
700 lines
22 KiB
C
//###########################################################################
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//
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// FILE: memcfg.c
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//
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// TITLE: C28x RAM config driver.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#include "memcfg.h"
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//*****************************************************************************
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//
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// MemCfg_lockConfig
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//
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//*****************************************************************************
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void
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MemCfg_lockConfig(uint32_t memSections)
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{
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//
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// Check the arguments.
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//
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ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
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(memSections == MEMCFG_SECT_ALL));
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//
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// Set the bit that blocks writes to the sections' configuration registers.
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//
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EALLOW;
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switch(memSections & MEMCFG_SECT_TYPE_MASK)
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{
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case MEMCFG_SECT_TYPE_D:
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HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK &
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memSections;
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break;
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case MEMCFG_SECT_TYPE_LS:
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK &
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memSections;
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break;
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case MEMCFG_SECT_TYPE_GS:
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK &
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memSections;
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break;
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case MEMCFG_SECT_TYPE_MASK:
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//
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// Lock configuration for all sections.
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//
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HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK &
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MEMCFG_SECT_DX_ALL;
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK &
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MEMCFG_SECT_LSX_ALL;
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK &
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MEMCFG_SECT_GSX_ALL;
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break;
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default:
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//
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// Do nothing. Invalid memSections. Make sure you aren't OR-ing
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// values for two different types of memory sections.
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//
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break;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// MemCfg_unlockConfig
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//
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//*****************************************************************************
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void
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MemCfg_unlockConfig(uint32_t memSections)
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{
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//
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// Check the arguments.
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//
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ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
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(memSections == MEMCFG_SECT_ALL));
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//
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// Clear the bit that blocks writes to the sections' configuration
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// registers.
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//
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EALLOW;
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switch(memSections & MEMCFG_SECT_TYPE_MASK)
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{
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case MEMCFG_SECT_TYPE_D:
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HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &= ~(MEMCFG_SECT_NUM_MASK &
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memSections);
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break;
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case MEMCFG_SECT_TYPE_LS:
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK &
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memSections);
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break;
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case MEMCFG_SECT_TYPE_GS:
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK &
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memSections);
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break;
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case MEMCFG_SECT_TYPE_MASK:
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//
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// Unlock configuration for all sections.
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//
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HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &=
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~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_DX_ALL));
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &=
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~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_LSX_ALL));
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &=
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~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_GSX_ALL));
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break;
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default:
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//
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// Do nothing. Invalid memSections. Make sure you aren't OR-ing
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// values for two different types of memory sections.
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//
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break;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// MemCfg_commitConfig
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//
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//*****************************************************************************
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void
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MemCfg_commitConfig(uint32_t memSections)
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{
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//
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// Check the arguments.
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//
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ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
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(memSections == MEMCFG_SECT_ALL));
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//
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// Set the bit that permanently blocks writes to the sections'
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// configuration registers.
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//
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EALLOW;
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switch(memSections & MEMCFG_SECT_TYPE_MASK)
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{
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case MEMCFG_SECT_TYPE_D:
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HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
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memSections;
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break;
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case MEMCFG_SECT_TYPE_LS:
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
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memSections;
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break;
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case MEMCFG_SECT_TYPE_GS:
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
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memSections;
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break;
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case MEMCFG_SECT_TYPE_MASK:
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//
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// Commit configuration for all sections.
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//
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HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
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MEMCFG_SECT_DX_ALL;
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
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MEMCFG_SECT_LSX_ALL;
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
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MEMCFG_SECT_GSX_ALL;
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break;
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default:
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//
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// Do nothing. Invalid memSections. Make sure you aren't OR-ing
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// values for two different types of RAM.
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//
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break;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// MemCfg_setProtection
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//
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//*****************************************************************************
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void
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MemCfg_setProtection(uint32_t memSection, uint32_t protectMode)
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{
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uint32_t shiftVal = 0U;
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uint32_t maskVal;
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uint32_t regVal;
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uint32_t sectionNum;
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uint32_t regOffset;
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//
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// Check the arguments.
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//
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ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
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((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
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((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS));
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//
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// Calculate how far the protect mode value needs to be shifted. Each
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// section number is represented by a bit in the lower word of memSection
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// and 8 bits in the corresponding ACCPROT register.
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//
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sectionNum = memSection & MEMCFG_SECT_NUM_MASK;
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while(sectionNum != 1U)
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{
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sectionNum = sectionNum >> 1U;
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shiftVal += 8U;
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}
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//
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// Calculate register offset. Also, make sure the shift value is no greater
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// than 31.
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//
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regOffset = (shiftVal & ~(0x1FU)) >> 4U;
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shiftVal &= 0x0001FU;
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maskVal = (uint32_t)MEMCFG_XACCPROTX_M << shiftVal;
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regVal = protectMode << shiftVal;
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//
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// Write the access protection mode into the appropriate field
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//
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EALLOW;
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switch(memSection & MEMCFG_SECT_TYPE_MASK)
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{
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case MEMCFG_SECT_TYPE_D:
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HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) &= ~maskVal;
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HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) |= regVal;
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break;
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case MEMCFG_SECT_TYPE_LS:
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) &= ~maskVal;
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) |= regVal;
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break;
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case MEMCFG_SECT_TYPE_GS:
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) &= ~maskVal;
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) |= regVal;
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break;
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default:
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//
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// Do nothing. Invalid memSection.
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//
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break;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// MemCfg_setLSRAMControllerSel
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//
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//*****************************************************************************
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void
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MemCfg_setLSRAMControllerSel(uint32_t ramSection,
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MemCfg_LSRAMControllerSel controllerSel)
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{
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uint32_t shiftVal;
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uint32_t temp;
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//
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// Check the arguments.
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//
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ASSERT((ramSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS);
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//
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// Calculate how far the controller select value needs to be shifted. Each
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// section number is represented by a bit in the lower word of ramSection
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// and 2 bits in the corresponding MSEL register.
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//
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shiftVal = 0U;
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temp = MEMCFG_SECT_NUM_MASK & ramSection;
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while(temp != 1U)
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{
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temp = temp >> 1U;
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shiftVal += 2U;
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}
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//
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// Write the controller select setting into the appropriate field
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//
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EALLOW;
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) =
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(HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) &
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~((uint32_t)MEMCFG_LSXMSEL_MSEL_LS0_M << shiftVal)) |
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((uint32_t)controllerSel << shiftVal);
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EDIS;
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}
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//*****************************************************************************
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//
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// MemCfg_setGSRAMControllerSel
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//
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//*****************************************************************************
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void
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MemCfg_setGSRAMControllerSel(uint32_t ramSections,
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MemCfg_GSRAMControllerSel controllerSel)
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{
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uint32_t sectionNum;
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//
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// Check the arguments.
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//
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ASSERT((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS);
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//
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// We only need the section number bits for this function.
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//
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sectionNum = ramSections & MEMCFG_SECT_NUM_MASK;
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//
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// Write the controller select setting into the appropriate field.
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//
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EALLOW;
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if(controllerSel == MEMCFG_GSRAMCONTROLLER_CPU1)
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{
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) &= ~sectionNum;
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}
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else
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{
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) |= sectionNum;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// MemCfg_setTestMode
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//
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//*****************************************************************************
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void
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MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode)
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{
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uint32_t shiftVal = 0U;
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uint32_t maskVal;
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uint32_t regVal;
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uint32_t sectionNum;
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//
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// Check the arguments.
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//
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ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
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((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
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((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
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((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG));
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//
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// Calculate how far the protect mode value needs to be shifted. Each
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// section number is represented by a bit in the lower word of memSection
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// and 2 bits in the corresponding TEST register.
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//
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sectionNum = memSection & MEMCFG_SECT_NUM_MASK;
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while(sectionNum != 1U)
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{
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sectionNum = sectionNum >> 1U;
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shiftVal += 2U;
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}
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maskVal = (uint32_t)MEMCFG_XTEST_M << shiftVal;
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regVal = (uint32_t)testMode << shiftVal;
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//
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// Write the test mode into the appropriate field
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//
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EALLOW;
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switch(memSection & MEMCFG_SECT_TYPE_MASK)
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{
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case MEMCFG_SECT_TYPE_D:
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HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) &= ~maskVal;
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HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) |= regVal;
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break;
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case MEMCFG_SECT_TYPE_LS:
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) &= ~maskVal;
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) |= regVal;
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break;
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case MEMCFG_SECT_TYPE_GS:
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) &= ~maskVal;
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) |= regVal;
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break;
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case MEMCFG_SECT_TYPE_MSG:
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HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) &= ~maskVal;
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HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) |= regVal;
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break;
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default:
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//
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// Do nothing. Invalid memSection.
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//
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break;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// MemCfg_initSections
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//
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//*****************************************************************************
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void
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MemCfg_initSections(uint32_t ramSections)
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{
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//
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// Check the arguments.
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//
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ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
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((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
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((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
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((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) ||
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(ramSections == MEMCFG_SECT_ALL));
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//
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// Set the bit in the various initialization registers that starts
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// initialization.
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//
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EALLOW;
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switch(ramSections & MEMCFG_SECT_TYPE_MASK)
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{
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case MEMCFG_SECT_TYPE_D:
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HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK &
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ramSections;
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break;
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case MEMCFG_SECT_TYPE_LS:
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK &
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ramSections;
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break;
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case MEMCFG_SECT_TYPE_GS:
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK &
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ramSections;
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break;
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case MEMCFG_SECT_TYPE_MSG:
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HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK &
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ramSections;
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break;
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case MEMCFG_SECT_TYPE_MASK:
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//
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// Initialize all sections.
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//
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HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK &
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MEMCFG_SECT_DX_ALL;
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HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK &
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MEMCFG_SECT_LSX_ALL;
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HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK &
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MEMCFG_SECT_GSX_ALL;
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HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK &
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MEMCFG_SECT_MSGX_ALL;
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break;
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default:
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//
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// Do nothing. Invalid ramSections. Make sure you aren't OR-ing
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// values for two different types of RAM.
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//
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break;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// MemCfg_getInitStatus
|
|
//
|
|
//*****************************************************************************
|
|
bool
|
|
MemCfg_getInitStatus(uint32_t ramSections)
|
|
{
|
|
uint32_t status;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
|
|
((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
|
|
((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
|
|
((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) ||
|
|
(ramSections == MEMCFG_SECT_ALL));
|
|
|
|
//
|
|
// Read registers containing the initialization complete status.
|
|
//
|
|
switch(ramSections & MEMCFG_SECT_TYPE_MASK)
|
|
{
|
|
case MEMCFG_SECT_TYPE_D:
|
|
status = HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE);
|
|
break;
|
|
|
|
case MEMCFG_SECT_TYPE_LS:
|
|
status = HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE);
|
|
break;
|
|
|
|
case MEMCFG_SECT_TYPE_GS:
|
|
status = HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE);
|
|
break;
|
|
|
|
case MEMCFG_SECT_TYPE_MSG:
|
|
status = HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE);
|
|
break;
|
|
|
|
case MEMCFG_SECT_TYPE_MASK:
|
|
//
|
|
// Return the overall status.
|
|
//
|
|
if((HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE) ==
|
|
MEMCFG_SECT_DX_ALL) &&
|
|
(HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE) ==
|
|
MEMCFG_SECT_LSX_ALL) &&
|
|
(HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE) ==
|
|
MEMCFG_SECT_GSX_ALL) &&
|
|
(HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE) ==
|
|
MEMCFG_SECT_MSGX_ALL))
|
|
{
|
|
status = MEMCFG_SECT_NUM_MASK;
|
|
}
|
|
else
|
|
{
|
|
status = 0U;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
//
|
|
// Invalid ramSections. Make sure you aren't OR-ing values for two
|
|
// different types of RAM.
|
|
//
|
|
status = 0U;
|
|
break;
|
|
}
|
|
|
|
return((ramSections & status) == (ramSections & MEMCFG_SECT_NUM_MASK));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MemCfg_getViolationAddress
|
|
//
|
|
//*****************************************************************************
|
|
uint32_t
|
|
MemCfg_getViolationAddress(uint32_t intFlag)
|
|
{
|
|
uint32_t address;
|
|
uint32_t stsNumber;
|
|
|
|
//
|
|
// Calculate the the address of the desired violation address register.
|
|
//
|
|
if((intFlag & MEMCFG_MVIOL_MASK) != 0U)
|
|
{
|
|
stsNumber = intFlag >> MEMCFG_MVIOL_SHIFT;
|
|
address = ACCESSPROTECTION_BASE + MEMCFG_O_MCPUFAVADDR;
|
|
}
|
|
else
|
|
{
|
|
stsNumber = intFlag;
|
|
address = ACCESSPROTECTION_BASE + MEMCFG_O_NMCPURDAVADDR;
|
|
}
|
|
|
|
while(stsNumber > 1U)
|
|
{
|
|
stsNumber = stsNumber >> 1U;
|
|
address += (uint32_t)(MEMCFG_O_NMCPUWRAVADDR - MEMCFG_O_NMCPURDAVADDR);
|
|
}
|
|
|
|
//
|
|
// Read and return the access violation address at the calculated location.
|
|
//
|
|
return(HWREG(address));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MemCfg_getCorrErrorAddress
|
|
//
|
|
//*****************************************************************************
|
|
uint32_t
|
|
MemCfg_getCorrErrorAddress(uint32_t stsFlag)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
if(stsFlag != MEMCFG_CERR_CPUREAD)
|
|
{
|
|
//
|
|
// Currently, the only correctable error address that can be read
|
|
// from a register is one for a CPU read error (MEMCFG_CERR_CPUREAD).
|
|
// For the sake of keeping this function portable to possible future
|
|
// devices with other error types, it still takes a stsFlag parameter.
|
|
//
|
|
ASSERT((bool)false);
|
|
}
|
|
|
|
//
|
|
// Read and return the error address.
|
|
//
|
|
return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CCPUREADDR));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MemCfg_getUncorrErrorAddress
|
|
//
|
|
//*****************************************************************************
|
|
uint32_t
|
|
MemCfg_getUncorrErrorAddress(uint32_t stsFlag)
|
|
{
|
|
uint32_t address;
|
|
uint32_t temp;
|
|
|
|
//
|
|
// Calculate the the address of the desired error address register.
|
|
//
|
|
address = MEMORYERROR_BASE + MEMCFG_O_UCCPUREADDR;
|
|
|
|
temp = stsFlag;
|
|
|
|
while(temp > 1U)
|
|
{
|
|
temp = temp >> 1U;
|
|
address += (uint32_t)(MEMCFG_O_UCDMAREADDR - MEMCFG_O_UCCPUREADDR);
|
|
}
|
|
|
|
//
|
|
// Read and return the error address at the calculated location.
|
|
//
|
|
return(HWREG(address));
|
|
}
|
|
|
|
|