321 lines
16 KiB
C
321 lines
16 KiB
C
//###########################################################################
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//
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// FILE: F2837xD_PieVect.c
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//
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// TITLE: F2837xD Device PIE Vector Initialization Functions
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//
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//###########################################################################
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// $
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2023 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//
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// Included Files
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//
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#include "F2837xD_device.h"
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#include "F2837xD_Examples.h"
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//
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// Globals
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//
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const struct PIE_VECT_TABLE PieVectTableInit = {
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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PIE_RESERVED_ISR, // Reserved
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TIMER1_ISR, // CPU Timer 1 Interrupt
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TIMER2_ISR, // CPU Timer 2 Interrupt
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DATALOG_ISR, // Datalogging Interrupt
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RTOS_ISR, // RTOS Interrupt
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EMU_ISR, // Emulation Interrupt
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NMI_ISR, // Non-Maskable Interrupt
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ILLEGAL_ISR, // Illegal Operation Trap
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USER1_ISR, // User Defined Trap 1
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USER2_ISR, // User Defined Trap 2
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USER3_ISR, // User Defined Trap 3
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USER4_ISR, // User Defined Trap 4
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USER5_ISR, // User Defined Trap 5
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USER6_ISR, // User Defined Trap 6
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USER7_ISR, // User Defined Trap 7
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USER8_ISR, // User Defined Trap 8
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USER9_ISR, // User Defined Trap 9
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USER10_ISR, // User Defined Trap 10
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USER11_ISR, // User Defined Trap 11
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USER12_ISR, // User Defined Trap 12
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ADCA1_ISR, // 1.1 - ADCA Interrupt 1
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ADCB1_ISR, // 1.2 - ADCB Interrupt 1
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ADCC1_ISR, // 1.3 - ADCC Interrupt 1
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XINT1_ISR, // 1.4 - XINT1 Interrupt
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XINT2_ISR, // 1.5 - XINT2 Interrupt
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ADCD1_ISR, // 1.6 - ADCD Interrupt 1
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TIMER0_ISR, // 1.7 - Timer 0 Interrupt
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WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt
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EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt
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EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt
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EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt
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EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt
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EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt
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EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt
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EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt
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EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt
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EPWM1_ISR, // 3.1 - ePWM1 Interrupt
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EPWM2_ISR, // 3.2 - ePWM2 Interrupt
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EPWM3_ISR, // 3.3 - ePWM3 Interrupt
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EPWM4_ISR, // 3.4 - ePWM4 Interrupt
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EPWM5_ISR, // 3.5 - ePWM5 Interrupt
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EPWM6_ISR, // 3.6 - ePWM6 Interrupt
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EPWM7_ISR, // 3.7 - ePWM7 Interrupt
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EPWM8_ISR, // 3.8 - ePWM8 Interrupt
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ECAP1_ISR, // 4.1 - eCAP1 Interrupt
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ECAP2_ISR, // 4.2 - eCAP2 Interrupt
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ECAP3_ISR, // 4.3 - eCAP3 Interrupt
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ECAP4_ISR, // 4.4 - eCAP4 Interrupt
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ECAP5_ISR, // 4.5 - eCAP5 Interrupt
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ECAP6_ISR, // 4.6 - eCAP6 Interrupt
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PIE_RESERVED_ISR, // 4.7 - Reserved
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PIE_RESERVED_ISR, // 4.8 - Reserved
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EQEP1_ISR, // 5.1 - eQEP1 Interrupt
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EQEP2_ISR, // 5.2 - eQEP2 Interrupt
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EQEP3_ISR, // 5.3 - eQEP3 Interrupt
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PIE_RESERVED_ISR, // 5.4 - Reserved
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PIE_RESERVED_ISR, // 5.5 - Reserved
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PIE_RESERVED_ISR, // 5.6 - Reserved
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PIE_RESERVED_ISR, // 5.7 - Reserved
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PIE_RESERVED_ISR, // 5.8 - Reserved
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SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt
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SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt
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SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt
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SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt
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MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt
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MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt
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MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt
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MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt
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DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt
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DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt
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DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt
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DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt
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DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt
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DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt
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PIE_RESERVED_ISR, // 7.7 - Reserved
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PIE_RESERVED_ISR, // 7.8 - Reserved
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I2CA_ISR, // 8.1 - I2CA Interrupt 1
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I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2
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I2CB_ISR, // 8.3 - I2CB Interrupt 1
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I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2
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SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt
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SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt
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SCID_RX_ISR, // 8.7 - SCID Receive Interrupt
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SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt
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SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt
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SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt
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SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt
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SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt
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CANA0_ISR, // 9.5 - CANA Interrupt 0
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CANA1_ISR, // 9.6 - CANA Interrupt 1
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CANB0_ISR, // 9.7 - CANB Interrupt 0
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CANB1_ISR, // 9.8 - CANB Interrupt 1
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ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt
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ADCA2_ISR, // 10.2 - ADCA Interrupt 2
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ADCA3_ISR, // 10.3 - ADCA Interrupt 3
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ADCA4_ISR, // 10.4 - ADCA Interrupt 4
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ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt
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ADCB2_ISR, // 10.6 - ADCB Interrupt 2
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ADCB3_ISR, // 10.7 - ADCB Interrupt 3
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ADCB4_ISR, // 10.8 - ADCB Interrupt 4
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CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1
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CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2
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CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3
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CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4
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CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5
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CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6
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CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7
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CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8
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XINT3_ISR, // 12.1 - XINT3 Interrupt
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XINT4_ISR, // 12.2 - XINT4 Interrupt
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XINT5_ISR, // 12.3 - XINT5 Interrupt
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PIE_RESERVED_ISR, // 12.4 - Reserved
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PIE_RESERVED_ISR, // 12.5 - Reserved
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VCU_ISR, // 12.6 - VCU Interrupt
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FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt
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FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt
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PIE_RESERVED_ISR, // 1.9 - Reserved
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PIE_RESERVED_ISR, // 1.10 - Reserved
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PIE_RESERVED_ISR, // 1.11 - Reserved
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PIE_RESERVED_ISR, // 1.12 - Reserved
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IPC0_ISR, // 1.13 - IPC Interrupt 0
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IPC1_ISR, // 1.14 - IPC Interrupt 1
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IPC2_ISR, // 1.15 - IPC Interrupt 2
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IPC3_ISR, // 1.16 - IPC Interrupt 3
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EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt
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EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt
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EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt
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EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt
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PIE_RESERVED_ISR, // 2.13 - Reserved
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PIE_RESERVED_ISR, // 2.14 - Reserved
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PIE_RESERVED_ISR, // 2.15 - Reserved
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PIE_RESERVED_ISR, // 2.16 - Reserved
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EPWM9_ISR, // 3.9 - ePWM9 Interrupt
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EPWM10_ISR, // 3.10 - ePWM10 Interrupt
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EPWM11_ISR, // 3.11 - ePWM11 Interrupt
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EPWM12_ISR, // 3.12 - ePWM12 Interrupt
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PIE_RESERVED_ISR, // 3.13 - Reserved
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PIE_RESERVED_ISR, // 3.14 - Reserved
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PIE_RESERVED_ISR, // 3.15 - Reserved
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PIE_RESERVED_ISR, // 3.16 - Reserved
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PIE_RESERVED_ISR, // 4.9 - Reserved
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PIE_RESERVED_ISR, // 4.10 - Reserved
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PIE_RESERVED_ISR, // 4.11 - Reserved
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PIE_RESERVED_ISR, // 4.12 - Reserved
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PIE_RESERVED_ISR, // 4.13 - Reserved
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PIE_RESERVED_ISR, // 4.14 - Reserved
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PIE_RESERVED_ISR, // 4.15 - Reserved
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PIE_RESERVED_ISR, // 4.16 - Reserved
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SD1_ISR, // 5.9 - SD1 Interrupt
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SD2_ISR, // 5.10 - SD2 Interrupt
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PIE_RESERVED_ISR, // 5.11 - Reserved
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PIE_RESERVED_ISR, // 5.12 - Reserved
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PIE_RESERVED_ISR, // 5.13 - Reserved
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PIE_RESERVED_ISR, // 5.14 - Reserved
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PIE_RESERVED_ISR, // 5.15 - Reserved
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PIE_RESERVED_ISR, // 5.16 - Reserved
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SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt
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SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt
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PIE_RESERVED_ISR, // 6.11 - Reserved
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PIE_RESERVED_ISR, // 6.12 - Reserved
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PIE_RESERVED_ISR, // 6.13 - Reserved
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PIE_RESERVED_ISR, // 6.14 - Reserved
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PIE_RESERVED_ISR, // 6.15 - Reserved
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PIE_RESERVED_ISR, // 6.16 - Reserved
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PIE_RESERVED_ISR, // 7.9 - Reserved
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PIE_RESERVED_ISR, // 7.10 - Reserved
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PIE_RESERVED_ISR, // 7.11 - Reserved
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PIE_RESERVED_ISR, // 7.12 - Reserved
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PIE_RESERVED_ISR, // 7.13 - Reserved
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PIE_RESERVED_ISR, // 7.14 - Reserved
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PIE_RESERVED_ISR, // 7.15 - Reserved
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PIE_RESERVED_ISR, // 7.16 - Reserved
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PIE_RESERVED_ISR, // 8.9 - Reserved
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PIE_RESERVED_ISR, // 8.10 - Reserved
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PIE_RESERVED_ISR, // 8.11 - Reserved
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PIE_RESERVED_ISR, // 8.12 - Reserved
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PIE_RESERVED_ISR, // 8.13 - Reserved
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PIE_RESERVED_ISR, // 8.14 - Reserved
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#ifdef CPU1
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UPPA_ISR, // 8.15 - uPPA Interrupt
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PIE_RESERVED_ISR, // 8.16 - Reserved
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#elif defined(CPU2)
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PIE_RESERVED_ISR, // 8.15 - Reserved
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PIE_RESERVED_ISR, // 8.16 - Reserved
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#endif
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PIE_RESERVED_ISR, // 9.9 - Reserved
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PIE_RESERVED_ISR, // 9.10 - Reserved
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PIE_RESERVED_ISR, // 9.11 - Reserved
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PIE_RESERVED_ISR, // 9.12 - Reserved
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PIE_RESERVED_ISR, // 9.13 - Reserved
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PIE_RESERVED_ISR, // 9.14 - Reserved
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#ifdef CPU1
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USBA_ISR, // 9.15 - USBA Interrupt
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#elif defined(CPU2)
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PIE_RESERVED_ISR, // 9.15 - Reserved
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#endif
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PIE_RESERVED_ISR, // 9.16 - Reserved
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ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt
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ADCC2_ISR, // 10.10 - ADCC Interrupt 2
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ADCC3_ISR, // 10.11 - ADCC Interrupt 3
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ADCC4_ISR, // 10.12 - ADCC Interrupt 4
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ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt
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ADCD2_ISR, // 10.14 - ADCD Interrupt 2
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ADCD3_ISR, // 10.15 - ADCD Interrupt 3
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ADCD4_ISR, // 10.16 - ADCD Interrupt 4
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PIE_RESERVED_ISR, // 11.9 - Reserved
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PIE_RESERVED_ISR, // 11.10 - Reserved
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PIE_RESERVED_ISR, // 11.11 - Reserved
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PIE_RESERVED_ISR, // 11.12 - Reserved
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PIE_RESERVED_ISR, // 11.13 - Reserved
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PIE_RESERVED_ISR, // 11.14 - Reserved
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PIE_RESERVED_ISR, // 11.15 - Reserved
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PIE_RESERVED_ISR, // 11.16 - Reserved
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EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt
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RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt
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FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt
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RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt
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SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt
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AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt
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CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt
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CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt
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};
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//
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// InitPieVectTable - This function initializes the PIE vector table to a
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// known state and must be executed after boot time.
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//
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void InitPieVectTable(void)
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{
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Uint16 i;
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Uint32 *Source = (void *) &PieVectTableInit;
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Uint32 *Dest = (void *) &PieVectTable;
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//
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// Do not write over first 3 32-bit locations (these locations are
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// initialized by Boot ROM with boot variables)
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//
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Source = Source + 3;
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Dest = Dest + 3;
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EALLOW;
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for(i = 0; i < 221; i++)
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{
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*Dest++ = *Source++;
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}
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EDIS;
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//
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// Enable the PIE Vector Table
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//
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PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
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}
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//
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// End of file
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//
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