240 lines
12 KiB
C
240 lines
12 KiB
C
//###########################################################################
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//
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// FILE: hw_cla.h
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//
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// TITLE: Definitions for the CLA registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_CLA_H
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#define HW_CLA_H
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//*************************************************************************************************
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//
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// The following are defines for the CLA register offsets
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//
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//*************************************************************************************************
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#ifndef __TMS320C28XX_CLA__
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#define CLA_O_MVECT1 0x0U // Task Interrupt Vector
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#define CLA_O_MVECT2 0x1U // Task Interrupt Vector
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#define CLA_O_MVECT3 0x2U // Task Interrupt Vector
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#define CLA_O_MVECT4 0x3U // Task Interrupt Vector
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#define CLA_O_MVECT5 0x4U // Task Interrupt Vector
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#define CLA_O_MVECT6 0x5U // Task Interrupt Vector
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#define CLA_O_MVECT7 0x6U // Task Interrupt Vector
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#define CLA_O_MVECT8 0x7U // Task Interrupt Vector
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#define CLA_O_MCTL 0x10U // Control Register
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#define CLA_O_MIFR 0x20U // Interrupt Flag Register
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#define CLA_O_MIOVF 0x21U // Interrupt Overflow Flag Register
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#define CLA_O_MIFRC 0x22U // Interrupt Force Register
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#define CLA_O_MICLR 0x23U // Interrupt Flag Clear Register
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#define CLA_O_MICLROVF 0x24U // Interrupt Overflow Flag Clear Register
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#define CLA_O_MIER 0x25U // Interrupt Enable Register
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#define CLA_O_MIRUN 0x26U // Interrupt Run Status Register
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#define CLA_O_MPC 0x28U // CLA Program Counter
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#define CLA_O_MAR0 0x2AU // CLA Auxiliary Register 0
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#define CLA_O_MAR1 0x2BU // CLA Auxiliary Register 1
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#define CLA_O_MSTF 0x2EU // CLA Floating-Point Status Register
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#define CLA_O_MR0 0x30U // CLA Floating-Point Result Register 0
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#define CLA_O_MR1 0x34U // CLA Floating-Point Result Register 1
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#define CLA_O_MR2 0x38U // CLA Floating-Point Result Register 2
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#define CLA_O_MR3 0x3CU // CLA Floating-Point Result Register 3
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#endif
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#ifdef __TMS320C28XX_CLA__
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#define CLA_O_SOFTINTEN 0x0U // CLA Software Interrupt Enable Register
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#define CLA_O_SOFTINTFRC 0x2U // CLA Software Interrupt Force Register
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#endif
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#ifndef __TMS320C28XX_CLA__
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MCTL register
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//
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//*************************************************************************************************
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#define CLA_MCTL_HARDRESET 0x1U // Hard Reset
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#define CLA_MCTL_SOFTRESET 0x2U // Soft Reset
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#define CLA_MCTL_IACKE 0x4U // IACK enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MIFR register
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//
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//*************************************************************************************************
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#define CLA_MIFR_INT1 0x1U // Task 1 Interrupt Flag
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#define CLA_MIFR_INT2 0x2U // Task 2 Interrupt Flag
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#define CLA_MIFR_INT3 0x4U // Task 3 Interrupt Flag
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#define CLA_MIFR_INT4 0x8U // Task 4 Interrupt Flag
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#define CLA_MIFR_INT5 0x10U // Task 5 Interrupt Flag
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#define CLA_MIFR_INT6 0x20U // Task 6 Interrupt Flag
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#define CLA_MIFR_INT7 0x40U // Task 7 Interrupt Flag
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#define CLA_MIFR_INT8 0x80U // Task 8 Interrupt Flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MIOVF register
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//
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//*************************************************************************************************
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#define CLA_MIOVF_INT1 0x1U // Task 1 Interrupt Overflow Flag
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#define CLA_MIOVF_INT2 0x2U // Task 2 Interrupt Overflow Flag
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#define CLA_MIOVF_INT3 0x4U // Task 3 Interrupt Overflow Flag
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#define CLA_MIOVF_INT4 0x8U // Task 4 Interrupt Overflow Flag
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#define CLA_MIOVF_INT5 0x10U // Task 5 Interrupt Overflow Flag
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#define CLA_MIOVF_INT6 0x20U // Task 6 Interrupt Overflow Flag
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#define CLA_MIOVF_INT7 0x40U // Task 7 Interrupt Overflow Flag
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#define CLA_MIOVF_INT8 0x80U // Task 8 Interrupt Overflow Flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MIFRC register
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//
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//*************************************************************************************************
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#define CLA_MIFRC_INT1 0x1U // Task 1 Interrupt Force
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#define CLA_MIFRC_INT2 0x2U // Task 2 Interrupt Force
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#define CLA_MIFRC_INT3 0x4U // Task 3 Interrupt Force
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#define CLA_MIFRC_INT4 0x8U // Task 4 Interrupt Force
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#define CLA_MIFRC_INT5 0x10U // Task 5 Interrupt Force
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#define CLA_MIFRC_INT6 0x20U // Task 6 Interrupt Force
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#define CLA_MIFRC_INT7 0x40U // Task 7 Interrupt Force
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#define CLA_MIFRC_INT8 0x80U // Task 8 Interrupt Force
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MICLR register
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//
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//*************************************************************************************************
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#define CLA_MICLR_INT1 0x1U // Task 1 Interrupt Flag Clear
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#define CLA_MICLR_INT2 0x2U // Task 2 Interrupt Flag Clear
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#define CLA_MICLR_INT3 0x4U // Task 3 Interrupt Flag Clear
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#define CLA_MICLR_INT4 0x8U // Task 4 Interrupt Flag Clear
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#define CLA_MICLR_INT5 0x10U // Task 5 Interrupt Flag Clear
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#define CLA_MICLR_INT6 0x20U // Task 6 Interrupt Flag Clear
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#define CLA_MICLR_INT7 0x40U // Task 7 Interrupt Flag Clear
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#define CLA_MICLR_INT8 0x80U // Task 8 Interrupt Flag Clear
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MICLROVF register
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//
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//*************************************************************************************************
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#define CLA_MICLROVF_INT1 0x1U // Task 1 Interrupt Overflow Flag Clear
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#define CLA_MICLROVF_INT2 0x2U // Task 2 Interrupt Overflow Flag Clear
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#define CLA_MICLROVF_INT3 0x4U // Task 3 Interrupt Overflow Flag Clear
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#define CLA_MICLROVF_INT4 0x8U // Task 4 Interrupt Overflow Flag Clear
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#define CLA_MICLROVF_INT5 0x10U // Task 5 Interrupt Overflow Flag Clear
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#define CLA_MICLROVF_INT6 0x20U // Task 6 Interrupt Overflow Flag Clear
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#define CLA_MICLROVF_INT7 0x40U // Task 7 Interrupt Overflow Flag Clear
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#define CLA_MICLROVF_INT8 0x80U // Task 8 Interrupt Overflow Flag Clear
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MIER register
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//
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//*************************************************************************************************
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#define CLA_MIER_INT1 0x1U // Task 1 Interrupt Enable
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#define CLA_MIER_INT2 0x2U // Task 2 Interrupt Enable
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#define CLA_MIER_INT3 0x4U // Task 3 Interrupt Enable
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#define CLA_MIER_INT4 0x8U // Task 4 Interrupt Enable
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#define CLA_MIER_INT5 0x10U // Task 5 Interrupt Enable
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#define CLA_MIER_INT6 0x20U // Task 6 Interrupt Enable
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#define CLA_MIER_INT7 0x40U // Task 7 Interrupt Enable
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#define CLA_MIER_INT8 0x80U // Task 8 Interrupt Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MIRUN register
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//
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//*************************************************************************************************
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#define CLA_MIRUN_INT1 0x1U // Task 1 Run Status
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#define CLA_MIRUN_INT2 0x2U // Task 2 Run Status
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#define CLA_MIRUN_INT3 0x4U // Task 3 Run Status
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#define CLA_MIRUN_INT4 0x8U // Task 4 Run Status
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#define CLA_MIRUN_INT5 0x10U // Task 5 Run Status
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#define CLA_MIRUN_INT6 0x20U // Task 6 Run Status
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#define CLA_MIRUN_INT7 0x40U // Task 7 Run Status
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#define CLA_MIRUN_INT8 0x80U // Task 8 Run Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the _MSTF register
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//
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//*************************************************************************************************
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#define CLA_MSTF_LVF 0x1U // Latched Overflow Flag
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#define CLA_MSTF_LUF 0x2U // Latched Underflow Flag
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#define CLA_MSTF_NF 0x4U // Negative Float Flag
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#define CLA_MSTF_ZF 0x8U // Zero Float Flag
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#define CLA_MSTF_TF 0x40U // Test Flag
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#define CLA_MSTF_RNDF32 0x200U // Round 32-bit Floating-Point Mode
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#define CLA_MSTF_MEALLOW 0x800U // MEALLOW Status
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#define CLA_MSTF_RPC_S 12U
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#define CLA_MSTF_RPC_M 0xFFFF000U // Return PC
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#endif
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#ifdef __TMS320C28XX_CLA__
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SOFTINTEN register
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//
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//*************************************************************************************************
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#define CLA_SOFTINTEN_TASK1 0x1U // Configure Software Interrupt or End of Task interrupt.
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#define CLA_SOFTINTEN_TASK2 0x2U // Configure Software Interrupt or End of Task interrupt.
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#define CLA_SOFTINTEN_TASK3 0x4U // Configure Software Interrupt or End of Task interrupt.
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#define CLA_SOFTINTEN_TASK4 0x8U // Configure Software Interrupt or End of Task interrupt.
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#define CLA_SOFTINTEN_TASK5 0x10U // Configure Software Interrupt or End of Task interrupt.
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#define CLA_SOFTINTEN_TASK6 0x20U // Configure Software Interrupt or End of Task interrupt.
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#define CLA_SOFTINTEN_TASK7 0x40U // Configure Software Interrupt or End of Task interrupt.
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#define CLA_SOFTINTEN_TASK8 0x80U // Configure Software Interrupt or End of Task interrupt.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SOFTINTFRC register
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//
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//*************************************************************************************************
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#define CLA_SOFTINTFRC_TASK1 0x1U // Force CLA software interrupt for the corresponding task.
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#define CLA_SOFTINTFRC_TASK2 0x2U // Force CLA software interrupt for the corresponding task.
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#define CLA_SOFTINTFRC_TASK3 0x4U // Force CLA software interrupt for the corresponding task.
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#define CLA_SOFTINTFRC_TASK4 0x8U // Force CLA software interrupt for the corresponding task.
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#define CLA_SOFTINTFRC_TASK5 0x10U // Force CLA software interrupt for the corresponding task.
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#define CLA_SOFTINTFRC_TASK6 0x20U // Force CLA software interrupt for the corresponding task.
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#define CLA_SOFTINTFRC_TASK7 0x40U // Force CLA software interrupt for the corresponding task.
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#define CLA_SOFTINTFRC_TASK8 0x80U // Force CLA software interrupt for the corresponding task.
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#endif
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#endif
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