164 lines
8.4 KiB
C
164 lines
8.4 KiB
C
//###########################################################################
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//
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// FILE: hw_dma.h
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//
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// TITLE: Definitions for the DMA registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_DMA_H
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#define HW_DMA_H
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//*************************************************************************************************
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//
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// The following are defines for the DMA register offsets
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//
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//*************************************************************************************************
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#define DMA_O_CTRL 0x0U // DMA Control Register
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#define DMA_O_DEBUGCTRL 0x1U // Debug Control Register
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#define DMA_O_PRIORITYCTRL1 0x4U // Priority Control 1 Register
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#define DMA_O_PRIORITYSTAT 0x6U // Priority Status Register
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#define DMA_O_MODE 0x0U // Mode Register
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#define DMA_O_CONTROL 0x1U // Control Register
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#define DMA_O_BURST_SIZE 0x2U // Burst Size Register
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#define DMA_O_BURST_COUNT 0x3U // Burst Count Register
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#define DMA_O_SRC_BURST_STEP 0x4U // Source Burst Step Register
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#define DMA_O_DST_BURST_STEP 0x5U // Destination Burst Step Register
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#define DMA_O_TRANSFER_SIZE 0x6U // Transfer Size Register
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#define DMA_O_TRANSFER_COUNT 0x7U // Transfer Count Register
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#define DMA_O_SRC_TRANSFER_STEP 0x8U // Source Transfer Step Register
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#define DMA_O_DST_TRANSFER_STEP 0x9U // Destination Transfer Step Register
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#define DMA_O_SRC_WRAP_SIZE 0xAU // Source Wrap Size Register
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#define DMA_O_SRC_WRAP_COUNT 0xBU // Source Wrap Count Register
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#define DMA_O_SRC_WRAP_STEP 0xCU // Source Wrap Step Register
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#define DMA_O_DST_WRAP_SIZE 0xDU // Destination Wrap Size Register
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#define DMA_O_DST_WRAP_COUNT 0xEU // Destination Wrap Count Register
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#define DMA_O_DST_WRAP_STEP 0xFU // Destination Wrap Step Register
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#define DMA_O_SRC_BEG_ADDR_SHADOW 0x10U // Source Begin Address Shadow Register
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#define DMA_O_SRC_ADDR_SHADOW 0x12U // Source Address Shadow Register
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#define DMA_O_SRC_BEG_ADDR_ACTIVE 0x14U // Source Begin Address Active Register
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#define DMA_O_SRC_ADDR_ACTIVE 0x16U // Source Address Active Register
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#define DMA_O_DST_BEG_ADDR_SHADOW 0x18U // Destination Begin Address Shadow Register
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#define DMA_O_DST_ADDR_SHADOW 0x1AU // Destination Address Shadow Register
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#define DMA_O_DST_BEG_ADDR_ACTIVE 0x1CU // Destination Begin Address Active Register
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#define DMA_O_DST_ADDR_ACTIVE 0x1EU // Destination Address Active Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMACTRL register
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//
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//*************************************************************************************************
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#define DMA_CTRL_HARDRESET 0x1U // Hard Reset Bit
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#define DMA_CTRL_PRIORITYRESET 0x2U // Priority Reset Bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DEBUGCTRL register
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//
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//*************************************************************************************************
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#define DMA_DEBUGCTRL_FREE 0x8000U // Debug Mode Bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the PRIORITYCTRL1 register
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//
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//*************************************************************************************************
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#define DMA_PRIORITYCTRL1_CH1PRIORITY 0x1U // Ch1 Priority Bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the PRIORITYSTAT register
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//
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//*************************************************************************************************
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#define DMA_PRIORITYSTAT_ACTIVESTS_S 0U
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#define DMA_PRIORITYSTAT_ACTIVESTS_M 0x7U // Active Channel Status Bits
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#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_S 4U
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#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_M 0x70U // Active Channel Status Shadow Bits
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MODE register
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//
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//*************************************************************************************************
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#define DMA_MODE_PERINTSEL_S 0U
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#define DMA_MODE_PERINTSEL_M 0x1FU // Peripheral Interrupt and Sync Select
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#define DMA_MODE_OVRINTE 0x80U // Overflow Interrupt Enable
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#define DMA_MODE_PERINTE 0x100U // Peripheral Interrupt Enable
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#define DMA_MODE_CHINTMODE 0x200U // Channel Interrupt Mode
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#define DMA_MODE_ONESHOT 0x400U // One Shot Mode Bit
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#define DMA_MODE_CONTINUOUS 0x800U // Continuous Mode Bit
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#define DMA_MODE_DATASIZE 0x4000U // Data Size Mode Bit
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#define DMA_MODE_CHINTE 0x8000U // Channel Interrupt Enable Bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CONTROL register
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//
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//*************************************************************************************************
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#define DMA_CONTROL_RUN 0x1U // Run Bit
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#define DMA_CONTROL_HALT 0x2U // Halt Bit
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#define DMA_CONTROL_SOFTRESET 0x4U // Soft Reset Bit
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#define DMA_CONTROL_PERINTFRC 0x8U // Interrupt Force Bit
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#define DMA_CONTROL_PERINTCLR 0x10U // Interrupt Clear Bit
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#define DMA_CONTROL_ERRCLR 0x80U // Error Clear Bit
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#define DMA_CONTROL_PERINTFLG 0x100U // Interrupt Flag Bit
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#define DMA_CONTROL_TRANSFERSTS 0x800U // Transfer Status Bit
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#define DMA_CONTROL_BURSTSTS 0x1000U // Burst Status Bit
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#define DMA_CONTROL_RUNSTS 0x2000U // Run Status Bit
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#define DMA_CONTROL_OVRFLG 0x4000U // Overflow Flag Bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the BURST_SIZE register
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//
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//*************************************************************************************************
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#define DMA_BURST_SIZE_BURSTSIZE_S 0U
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#define DMA_BURST_SIZE_BURSTSIZE_M 0x1FU // Burst Transfer Size
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the BURST_COUNT register
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//
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//*************************************************************************************************
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#define DMA_BURST_COUNT_BURSTCOUNT_S 0U
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#define DMA_BURST_COUNT_BURSTCOUNT_M 0x1FU // Burst Transfer Size
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#endif
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