666 lines
17 KiB
C
666 lines
17 KiB
C
//###########################################################################
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//
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// FILE: spi.c
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//
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// TITLE: C28x SPI driver.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#include "spi.h"
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//*****************************************************************************
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//
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// SPI_setConfig
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//
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//*****************************************************************************
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void
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SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol,
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SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth)
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{
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uint16_t regValue;
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uint32_t baud;
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//
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// Check the arguments.
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//
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ASSERT(SPI_isBaseValid(base));
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ASSERT(bitRate <= (lspclkHz / 4U));
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ASSERT((lspclkHz / bitRate) <= 128U);
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ASSERT((dataWidth >= 1U) && (dataWidth <= 16U));
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ASSERT((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPISWRESET) == 0U);
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//
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// Set polarity and data width.
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//
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regValue = (((uint16_t)protocol << 6U) & SPI_CCR_CLKPOLARITY) |
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(dataWidth - 1U);
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HWREGH(base + SPI_O_CCR) = (HWREGH(base + SPI_O_CCR) &
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~(SPI_CCR_CLKPOLARITY | SPI_CCR_SPICHAR_M)) |
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regValue;
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//
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// Set the mode and phase.
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//
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regValue = (uint16_t)mode | (((uint16_t)protocol << 2U) &
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SPI_CTL_CLK_PHASE);
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HWREGH(base + SPI_O_CTL) = (HWREGH(base + SPI_O_CTL) &
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~(SPI_CTL_TALK | SPI_CTL_CONTROLLER_PERIPHERAL |
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SPI_CTL_CLK_PHASE)) | regValue;
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//
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// Set the clock.
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//
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baud = (lspclkHz / bitRate) - 1U;
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HWREGH(base + SPI_O_BRR) = (uint16_t)baud;
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}
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//*****************************************************************************
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//
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// SPI_setBaudRate
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//
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//*****************************************************************************
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void
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SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate)
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{
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uint32_t baud;
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//
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// Check the arguments.
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//
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ASSERT(SPI_isBaseValid(base));
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ASSERT(bitRate <= (lspclkHz / 4U));
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ASSERT((lspclkHz / bitRate) <= 128U);
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//
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// Set the clock.
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//
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baud = (lspclkHz / bitRate) - 1U;
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HWREGH(base + SPI_O_BRR) = (uint16_t)baud;
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}
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//*****************************************************************************
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//
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// SPI_enableInterrupt
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//
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//*****************************************************************************
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void
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SPI_enableInterrupt(uint32_t base, uint32_t intFlags)
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{
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//
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// Check the arguments.
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//
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ASSERT(SPI_isBaseValid(base));
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//
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// Enable the specified non-FIFO interrupts.
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//
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if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U)
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{
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HWREGH(base + SPI_O_CTL) |= SPI_CTL_SPIINTENA;
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}
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if((intFlags & SPI_INT_RX_OVERRUN) != 0U)
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{
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HWREGH(base + SPI_O_CTL) |= SPI_CTL_OVERRUNINTENA;
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}
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//
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// Enable the specified FIFO-mode interrupts.
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//
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if((intFlags & SPI_INT_TXFF) != 0U)
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{
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HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFFIENA;
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}
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if((intFlags & (SPI_INT_RXFF | SPI_INT_RXFF_OVERFLOW)) != 0U)
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{
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HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFIENA;
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}
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}
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//*****************************************************************************
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//
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// SPI_disableInterrupt
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//
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//*****************************************************************************
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void
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SPI_disableInterrupt(uint32_t base, uint32_t intFlags)
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{
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//
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// Check the arguments.
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//
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ASSERT(SPI_isBaseValid(base));
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//
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// Disable the specified non-FIFO interrupts.
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//
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if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U)
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{
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HWREGH(base + SPI_O_CTL) &= ~(SPI_CTL_SPIINTENA);
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}
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if((intFlags & SPI_INT_RX_OVERRUN) != 0U)
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{
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HWREGH(base + SPI_O_CTL) &= ~(SPI_CTL_OVERRUNINTENA);
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}
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//
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// Disable the specified FIFO-mode interrupts.
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//
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if((intFlags & SPI_INT_TXFF) != 0U)
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{
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HWREGH(base + SPI_O_FFTX) &= ~(SPI_FFTX_TXFFIENA);
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}
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if((intFlags & (SPI_INT_RXFF | SPI_INT_RXFF_OVERFLOW)) != 0U)
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{
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HWREGH(base + SPI_O_FFRX) &= ~(SPI_FFRX_RXFFIENA);
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}
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}
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//*****************************************************************************
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//
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// SPI_getInterruptStatus
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//
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//*****************************************************************************
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uint32_t
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SPI_getInterruptStatus(uint32_t base)
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{
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uint32_t temp = 0;
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//
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// Check the arguments.
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//
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ASSERT(SPI_isBaseValid(base));
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if((HWREGH(base + SPI_O_STS) & SPI_STS_INT_FLAG) != 0U)
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{
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temp |= SPI_INT_RX_DATA_TX_EMPTY;
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}
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if((HWREGH(base + SPI_O_STS) & SPI_STS_OVERRUN_FLAG) != 0U)
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{
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temp |= SPI_INT_RX_OVERRUN;
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}
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if((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFINT) != 0U)
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{
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temp |= SPI_INT_TXFF;
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}
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if((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFINT) != 0U)
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{
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temp |= SPI_INT_RXFF;
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}
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if((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFOVF) != 0U)
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{
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temp |= SPI_INT_RXFF_OVERFLOW;
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}
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return(temp);
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}
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//*****************************************************************************
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//
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// SPI_clearInterruptStatus
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//
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//*****************************************************************************
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void
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SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags)
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{
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//
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// Check the arguments.
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//
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ASSERT(SPI_isBaseValid(base));
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//
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// Clear the specified non-FIFO interrupt sources.
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//
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if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U)
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{
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HWREGH(base + SPI_O_CCR) &= ~(SPI_CCR_SPISWRESET);
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HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPISWRESET;
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}
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if((intFlags & SPI_INT_RX_OVERRUN) != 0U)
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{
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HWREGH(base + SPI_O_STS) |= SPI_STS_OVERRUN_FLAG;
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}
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//
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// Clear the specified FIFO-mode interrupt sources.
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//
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if((intFlags & SPI_INT_TXFF) != 0U)
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{
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HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFFINTCLR;
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}
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if((intFlags & SPI_INT_RXFF) != 0U)
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{
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HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFINTCLR;
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}
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if((intFlags & SPI_INT_RXFF_OVERFLOW) != 0U)
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{
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HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFOVFCLR;
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}
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}
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//*****************************************************************************
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//
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// SPI_pollingNonFIFOTransaction
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//
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//*****************************************************************************
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uint16_t
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SPI_pollingNonFIFOTransaction(uint32_t base, uint16_t charLength, uint16_t data)
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{
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uint16_t rxData;
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ASSERT((charLength >= 1U) && (charLength <= 16U));
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ASSERT(data < ((uint32_t)1U << charLength));
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//
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// Set the character length
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//
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SPI_setcharLength(base, charLength);
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//
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// Write to SPI Transmit buffer
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//
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SPI_writeDataBlockingNonFIFO(base, data << (16U - charLength));
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//
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// Read SPI Receive buffer
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//
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rxData = SPI_readDataBlockingNonFIFO(base);
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return(rxData);
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}
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//*****************************************************************************
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//
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// SPI_pollingFIFOTransaction
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//
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//*****************************************************************************
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void
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SPI_pollingFIFOTransaction(uint32_t base, uint16_t charLength,
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uint16_t *pTxBuffer, uint16_t *pRxBuffer,
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uint16_t numOfWords, uint16_t txDelay)
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{
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ASSERT((charLength >= 1U) && (charLength <= 16U));
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SPI_setcharLength(base, charLength);
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//
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// Reset the TX / RX FIFO buffers to default state
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//
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SPI_disableFIFO(base); // Disable FIFO register
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SPI_enableFIFO(base); // Enable FIFO register
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//
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// Configure the FIFO Transmit Delay
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//
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SPI_setTxFifoTransmitDelay(base, txDelay);
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//
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// Determine the number of 16-level words from number of words to be
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// transmitted / received
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//
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uint16_t numOfSixteenWords = numOfWords / (uint16_t)SPI_FIFO_TXFULL;
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//
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// Determine the number of remaining words from number of words to be
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// transmitted / received
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//
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uint16_t remainingWords = numOfWords % (uint16_t)SPI_FIFO_TXFULL;
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uint16_t count = 0;
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uint16_t i = 0;
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uint16_t txBuffer_pos = 0;
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uint16_t rxBuffer_pos = 0;
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//
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// Number of transactions is based on numOfSixteenWords
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// Each transaction will transmit and receive 16 words.
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//
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while(count < numOfSixteenWords)
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{
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//
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// Fill-up the SPI Transmit FIFO buffers
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//
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for(i = 1; i <= (uint16_t)SPI_FIFO_TXFULL; i++)
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{
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SPI_writeDataBlockingFIFO(base, pTxBuffer[txBuffer_pos] <<
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(16U - charLength));
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txBuffer_pos++;
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}
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//
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// Wait till SPI Receive FIFO buffer is full
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//
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while(SPI_getRxFIFOStatus(base) < SPI_FIFO_RXFULL)
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{
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}
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//
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// Read the SPI Receive FIFO buffers
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//
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for(i = 1U; i <= (uint16_t)SPI_FIFO_RXFULL; i++)
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{
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if(pRxBuffer == NULL)
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{
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SPI_readDataBlockingFIFO(base);
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}
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else
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{
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pRxBuffer[rxBuffer_pos] = SPI_readDataBlockingFIFO(base);
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rxBuffer_pos++;
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}
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}
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count++;
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}
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//
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// Number of transactions is based on remainingWords
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//
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for(i = 0U; i < remainingWords; i++)
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{
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SPI_writeDataBlockingFIFO(base, pTxBuffer[txBuffer_pos] <<
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(16U - charLength));
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txBuffer_pos++;
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}
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//
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// Wait till SPI Receive FIFO buffer remaining words
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//
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while((uint16_t)SPI_getRxFIFOStatus(base) < remainingWords)
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{
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}
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//
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// Read the SPI Receive FIFO buffers
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//
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for(i = 0; i < remainingWords; i++)
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{
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if(pRxBuffer == NULL)
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{
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SPI_readDataBlockingFIFO(base);
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}
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else
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{
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pRxBuffer[rxBuffer_pos] = SPI_readDataBlockingFIFO(base);
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rxBuffer_pos++;
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}
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}
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//
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// Disable SPI FIFO
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//
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SPI_disableFIFO(base);
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}
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//*****************************************************************************
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//
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// SPI_transmit24Bits
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//
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//*****************************************************************************
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void
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SPI_transmit24Bits(uint32_t base, uint32_t data, uint16_t txDelay)
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{
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uint16_t i;
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uint16_t rxBuffer[3];
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uint16_t txBuffer[3];
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ASSERT(data < ((uint32_t)1U << 24U));
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//
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// Empty Receive buffer
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//
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for(i = 0U; i < 3U; i++)
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{
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rxBuffer[i] = 0U;
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}
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//
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// Fill Transmit buffer with appropriate data
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//
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txBuffer[0] = (uint16_t)(data >> 16U); // data[23:16]
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txBuffer[1] = (uint16_t)(data) >> 8U; // data[15:8]
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txBuffer[2] = (uint16_t)(data) & 0x00FFU; // data[7:0]
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//
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// Three 8-bits make a 24-bit
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// Character length = 8
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// number of bytes = 3
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//
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SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 3U, txDelay);
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}
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//*****************************************************************************
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//
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// SPI_receive16Bits
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//
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//*****************************************************************************
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uint16_t
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SPI_receive16Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData,
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uint16_t txDelay)
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{
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uint16_t i;
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uint16_t txBuffer[2];
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uint16_t rxBuffer[2];
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uint16_t rxData = 0U;
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ASSERT(dummyData <= 0xFFU);
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//
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// Empty Transmit buffer
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//
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for(i = 0U; i < 2U; i++)
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{
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txBuffer[i] = dummyData;
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rxBuffer[i] = 0U;
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}
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//
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// Send dummy words to receive data from peripheral
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//
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SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 2U, txDelay);
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if(endianness == SPI_DATA_LITTLE_ENDIAN)
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{
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//
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// LITTLE_ENDIAN
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//
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rxData = (rxBuffer[1] << 8) | rxBuffer[0];
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}
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else
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{
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//
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// BIG_ENDIAN
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//
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rxData = (rxBuffer[0] << 8) | rxBuffer[1];
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}
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return(rxData);
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}
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//*****************************************************************************
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//
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// SPI_receive24Bits
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//
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//*****************************************************************************
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uint32_t
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SPI_receive24Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData,
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uint16_t txDelay)
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{
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uint16_t i;
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uint16_t txBuffer[3];
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uint16_t rxBuffer[3];
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uint32_t rxData = 0;
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ASSERT(dummyData <= 0xFFU);
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//
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// Empty Transmit buffer
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//
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for(i = 0U; i < 3U; i++)
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{
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txBuffer[i] = dummyData;
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rxBuffer[i] = 0U;
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}
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//
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// Send dummy words to receive data from peripheral
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// Two 8-bits make a 16-bit
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// Character length = 8
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// number of bytes = 2
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//
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SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 3U, txDelay);
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if(endianness == SPI_DATA_LITTLE_ENDIAN)
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{
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//
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// LITTLE_ENDIAN
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//
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rxData = ((uint32_t)rxBuffer[2] << 16) |
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((uint32_t)rxBuffer[1] << 8) |
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(uint32_t)rxBuffer[0];
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}
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else
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{
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//
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// BIG_ENDIAN
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//
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rxData = ((uint32_t)rxBuffer[0] << 16) |
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((uint32_t)rxBuffer[1] << 8) |
|
|
(uint32_t)rxBuffer[2];
|
|
}
|
|
|
|
return(rxData);
|
|
}
|
|
//*****************************************************************************
|
|
//
|
|
// SPI_transmit32Bits
|
|
//
|
|
//*****************************************************************************
|
|
|
|
void
|
|
SPI_transmit32Bits(uint32_t base, uint32_t data, uint16_t txDelay)
|
|
{
|
|
uint16_t i;
|
|
uint16_t txBuffer[2];
|
|
uint16_t rxBuffer[2];
|
|
|
|
//
|
|
// Empty Receive buffer
|
|
//
|
|
for(i = 0U; i < 2U; i++)
|
|
{
|
|
rxBuffer[i] = 0U;
|
|
}
|
|
|
|
//
|
|
// Fill Transmit buffer with appropriate data
|
|
//
|
|
txBuffer[0] = (uint16_t)(data >> 16U); // data[31:16]
|
|
txBuffer[1] = (uint16_t)(data); // data[15:0]
|
|
|
|
//
|
|
// Two 16-bits make a 32-bit
|
|
// Character length = 16
|
|
// number of bytes = 2
|
|
//
|
|
SPI_pollingFIFOTransaction(base, 16U, txBuffer, rxBuffer, 2U, txDelay);
|
|
}
|
|
//*****************************************************************************
|
|
//
|
|
// SPI_receive32Bits
|
|
//
|
|
//*****************************************************************************
|
|
|
|
uint32_t
|
|
SPI_receive32Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData,
|
|
uint16_t txDelay)
|
|
{
|
|
uint16_t i;
|
|
uint16_t txBuffer[4];
|
|
uint16_t rxBuffer[4];
|
|
uint32_t rxData = 0U;
|
|
|
|
ASSERT(dummyData <= 0xFFU);
|
|
|
|
//
|
|
// Empty Transmit buffer
|
|
//
|
|
for(i = 0U; i < 4U; i++)
|
|
{
|
|
txBuffer[i] = dummyData;
|
|
rxBuffer[i] = 0U;
|
|
}
|
|
|
|
//
|
|
// Send dummy words to receive data from peripheral
|
|
// Four 8-bits make a 32-bit
|
|
// Character length = 8
|
|
// number of bytes = 4
|
|
//
|
|
SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 4U, txDelay);
|
|
|
|
if(endianness == SPI_DATA_LITTLE_ENDIAN)
|
|
{
|
|
//
|
|
// LITTLE_ENDIAN
|
|
//
|
|
rxData = ((uint32_t)rxBuffer[3] << 24U) |
|
|
((uint32_t)rxBuffer[2] << 16U) |
|
|
((uint32_t)rxBuffer[1] << 8U) |
|
|
(uint32_t)rxBuffer[0];
|
|
}
|
|
else
|
|
{
|
|
//
|
|
// BIG_ENDIAN
|
|
//
|
|
rxData = ((uint32_t)rxBuffer[0] << 24U) |
|
|
((uint32_t)rxBuffer[1] << 16U) |
|
|
((uint32_t)rxBuffer[2] << 8U) |
|
|
(uint32_t)rxBuffer[3];
|
|
}
|
|
|
|
return(rxData);
|
|
}
|