395 lines
15 KiB
C
395 lines
15 KiB
C
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//#############################################################################
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//
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// FILE: device.h
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//
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// TITLE: Device setup for examples.
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//
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//#############################################################################
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//
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2013-2023 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//#############################################################################
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//
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// Included Files
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//
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#include "driverlib.h"
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#if (!defined(CPU1) && !defined(CPU2))
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#error "You must define CPU1 or CPU2 in your project properties. Otherwise, \
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the offsets in your header files will be inaccurate."
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#endif
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#if (defined(CPU1) && defined(CPU2))
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#error "You have defined both CPU1 and CPU2 in your project properties. Only \
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a single CPU should be defined."
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#endif
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//*****************************************************************************
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//
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// Defines for pin numbers and other GPIO configuration
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//
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//*****************************************************************************
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//
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// LEDs
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//
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#ifdef _LAUNCHXL_F28379D
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#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD10
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#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD9
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#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD10
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#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD9
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#else
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#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2
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#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3
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#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2
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#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3
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#endif
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//
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// SCI for USB-to-UART adapter on FTDI chip
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//
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#ifdef _LAUNCHXL_F28379D
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#define DEVICE_GPIO_PIN_SCIRXDA 43U // GPIO number for SCI RX
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#define DEVICE_GPIO_PIN_SCITXDA 42U // GPIO number for SCI TX
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#define DEVICE_GPIO_CFG_SCIRXDA GPIO_43_SCIRXDA // "pinConfig" for SCI RX
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#define DEVICE_GPIO_CFG_SCITXDA GPIO_42_SCITXDA // "pinConfig" for SCI TX
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#else
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#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX
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#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX
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#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX
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#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX
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#endif
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//
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// GPIO assignment for CAN-A and CAN-B
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//
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#ifdef _LAUNCHXL_F28379D
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#define DEVICE_GPIO_CFG_CANRXA GPIO_36_CANRXA // "pinConfig" for CANA RX
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#define DEVICE_GPIO_CFG_CANTXA GPIO_37_CANTXA // "pinConfig" for CANA TX
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#define DEVICE_GPIO_CFG_CANRXB GPIO_17_CANRXB // "pinConfig" for CANB RX
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#define DEVICE_GPIO_CFG_CANTXB GPIO_12_CANTXB // "pinConfig" for CANB TX
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#else
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#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX
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#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX
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#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX
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#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX
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//I2CA GPIO pins
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#define DEVICE_GPIO_PIN_SDAA 104
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#define DEVICE_GPIO_PIN_SCLA 105
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#define DEVICE_GPIO_CFG_SDAA GPIO_104_SDAA
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#define DEVICE_GPIO_CFG_SCLA GPIO_105_SCLA
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//I2CB GPIO pins
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#define DEVICE_GPIO_PIN_SDAB 40
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#define DEVICE_GPIO_PIN_SCLB 41
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#define DEVICE_GPIO_CFG_SDAB GPIO_40_SDAB
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#define DEVICE_GPIO_CFG_SCLB GPIO_41_SCLB
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#endif
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//*****************************************************************************
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//
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// Defines related to clock configuration
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//
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//*****************************************************************************
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//
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// Launchpad Configuration
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//
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#ifdef _LAUNCHXL_F28379D
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//
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// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock().
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//
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#define DEVICE_OSCSRC_FREQ 10000000U
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//
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// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
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// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
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//
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#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \
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SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
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SYSCTL_PLL_ENABLE)
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//
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// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
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// code below if a different clock configuration is used!
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//
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#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2)
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//
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// ControlCARD Configuration
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//
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#else
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//
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// 20MHz XTAL on controlCARD. For use with SysCtl_getClock().
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//
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#define DEVICE_OSCSRC_FREQ 20000000U
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//
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// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
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// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
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//
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#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) | \
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SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
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SYSCTL_PLL_ENABLE)
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//
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// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
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// code below if a different clock configuration is used!
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//
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#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2)
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#endif
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//
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// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
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// low speed peripheral clock divider of 4. Update the code below if a
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// different LSPCLK divider is used!
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//
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#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4)
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//*****************************************************************************
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//
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// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro
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// will convert the desired delay in microseconds to the count value expected
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// by the function. \b x is the number of microseconds to delay.
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//
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//*****************************************************************************
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#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \
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(long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L)
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//
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// The macros that can be used as parameter to the function Device_bootCPU2
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//
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#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000U
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#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001U
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#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004U
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#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005U
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#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007U
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#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000AU
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#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000BU
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//
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// Other macros that are needed for the Device_bootCPU2 function
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//
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#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013U
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#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000CU
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#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000U
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#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001U
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#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002U
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#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003U
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#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004U
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#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005U
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//
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// Macros used as return value by the Device_bootCPU2 function
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//
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#define STATUS_FAIL 0x0001
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#define STATUS_PASS 0x0000
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//*****************************************************************************
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//
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// Defines, Globals, and Header Includes related to Flash Support
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//
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//*****************************************************************************
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#ifdef _FLASH
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#include <stddef.h>
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extern uint16_t RamfuncsLoadStart;
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extern uint16_t RamfuncsLoadEnd;
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extern uint16_t RamfuncsLoadSize;
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extern uint16_t RamfuncsRunStart;
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extern uint16_t RamfuncsRunEnd;
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extern uint16_t RamfuncsRunSize;
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#define DEVICE_FLASH_WAITSTATES 3
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#endif
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extern uint32_t Example_PassCount;
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extern uint32_t Example_Fail;
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//*****************************************************************************
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//
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// Function Prototypes
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup device_api
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! @brief Function to initialize the device. Primarily initializes system control to a
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//! known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
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//! and enabling the clocks to the peripherals.
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//!
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//! \param None.
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//! \return None.
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//
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//*****************************************************************************
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extern void Device_init(void);
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//*****************************************************************************
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//!
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//!
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//! @brief Function to turn on all peripherals, enabling reads and writes to the
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//! peripherals' registers.
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//!
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//! Note that to reduce power, unused peripherals should be disabled.
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//!
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//! @param None
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//! @return None
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//
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//*****************************************************************************
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extern void Device_enableAllPeripherals(void);
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//*****************************************************************************
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//!
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//!
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//! @brief Function to disable pin locks on GPIOs.
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//!
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//! @param None
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//! @return None
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//
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//*****************************************************************************
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extern void Device_initGPIO(void);
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//*****************************************************************************
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//!
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//! @brief Function to enable pullups for the unbonded GPIOs on the 176PTP package:
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//! GPIOs Grp Bits
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//! 95-132 C 31
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//! D 31:0
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//! E 4:0
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//! 134-168 E 31:6
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//! F 8:0
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//!
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//! @param None
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//! @return None
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//
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//*****************************************************************************
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extern void Device_enableUnbondedGPIOPullupsFor176Pin(void);
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//*****************************************************************************
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//!
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//! @brief Function to enable pullups for the unbonded GPIOs on the 100PZ package:
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//! GPIOs Grp Bits
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//! 0-1 A 1:0
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//! 5-9 A 9:5
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//! 22-40 A 31:22
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//! B 8:0
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//! 44-57 B 25:12
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//! 67-68 C 4:3
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//! 74-77 C 13:10
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//! 79-83 C 19:15
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//! 93-168 C 31:29
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//! D 31:0
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//! E 31:0
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//! F 8:0
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//! @param None
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//! @return None
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//
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//
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//*****************************************************************************
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extern void Device_enableUnbondedGPIOPullupsFor100Pin(void);
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//*****************************************************************************
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//!
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//! @brief Function to enable pullups for the unbonded GPIOs on the
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//! 176PTP package.
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//!
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//! @param None
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//! @return None
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//
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//*****************************************************************************
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extern void Device_enableUnbondedGPIOPullups(void);
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#ifdef CPU1
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//*****************************************************************************
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//!
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//! @brief Function to implement Analog trim of TMX devices
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//!
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//! @param None
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//! @return None
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//
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//*****************************************************************************
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extern void Device_configureTMXAnalogTrim(void);
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//*****************************************************************************
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//! @brief Executes a CPU02 control system bootloader.
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//!
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//! \param bootMode specifies which CPU02 control system boot mode to execute.
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//!
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//! This function will allow the CPU01 master system to boot the CPU02 control
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//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI,
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//! SCI, I2C, or parallel I/O. This function blocks and waits until the
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//! control system boot ROM is configured and ready to receive CPU01 to CPU02
|
||
|
|
//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and
|
||
|
|
//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the
|
||
|
|
//! command to execute the selected bootloader.
|
||
|
|
//!
|
||
|
|
//! The \e bootMode parameter accepts one of the following values:
|
||
|
|
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL
|
||
|
|
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI
|
||
|
|
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI
|
||
|
|
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C
|
||
|
|
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN
|
||
|
|
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM
|
||
|
|
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH
|
||
|
|
//!
|
||
|
|
//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is
|
||
|
|
//! invalid and command was not sent.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern uint16_t Device_bootCPU2(uint32_t ulBootMode);
|
||
|
|
#endif
|
||
|
|
//*****************************************************************************
|
||
|
|
//!
|
||
|
|
//! @brief Error handling function to be called when an ASSERT is violated
|
||
|
|
//!
|
||
|
|
//! @param *filename File name in which the error has occurred
|
||
|
|
//! @param line Line number within the file
|
||
|
|
//! @return None
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern void __error__(const char *filename, uint32_t line);
|
||
|
|
extern void Example_setResultPass(void);
|
||
|
|
extern void Example_setResultFail(void);
|
||
|
|
extern void Example_done(void);
|
||
|
|
|
||
|
|
//
|
||
|
|
// End of file
|
||
|
|
//
|