最初始的空版本,板子验证过没问题
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<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.FLOAT_SUPPORT.1829224539" name="Specify floating point support (--float_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.FLOAT_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.FLOAT_SUPPORT.fpu32" valueType="enumerated"/>
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<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.ABI.1307771009" name="Application binary interface [See 'General' page to edit] (--abi)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.ABI" value="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.ABI.eabi" valueType="enumerated"/>
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<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__CPP_SRCS.133646606" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__CPP_SRCS"/>
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</tool>
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|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.STACK_SIZE.470135001" name="Set C system stack size (--stack_size, -stack)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.STACK_SIZE" value="0x200" valueType="string"/>
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<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.MAP_FILE.1419742500" name="Link information (map) listed into <file> (--map_file, -m)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.MAP_FILE" value="${ProjName}.map" valueType="string"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.OUTPUT_FILE.900642667" name="Specify output file name (--output_file, -o)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.OUTPUT_FILE" value="${ProjName}.out" valueType="string"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.HEAP_SIZE.1585835671" name="Heap size for C/C++ dynamic memory allocation (--heap_size, -heap)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.HEAP_SIZE" value="0x200" valueType="string"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.LIBRARY.794079965" name="Include library file or command file as input (--library, -l)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.LIBRARY" valueType="libs">
|
||||
<listOptionValue builtIn="false" value="${COM_TI_C2000WARE_SOFTWARE_PACKAGE_LIBRARIES}"/>
|
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<listOptionValue builtIn="false" value="rts2800_fpu32_eabi.lib"/>
|
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<listOptionValue builtIn="false" value="libc.a"/>
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|
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<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.SEARCH_PATH.1407208758" name="Add <dir> to library search path (--search_path, -i)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.SEARCH_PATH" valueType="libPaths">
|
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<listOptionValue builtIn="false" value="${COM_TI_C2000WARE_SOFTWARE_PACKAGE_LIBRARY_PATH}"/>
|
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|
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<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
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|
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|
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<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.DISPLAY_ERROR_NUMBER.2118334730" name="Emit diagnostic identifier numbers (--display_error_number)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.XML_LINK_INFO.685136022" name="Detailed link information data-base into <file> (--xml_link_info, -xml_link_info)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.XML_LINK_INFO" value="${ProjName}_linkInfo.xml" valueType="string"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.ENTRY_POINT.288757206" name="Specify program entry point for the output module (--entry_point, -e)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.ENTRY_POINT" value="code_start" valueType="string"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__CMD_SRCS.50474873" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__CMD_SRCS"/>
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<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__CMD2_SRCS.434826687" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__CMD2_SRCS"/>
|
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<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__GEN_CMDS.1124815514" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__GEN_CMDS"/>
|
||||
</tool>
|
||||
<tool id="com.ti.ccstudio.buildDefinitions.C2000_22.6.hex.1487025482" name="C2000 Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.hex"/>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="device/driverlib/ccs/Release/driverlib.lib|device/driverlib/ccs/Release/driverlib_coff.lib|2837xD_RAM_lnk_cpu1.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="template_empty.com.ti.ccstudio.buildDefinitions.C2000.ProjectType.1060187282" name="C2000" projectType="com.ti.ccstudio.buildDefinitions.C2000.ProjectType"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
</cproject>
|
|
@ -0,0 +1,2 @@
|
|||
CPU1_FLASH/
|
||||
CPU1_RAM/
|
File diff suppressed because one or more lines are too long
|
@ -0,0 +1,45 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>template_empty</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>com.ti.ccstudio.core.ccsNature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<variableList>
|
||||
<variable>
|
||||
<name>C2000_COMMON_INCLUDE</name>
|
||||
<value>$%7BC2000_INSTALL_DIR%7D/device_support/f2837xd/common/include</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>C2000_DLIB_ROOT</name>
|
||||
<value>$%7BC2000_INSTALL_DIR%7D/driverlib/f2837xd/driverlib</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>C2000_HEADERS_INCLUDE</name>
|
||||
<value>$%7BC2000_INSTALL_DIR%7D/device_support/f2837xd/headers/include</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>C2000_INSTALL_DIR</name>
|
||||
<value>$%7BCOM_TI_C2000WARE_SOFTWARE_PACKAGE_INSTALL_DIR%7D</value>
|
||||
</variable>
|
||||
</variableList>
|
||||
</projectDescription>
|
|
@ -0,0 +1,3 @@
|
|||
eclipse.preferences.version=1
|
||||
inEditor=false
|
||||
onBuild=false
|
|
@ -0,0 +1,2 @@
|
|||
eclipse.preferences.version=1
|
||||
org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
|
|
@ -0,0 +1,29 @@
|
|||
eclipse.preferences.version=1
|
||||
encoding//CPU1_FLASH/common/subdir_rules.mk=UTF-8
|
||||
encoding//CPU1_FLASH/common/subdir_vars.mk=UTF-8
|
||||
encoding//CPU1_FLASH/device/driverlib/ccs/Release/subdir_rules.mk=UTF-8
|
||||
encoding//CPU1_FLASH/device/driverlib/ccs/Release/subdir_vars.mk=UTF-8
|
||||
encoding//CPU1_FLASH/device/driverlib/subdir_rules.mk=UTF-8
|
||||
encoding//CPU1_FLASH/device/driverlib/subdir_vars.mk=UTF-8
|
||||
encoding//CPU1_FLASH/device/subdir_rules.mk=UTF-8
|
||||
encoding//CPU1_FLASH/device/subdir_vars.mk=UTF-8
|
||||
encoding//CPU1_FLASH/makefile=UTF-8
|
||||
encoding//CPU1_FLASH/objects.mk=UTF-8
|
||||
encoding//CPU1_FLASH/sources.mk=UTF-8
|
||||
encoding//CPU1_FLASH/subdir_rules.mk=UTF-8
|
||||
encoding//CPU1_FLASH/subdir_vars.mk=UTF-8
|
||||
encoding//CPU1_RAM/common/subdir_rules.mk=UTF-8
|
||||
encoding//CPU1_RAM/common/subdir_vars.mk=UTF-8
|
||||
encoding//CPU1_RAM/device/driverlib/ccs/Release/subdir_rules.mk=UTF-8
|
||||
encoding//CPU1_RAM/device/driverlib/ccs/Release/subdir_vars.mk=UTF-8
|
||||
encoding//CPU1_RAM/device/driverlib/subdir_rules.mk=UTF-8
|
||||
encoding//CPU1_RAM/device/driverlib/subdir_vars.mk=UTF-8
|
||||
encoding//CPU1_RAM/device/subdir_rules.mk=UTF-8
|
||||
encoding//CPU1_RAM/device/subdir_vars.mk=UTF-8
|
||||
encoding//CPU1_RAM/makefile=UTF-8
|
||||
encoding//CPU1_RAM/objects.mk=UTF-8
|
||||
encoding//CPU1_RAM/sources.mk=UTF-8
|
||||
encoding//CPU1_RAM/subdir_rules.mk=UTF-8
|
||||
encoding//CPU1_RAM/subdir_vars.mk=UTF-8
|
||||
encoding//FLASH/device/driverlib/ccs/Debug/subdir_rules.mk=UTF-8
|
||||
encoding//FLASH/device/driverlib/ccs/Debug/subdir_vars.mk=UTF-8
|
|
@ -0,0 +1,31 @@
|
|||
{
|
||||
"env": {
|
||||
"C2000_INSTALL_DIR": "D:\\ti\\c2000\\C2000Ware_5_01_00_00",
|
||||
"CG_TOOL_ROOT" : "D:\\ti\\ccs\\tools\\compiler\\ti-cgt-c2000_22.6.1.LTS",
|
||||
|
||||
},
|
||||
"configurations": [
|
||||
{
|
||||
"name": "1",
|
||||
"includePath": [
|
||||
"${C2000_INSTALL_DIR}",
|
||||
"${C2000_INSTALL_DIR}\\device_support\\f2837xd\\common\\include",
|
||||
"${C2000_INSTALL_DIR}\\device_support\\f2837xd\\headers\\include",
|
||||
"${C2000_INSTALL_DIR}\\driverlib\\f2837xd\\driverlib",
|
||||
|
||||
"${workspaceFolder}",
|
||||
"${workspaceFolder}\\device",
|
||||
"${CG_TOOL_ROOT}\\include"
|
||||
],
|
||||
"defines": [
|
||||
"CPU1",
|
||||
"interrupt= ",
|
||||
"__interrupt= "
|
||||
],
|
||||
"intelliSenseMode": "windows-msvc-x64",
|
||||
"cStandard": "c99",
|
||||
"cppStandard": "c++11"
|
||||
}
|
||||
],
|
||||
"version": 4
|
||||
}
|
|
@ -0,0 +1,61 @@
|
|||
{
|
||||
"files.associations": {
|
||||
"stdio.h": "c",
|
||||
"f28x_project.h": "c",
|
||||
"u_cstring": "c",
|
||||
"cstring": "c",
|
||||
"xmemory": "c",
|
||||
"xstring": "c",
|
||||
"sci_init.h": "c",
|
||||
"stdlib.h": "c",
|
||||
"string.h": "c",
|
||||
"timer_init.h": "c",
|
||||
"led_init.h": "c",
|
||||
"cstdint": "cpp",
|
||||
"xutility": "cpp",
|
||||
"*.cla": "c",
|
||||
"cla_init.h": "c",
|
||||
"speedtest.h": "c",
|
||||
"pdpwm.h": "c",
|
||||
"epwm_init.h": "c",
|
||||
"cmath": "c",
|
||||
"compare": "c",
|
||||
"concepts": "c",
|
||||
"exception": "c",
|
||||
"iterator": "c",
|
||||
"string": "c",
|
||||
"tuple": "c",
|
||||
"type_traits": "c",
|
||||
"utility": "c",
|
||||
"*.stdh": "c",
|
||||
"cassert": "c",
|
||||
"cctype": "c",
|
||||
"cfloat": "c",
|
||||
"climits": "c",
|
||||
"cstddef": "c",
|
||||
"cstdio": "c",
|
||||
"cstdlib": "c",
|
||||
"ctime": "c",
|
||||
"cwchar": "c",
|
||||
"iosfwd": "c",
|
||||
"limits": "c",
|
||||
"new": "c",
|
||||
"stdexcept": "c",
|
||||
"f2838x_device.h": "c",
|
||||
"f2838x_cla_typedefs.h": "c",
|
||||
"global_defines.h": "c",
|
||||
"adc_ppb_init_ost.h": "c",
|
||||
"cmpss_init_ost.h": "c",
|
||||
"stdint.h": "c",
|
||||
"sample.h": "c",
|
||||
"pcsfsm.h": "c",
|
||||
"rs485_with_host.h": "c",
|
||||
"fsm_public.h": "c",
|
||||
"fsm_protected.h": "c",
|
||||
"driverlib.h": "c"
|
||||
},
|
||||
"doxdocgen.c.triggerSequence": "///",
|
||||
"doxdocgen.file.copyrightTag": [
|
||||
"@天神创意无限公司 (c) {year}"
|
||||
],
|
||||
}
|
|
@ -0,0 +1,152 @@
|
|||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
|
||||
/* BEGIN is used for the "boot to Flash" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 : /* Data Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMM1 PAGE = 1
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
|
||||
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.bss:cio : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.const : > FLASHF, PAGE = 0, ALIGN(8)
|
||||
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
SHARERAMGS2 : > RAMGS2, PAGE = 1
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
LOAD_END(RamfuncsLoadEnd),
|
||||
RUN_START(RamfuncsRunStart),
|
||||
RUN_SIZE(RamfuncsRunSize),
|
||||
RUN_END(RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
|
||||
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
|
||||
|
||||
ramconsts : LOAD = FLASHF, PAGE = 0
|
||||
RUN = RAMLS5, PAGE = 1
|
||||
LOAD_START(_ramconsts_loadstart),
|
||||
LOAD_SIZE(_ramconsts_loadsize),
|
||||
RUN_START(_ramconsts_runstart)
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
|
@ -0,0 +1,141 @@
|
|||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >> RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
|
@ -0,0 +1,246 @@
|
|||
MEMORY
|
||||
{
|
||||
PAGE 0: /* Program Memory */
|
||||
PAGE 1: /* Data Memory */
|
||||
ACCESSPROTECTION : origin = 0x0005F4C0, length = 0x00000040
|
||||
ADCA : origin = 0x00007400, length = 0x00000080
|
||||
ADCB : origin = 0x00007480, length = 0x00000080
|
||||
ADCC : origin = 0x00007500, length = 0x00000080
|
||||
ADCD : origin = 0x00007580, length = 0x00000080
|
||||
ADCARESULT : origin = 0x00000B00, length = 0x00000018
|
||||
ADCBRESULT : origin = 0x00000B20, length = 0x00000018
|
||||
ADCCRESULT : origin = 0x00000B40, length = 0x00000018
|
||||
ADCDRESULT : origin = 0x00000B60, length = 0x00000018
|
||||
ANALOGSUBSYS : origin = 0x0005D180, length = 0x00000048
|
||||
CANA : origin = 0x00048000, length = 0x00000200
|
||||
CANB : origin = 0x0004A000, length = 0x00000200
|
||||
CLA1 : origin = 0x00001400, length = 0x00000080
|
||||
CLB1DATAEXCH : origin = 0x00003200, length = 0x00000200
|
||||
CLB2DATAEXCH : origin = 0x00003600, length = 0x00000200
|
||||
CLB3DATAEXCH : origin = 0x00003A00, length = 0x00000200
|
||||
CLB4DATAEXCH : origin = 0x00003E00, length = 0x00000200
|
||||
CLB1LOGICCFG : origin = 0x00003000, length = 0x00000052
|
||||
CLB2LOGICCFG : origin = 0x00003400, length = 0x00000052
|
||||
CLB3LOGICCFG : origin = 0x00003800, length = 0x00000052
|
||||
CLB4LOGICCFG : origin = 0x00003C00, length = 0x00000052
|
||||
CLB1LOGICCTRL : origin = 0x00003100, length = 0x00000040
|
||||
CLB2LOGICCTRL : origin = 0x00003500, length = 0x00000040
|
||||
CLB3LOGICCTRL : origin = 0x00003900, length = 0x00000040
|
||||
CLB4LOGICCTRL : origin = 0x00003D00, length = 0x00000040
|
||||
CLBXBAR : origin = 0x00007A40, length = 0x00000040
|
||||
CLKCFG : origin = 0x0005D200, length = 0x00000032
|
||||
CMPSS1 : origin = 0x00005C80, length = 0x00000020
|
||||
CMPSS2 : origin = 0x00005CA0, length = 0x00000020
|
||||
CMPSS3 : origin = 0x00005CC0, length = 0x00000020
|
||||
CMPSS4 : origin = 0x00005CE0, length = 0x00000020
|
||||
CMPSS5 : origin = 0x00005D00, length = 0x00000020
|
||||
CMPSS6 : origin = 0x00005D20, length = 0x00000020
|
||||
CMPSS7 : origin = 0x00005D40, length = 0x00000020
|
||||
CMPSS8 : origin = 0x00005D60, length = 0x00000020
|
||||
CPUTIMER0 : origin = 0x00000C00, length = 0x00000008
|
||||
CPUTIMER1 : origin = 0x00000C08, length = 0x00000008
|
||||
CPUTIMER2 : origin = 0x00000C10, length = 0x00000008
|
||||
CPUSYS : origin = 0x0005D300, length = 0x00000082
|
||||
DACA : origin = 0x00005C00, length = 0x00000008
|
||||
DACB : origin = 0x00005C10, length = 0x00000008
|
||||
DACC : origin = 0x00005C20, length = 0x00000008
|
||||
DCSMCOMMON : origin = 0x0005F070, length = 0x00000008
|
||||
DCSMZ1 : origin = 0x0005F000, length = 0x00000024
|
||||
DCSMZ2 : origin = 0x0005F040, length = 0x00000024
|
||||
DEVCFG : origin = 0x0005D000, length = 0x0000012E
|
||||
DMACLASRCSEL : origin = 0x00007980, length = 0x0000001A
|
||||
DMA : origin = 0x00001000, length = 0x00000200
|
||||
ECAP1 : origin = 0x00005000, length = 0x00000020
|
||||
ECAP2 : origin = 0x00005020, length = 0x00000020
|
||||
ECAP3 : origin = 0x00005040, length = 0x00000020
|
||||
ECAP4 : origin = 0x00005060, length = 0x00000020
|
||||
ECAP5 : origin = 0x00005080, length = 0x00000020
|
||||
ECAP6 : origin = 0x000050A0, length = 0x00000020
|
||||
EMIF1CONFIG : origin = 0x0005F480, length = 0x00000020
|
||||
EMIF2CONFIG : origin = 0x0005F4A0, length = 0x00000020
|
||||
EMIF1 : origin = 0x00047000, length = 0x00000070
|
||||
EMIF2 : origin = 0x00047800, length = 0x00000070
|
||||
EPWM1 : origin = 0x00004000, length = 0x00000100
|
||||
EPWM2 : origin = 0x00004100, length = 0x00000100
|
||||
EPWM3 : origin = 0x00004200, length = 0x00000100
|
||||
EPWM4 : origin = 0x00004300, length = 0x00000100
|
||||
EPWM5 : origin = 0x00004400, length = 0x00000100
|
||||
EPWM6 : origin = 0x00004500, length = 0x00000100
|
||||
EPWM7 : origin = 0x00004600, length = 0x00000100
|
||||
EPWM8 : origin = 0x00004700, length = 0x00000100
|
||||
EPWM9 : origin = 0x00004800, length = 0x00000100
|
||||
EPWM10 : origin = 0x00004900, length = 0x00000100
|
||||
EPWM11 : origin = 0x00004A00, length = 0x00000100
|
||||
EPWM12 : origin = 0x00004B00, length = 0x00000100
|
||||
EPWMXBAR : origin = 0x00007A00, length = 0x00000040
|
||||
EQEP1 : origin = 0x00005100, length = 0x00000022
|
||||
EQEP2 : origin = 0x00005140, length = 0x00000022
|
||||
EQEP3 : origin = 0x00005180, length = 0x00000022
|
||||
FLASH0CTRL : origin = 0x0005F800, length = 0x00000182
|
||||
FLASH0ECC : origin = 0x0005FB00, length = 0x00000028
|
||||
FLASHPUMPSEMAPHORE : origin = 0x00050024, length = 0x00000002
|
||||
GPIOCTRL : origin = 0x00007C00, length = 0x00000180
|
||||
GPIODATA : origin = 0x00007F00, length = 0x00000030
|
||||
I2CA : origin = 0x00007300, length = 0x00000022
|
||||
I2CB : origin = 0x00007340, length = 0x00000022
|
||||
INPUTXBAR : origin = 0x00007900, length = 0x00000020
|
||||
IPC : origin = 0x00050000, length = 0x00000024
|
||||
MEMORYERROR : origin = 0x0005F500, length = 0x00000040
|
||||
MEMCFG : origin = 0x0005F400, length = 0x00000080
|
||||
MCBSPA : origin = 0x00006000, length = 0x00000024
|
||||
MCBSPB : origin = 0x00006040, length = 0x00000024
|
||||
NMIINTRUPT : origin = 0x00007060, length = 0x00000007
|
||||
OUTPUTXBAR : origin = 0x00007A80, length = 0x00000040
|
||||
PIECTRL : origin = 0x00000CE0, length = 0x0000001A
|
||||
PIEVECTTABLE : origin = 0x00000D00, length = 0x00000200
|
||||
ROMPREFETCH : origin = 0x0005E608, length = 0x00000002
|
||||
ROMWAITSTATE : origin = 0x0005F540, length = 0x00000002
|
||||
SCIA : origin = 0x00007200, length = 0x00000010
|
||||
SCIB : origin = 0x00007210, length = 0x00000010
|
||||
SCIC : origin = 0x00007220, length = 0x00000010
|
||||
SCID : origin = 0x00007230, length = 0x00000010
|
||||
SDFM1 : origin = 0x00005E00, length = 0x00000080
|
||||
SDFM2 : origin = 0x00005E80, length = 0x00000080
|
||||
SPIA : origin = 0x00006100, length = 0x00000010
|
||||
SPIB : origin = 0x00006110, length = 0x00000010
|
||||
SPIC : origin = 0x00006120, length = 0x00000010
|
||||
SYNCSOC : origin = 0x00007940, length = 0x00000006
|
||||
UPP : origin = 0x00006200, length = 0x00000048
|
||||
WD : origin = 0x00007000, length = 0x0000002B
|
||||
XBAR : origin = 0x00007920, length = 0x00000020
|
||||
XINT : origin = 0x00007070, length = 0x0000000B
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*** PIE Vect Table and Boot ROM Variables Structures ***/
|
||||
UNION run = PIEVECTTABLE
|
||||
{
|
||||
PieVectTableFile
|
||||
GROUP
|
||||
{
|
||||
EmuKeyVar
|
||||
EmuBModeVar
|
||||
EmuBootPinsVar
|
||||
FlashCallbackVar
|
||||
FlashScalingVar
|
||||
}
|
||||
}
|
||||
|
||||
AccessProtectionRegsFile : > ACCESSPROTECTION, type=NOINIT
|
||||
AdcaRegsFile : > ADCA, type=NOINIT
|
||||
AdcbRegsFile : > ADCB, type=NOINIT
|
||||
AdccRegsFile : > ADCC, type=NOINIT
|
||||
AdcdRegsFile : > ADCD, type=NOINIT
|
||||
AdcaResultRegsFile : > ADCARESULT, type=NOINIT
|
||||
AdcbResultRegsFile : > ADCBRESULT, type=NOINIT
|
||||
AdccResultRegsFile : > ADCCRESULT, type=NOINIT
|
||||
AdcdResultRegsFile : > ADCDRESULT, type=NOINIT
|
||||
AnalogSubsysRegsFile : > ANALOGSUBSYS, type=NOINIT
|
||||
CanaRegsFile : > CANA, type=NOINIT
|
||||
CanbRegsFile : > CANB, type=NOINIT
|
||||
Cla1RegsFile : > CLA1, type=NOINIT
|
||||
Clb1DataExchRegsFile : > CLB1DATAEXCH, type=NOINIT
|
||||
Clb2DataExchRegsFile : > CLB2DATAEXCH, type=NOINIT
|
||||
Clb3DataExchRegsFile : > CLB3DATAEXCH, type=NOINIT
|
||||
Clb4DataExchRegsFile : > CLB4DATAEXCH, type=NOINIT
|
||||
Clb1LogicCfgRegsFile : > CLB1LOGICCFG, type=NOINIT
|
||||
Clb2LogicCfgRegsFile : > CLB2LOGICCFG, type=NOINIT
|
||||
Clb3LogicCfgRegsFile : > CLB3LOGICCFG, type=NOINIT
|
||||
Clb4LogicCfgRegsFile : > CLB4LOGICCFG, type=NOINIT
|
||||
Clb1LogicCtrlRegsFile : > CLB1LOGICCTRL, type=NOINIT
|
||||
Clb2LogicCtrlRegsFile : > CLB2LOGICCTRL, type=NOINIT
|
||||
Clb3LogicCtrlRegsFile : > CLB3LOGICCTRL, type=NOINIT
|
||||
Clb4LogicCtrlRegsFile : > CLB4LOGICCTRL, type=NOINIT
|
||||
ClbXbarRegsFile : > CLBXBAR, type=NOINIT
|
||||
ClkCfgRegsFile : > CLKCFG, type=NOINIT
|
||||
Cmpss1RegsFile : > CMPSS1, type=NOINIT
|
||||
Cmpss2RegsFile : > CMPSS2, type=NOINIT
|
||||
Cmpss3RegsFile : > CMPSS3, type=NOINIT
|
||||
Cmpss4RegsFile : > CMPSS4, type=NOINIT
|
||||
Cmpss5RegsFile : > CMPSS5, type=NOINIT
|
||||
Cmpss6RegsFile : > CMPSS6, type=NOINIT
|
||||
Cmpss7RegsFile : > CMPSS7, type=NOINIT
|
||||
Cmpss8RegsFile : > CMPSS8, type=NOINIT
|
||||
CpuTimer0RegsFile : > CPUTIMER0, type=NOINIT
|
||||
CpuTimer1RegsFile : > CPUTIMER1, type=NOINIT
|
||||
CpuTimer2RegsFile : > CPUTIMER2, type=NOINIT
|
||||
CpuSysRegsFile : > CPUSYS, type=NOINIT
|
||||
DacaRegsFile : > DACA, type=NOINIT
|
||||
DacbRegsFile : > DACB, type=NOINIT
|
||||
DaccRegsFile : > DACC, type=NOINIT
|
||||
DcsmCommonRegsFile : > DCSMCOMMON, type=NOINIT
|
||||
DcsmZ1RegsFile : > DCSMZ1, type=NOINIT
|
||||
DcsmZ2RegsFile : > DCSMZ2, type=NOINIT
|
||||
DevCfgRegsFile : > DEVCFG, type=NOINIT
|
||||
DmaClaSrcSelRegsFile : > DMACLASRCSEL, type=NOINIT
|
||||
DmaRegsFile : > DMA, type=NOINIT
|
||||
ECap1RegsFile : > ECAP1, type=NOINIT
|
||||
ECap2RegsFile : > ECAP2, type=NOINIT
|
||||
ECap3RegsFile : > ECAP3, type=NOINIT
|
||||
ECap4RegsFile : > ECAP4, type=NOINIT
|
||||
ECap5RegsFile : > ECAP5, type=NOINIT
|
||||
ECap6RegsFile : > ECAP6, type=NOINIT
|
||||
Emif1ConfigRegsFile : > EMIF1CONFIG, type=NOINIT
|
||||
Emif2ConfigRegsFile : > EMIF2CONFIG, type=NOINIT
|
||||
Emif1RegsFile : > EMIF1, type=NOINIT
|
||||
Emif2RegsFile : > EMIF2, type=NOINIT
|
||||
EPwm1RegsFile : > EPWM1, type=NOINIT
|
||||
EPwm2RegsFile : > EPWM2, type=NOINIT
|
||||
EPwm3RegsFile : > EPWM3, type=NOINIT
|
||||
EPwm4RegsFile : > EPWM4, type=NOINIT
|
||||
EPwm5RegsFile : > EPWM5, type=NOINIT
|
||||
EPwm6RegsFile : > EPWM6, type=NOINIT
|
||||
EPwm7RegsFile : > EPWM7, type=NOINIT
|
||||
EPwm8RegsFile : > EPWM8, type=NOINIT
|
||||
EPwm9RegsFile : > EPWM9, type=NOINIT
|
||||
EPwm10RegsFile : > EPWM10, type=NOINIT
|
||||
EPwm11RegsFile : > EPWM11, type=NOINIT
|
||||
EPwm12RegsFile : > EPWM12, type=NOINIT
|
||||
EPwmXbarRegsFile : > EPWMXBAR, type=NOINIT
|
||||
EQep1RegsFile : > EQEP1, type=NOINIT
|
||||
EQep2RegsFile : > EQEP2, type=NOINIT
|
||||
EQep3RegsFile : > EQEP3, type=NOINIT
|
||||
Flash0CtrlRegsFile : > FLASH0CTRL, type=NOINIT
|
||||
Flash0EccRegsFile : > FLASH0ECC, type=NOINIT
|
||||
FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, type=NOINIT
|
||||
GpioCtrlRegsFile : > GPIOCTRL, type=NOINIT
|
||||
GpioDataRegsFile : > GPIODATA, type=NOINIT
|
||||
I2caRegsFile : > I2CA, type=NOINIT
|
||||
I2cbRegsFile : > I2CB, type=NOINIT
|
||||
InputXbarRegsFile : > INPUTXBAR, type=NOINIT
|
||||
IpcRegsFile : > IPC, type=NOINIT
|
||||
MemoryErrorRegsFile : > MEMORYERROR, type=NOINIT
|
||||
MemCfgRegsFile : > MEMCFG, type=NOINIT
|
||||
McbspaRegsFile : > MCBSPA, type=NOINIT
|
||||
McbspbRegsFile : > MCBSPB, type=NOINIT
|
||||
NmiIntruptRegsFile : > NMIINTRUPT, type=NOINIT
|
||||
OutputXbarRegsFile : > OUTPUTXBAR, type=NOINIT
|
||||
PieCtrlRegsFile : > PIECTRL, type=NOINIT
|
||||
PieVectTableFile : > PIEVECTTABLE, type=NOINIT
|
||||
RomPrefetchRegsFile : > ROMPREFETCH, type=NOINIT
|
||||
RomWaitStateRegsFile : > ROMWAITSTATE, type=NOINIT
|
||||
SciaRegsFile : > SCIA, type=NOINIT
|
||||
ScibRegsFile : > SCIB, type=NOINIT
|
||||
ScicRegsFile : > SCIC, type=NOINIT
|
||||
ScidRegsFile : > SCID, type=NOINIT
|
||||
Sdfm1RegsFile : > SDFM1, type=NOINIT
|
||||
Sdfm2RegsFile : > SDFM2, type=NOINIT
|
||||
SpiaRegsFile : > SPIA, type=NOINIT
|
||||
SpibRegsFile : > SPIB, type=NOINIT
|
||||
SpicRegsFile : > SPIC, type=NOINIT
|
||||
SyncSocRegsFile : > SYNCSOC, type=NOINIT
|
||||
UppRegsFile : > UPP, type=NOINIT
|
||||
WdRegsFile : > WD, type=NOINIT
|
||||
XbarRegsFile : > XBAR, type=NOINIT
|
||||
XintRegsFile : > XINT, type=NOINIT
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
;//###########################################################################
|
||||
;//
|
||||
;// FILE: F2837xD_CodeStartBranch.asm
|
||||
;//
|
||||
;// TITLE: Branch for redirecting code execution after boot.
|
||||
;//
|
||||
;// For these examples, code_start is the first code that is executed after
|
||||
;// exiting the boot ROM code.
|
||||
;//
|
||||
;// The codestart section in the linker cmd file is used to physically place
|
||||
;// this code at the correct memory location. This section should be placed
|
||||
;// at the location the BOOT ROM will re-direct the code to. For example,
|
||||
;// for boot to FLASH this code will be located at 0x3f7ff6.
|
||||
;//
|
||||
;// In addition, the example F2837xD projects are setup such that the codegen
|
||||
;// entry point is also set to the code_start label. This is done by linker
|
||||
;// option -e in the project build options. When the debugger loads the code,
|
||||
;// it will automatically set the PC to the "entry point" address indicated by
|
||||
;// the -e linker option. In this case the debugger is simply assigning the PC,
|
||||
;// it is not the same as a full reset of the device.
|
||||
;//
|
||||
;// The compiler may warn that the entry point for the project is other then
|
||||
;// _c_init00. _c_init00 is the C environment setup and is run before
|
||||
;// main() is entered. The code_start code will re-direct the execution
|
||||
;// to _c_init00 and thus there is no worry and this warning can be ignored.
|
||||
;//
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// $Release Date: $
|
||||
;// $Copyright:
|
||||
;// Copyright (C) 2013-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
;//
|
||||
;// Redistribution and use in source and binary forms, with or without
|
||||
;// modification, are permitted provided that the following conditions
|
||||
;// are met:
|
||||
;//
|
||||
;// Redistributions of source code must retain the above copyright
|
||||
;// notice, this list of conditions and the following disclaimer.
|
||||
;//
|
||||
;// Redistributions in binary form must reproduce the above copyright
|
||||
;// notice, this list of conditions and the following disclaimer in the
|
||||
;// documentation and/or other materials provided with the
|
||||
;// distribution.
|
||||
;//
|
||||
;// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
;// its contributors may be used to endorse or promote products derived
|
||||
;// from this software without specific prior written permission.
|
||||
;//
|
||||
;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;// $
|
||||
;//###########################################################################
|
||||
|
||||
***********************************************************************
|
||||
|
||||
WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0
|
||||
|
||||
.ref _c_int00
|
||||
.global code_start
|
||||
|
||||
***********************************************************************
|
||||
* Function: codestart section
|
||||
*
|
||||
* Description: Branch to code starting point
|
||||
***********************************************************************
|
||||
|
||||
.sect "codestart"
|
||||
.retain
|
||||
|
||||
code_start:
|
||||
.if WD_DISABLE == 1
|
||||
LB wd_disable ;Branch to watchdog disable code
|
||||
.else
|
||||
LB _c_int00 ;Branch to start of boot._asm in RTS library
|
||||
.endif
|
||||
|
||||
;end codestart section
|
||||
|
||||
***********************************************************************
|
||||
* Function: wd_disable
|
||||
*
|
||||
* Description: Disables the watchdog timer
|
||||
***********************************************************************
|
||||
.if WD_DISABLE == 1
|
||||
|
||||
.text
|
||||
wd_disable:
|
||||
SETC OBJMODE ;Set OBJMODE for 28x object code
|
||||
EALLOW ;Enable EALLOW protected register access
|
||||
MOVZ DP, #7029h>>6 ;Set data page for WDCR register
|
||||
MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
|
||||
EDIS ;Disable EALLOW protected register access
|
||||
LB _c_int00 ;Branch to start of boot._asm in RTS library
|
||||
|
||||
.endif
|
||||
|
||||
;end wd_disable
|
||||
|
||||
.end
|
||||
|
||||
;//
|
||||
;// End of file.
|
||||
;//
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,953 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_globalvariabledefs.c
|
||||
//
|
||||
// TITLE: F2837xD Global Variables and Data Section Pragmas.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "F2837xD_device.h" // F2837xD Headerfile Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Define Global Peripheral Variables:
|
||||
//
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AccessProtectionRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile");
|
||||
#endif
|
||||
volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_REGS AdcaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_REGS AdcbRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdccRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdccRegs,"AdccRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_REGS AdccRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcdRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcdRegs,"AdcdRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_REGS AdcdRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcaResultRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_RESULT_REGS AdcaResultRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcbResultRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_RESULT_REGS AdcbResultRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdccResultRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdccResultRegs,"AdccResultRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_RESULT_REGS AdccResultRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcdResultRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcdResultRegs,"AdcdResultRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_RESULT_REGS AdcdResultRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AnalogSubsysRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile");
|
||||
#endif
|
||||
volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
#if __TI_COMPILER_VERSION__ >= 16006000
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CanaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CanaRegs,"CanaRegsFile");
|
||||
#endif
|
||||
volatile struct CAN_REGS CanaRegs;
|
||||
#endif // __TI_COMPILER_VERSION__ >= 16006000
|
||||
|
||||
#if __TI_COMPILER_VERSION__ >= 16006000
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CanbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CanbRegs,"CanbRegsFile");
|
||||
#endif
|
||||
volatile struct CAN_REGS CanbRegs;
|
||||
#endif // __TI_COMPILER_VERSION__ >= 16006000
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cla1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile");
|
||||
#endif
|
||||
volatile struct CLA_REGS Cla1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb1DataExchRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb1DataExchRegs,"Clb1DataExchRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_DATA_EXCHANGE_REGS Clb1DataExchRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb2DataExchRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb2DataExchRegs,"Clb2DataExchRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_DATA_EXCHANGE_REGS Clb2DataExchRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb3DataExchRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb3DataExchRegs,"Clb3DataExchRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_DATA_EXCHANGE_REGS Clb3DataExchRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb4DataExchRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb4DataExchRegs,"Clb4DataExchRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_DATA_EXCHANGE_REGS Clb4DataExchRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb1LogicCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb1LogicCfgRegs,"Clb1LogicCfgRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONFIG_REGS Clb1LogicCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb2LogicCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb2LogicCfgRegs,"Clb2LogicCfgRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONFIG_REGS Clb2LogicCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb3LogicCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb3LogicCfgRegs,"Clb3LogicCfgRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONFIG_REGS Clb3LogicCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb4LogicCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb4LogicCfgRegs,"Clb4LogicCfgRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONFIG_REGS Clb4LogicCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb1LogicCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb1LogicCtrlRegs,"Clb1LogicCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONTROL_REGS Clb1LogicCtrlRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb2LogicCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb2LogicCtrlRegs,"Clb2LogicCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONTROL_REGS Clb2LogicCtrlRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb3LogicCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb3LogicCtrlRegs,"Clb3LogicCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONTROL_REGS Clb3LogicCtrlRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb4LogicCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb4LogicCtrlRegs,"Clb4LogicCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONTROL_REGS Clb4LogicCtrlRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ClbXbarRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ClbXbarRegs,"ClbXbarRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_XBAR_REGS ClbXbarRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ClkCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile");
|
||||
#endif
|
||||
volatile struct CLK_CFG_REGS ClkCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss3RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss3Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss4RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss4Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss5RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss5Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss6RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss6Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss7RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss7Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss8RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss8Regs,"Cmpss8RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss8Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CpuTimer0RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile");
|
||||
#endif
|
||||
volatile struct CPUTIMER_REGS CpuTimer0Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CpuTimer1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile");
|
||||
#endif
|
||||
volatile struct CPUTIMER_REGS CpuTimer1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CpuTimer2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile");
|
||||
#endif
|
||||
volatile struct CPUTIMER_REGS CpuTimer2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CpuSysRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile");
|
||||
#endif
|
||||
volatile struct CPU_SYS_REGS CpuSysRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DacaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DacaRegs,"DacaRegsFile");
|
||||
#endif
|
||||
volatile struct DAC_REGS DacaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DacbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DacbRegs,"DacbRegsFile");
|
||||
#endif
|
||||
volatile struct DAC_REGS DacbRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DaccRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DaccRegs,"DaccRegsFile");
|
||||
#endif
|
||||
volatile struct DAC_REGS DaccRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DcsmCommonRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile");
|
||||
#endif
|
||||
volatile struct DCSM_COMMON_REGS DcsmCommonRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DcsmZ1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DcsmZ1Regs,"DcsmZ1RegsFile");
|
||||
#endif
|
||||
volatile struct DCSM_Z1_REGS DcsmZ1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DcsmZ2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DcsmZ2Regs,"DcsmZ2RegsFile");
|
||||
#endif
|
||||
volatile struct DCSM_Z2_REGS DcsmZ2Regs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DevCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile");
|
||||
#endif
|
||||
volatile struct DEV_CFG_REGS DevCfgRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DmaClaSrcSelRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile");
|
||||
#endif
|
||||
volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DmaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DmaRegs,"DmaRegsFile");
|
||||
#endif
|
||||
volatile struct DMA_REGS DmaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap3RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap3Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap4RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap4Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap5RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap5Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap6RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap6Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Emif1ConfigRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Emif1ConfigRegs,"Emif1ConfigRegsFile");
|
||||
#endif
|
||||
volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Emif2ConfigRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Emif2ConfigRegs,"Emif2ConfigRegsFile");
|
||||
#endif
|
||||
volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Emif1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Emif1Regs,"Emif1RegsFile");
|
||||
#endif
|
||||
volatile struct EMIF_REGS Emif1Regs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Emif2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Emif2Regs,"Emif2RegsFile");
|
||||
#endif
|
||||
volatile struct EMIF_REGS Emif2Regs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm3RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm3Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm4RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm4Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm5RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm5Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm6RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm6Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm7RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm7Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm8RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm8Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm9RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm9Regs,"EPwm9RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm9Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm10RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm10Regs,"EPwm10RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm10Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm11RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm11Regs,"EPwm11RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm11Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm12RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm12Regs,"EPwm12RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm12Regs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwmXbarRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_XBAR_REGS EPwmXbarRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EQep1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile");
|
||||
#endif
|
||||
volatile struct EQEP_REGS EQep1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EQep2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile");
|
||||
#endif
|
||||
volatile struct EQEP_REGS EQep2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EQep3RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EQep3Regs,"EQep3RegsFile");
|
||||
#endif
|
||||
volatile struct EQEP_REGS EQep3Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Flash0CtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile");
|
||||
#endif
|
||||
volatile struct FLASH_CTRL_REGS Flash0CtrlRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Flash0EccRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile");
|
||||
#endif
|
||||
volatile struct FLASH_ECC_REGS Flash0EccRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile");
|
||||
#endif
|
||||
volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("GpioCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("GpioDataRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile");
|
||||
#endif
|
||||
volatile struct GPIO_DATA_REGS GpioDataRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("I2caRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(I2caRegs,"I2caRegsFile");
|
||||
#endif
|
||||
volatile struct I2C_REGS I2caRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("I2cbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(I2cbRegs,"I2cbRegsFile");
|
||||
#endif
|
||||
volatile struct I2C_REGS I2cbRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("InputXbarRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile");
|
||||
#endif
|
||||
volatile struct INPUT_XBAR_REGS InputXbarRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("IpcRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(IpcRegs,"IpcRegsFile");
|
||||
#endif
|
||||
volatile struct IPC_REGS_CPU1 IpcRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
#ifdef CPU2
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("IpcRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(IpcRegs,"IpcRegsFile");
|
||||
#endif
|
||||
volatile struct IPC_REGS_CPU2 IpcRegs;
|
||||
#endif // ifdef CPU2
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("MemoryErrorRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile");
|
||||
#endif
|
||||
volatile struct MEMORY_ERROR_REGS MemoryErrorRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("MemCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile");
|
||||
#endif
|
||||
volatile struct MEM_CFG_REGS MemCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("McbspaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile");
|
||||
#endif
|
||||
volatile struct McBSP_REGS McbspaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("McbspbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile");
|
||||
#endif
|
||||
volatile struct McBSP_REGS McbspbRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("NmiIntruptRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile");
|
||||
#endif
|
||||
volatile struct NMI_INTRUPT_REGS NmiIntruptRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("OutputXbarRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile");
|
||||
#endif
|
||||
volatile struct OUTPUT_XBAR_REGS OutputXbarRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("PieCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct PIE_CTRL_REGS PieCtrlRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("PieVectTableFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(PieVectTable,"PieVectTableFile");
|
||||
#endif
|
||||
volatile struct PIE_VECT_TABLE PieVectTable;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("RomPrefetchRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(RomPrefetchRegs,"RomPrefetchRegsFile");
|
||||
#endif
|
||||
volatile struct ROM_PREFETCH_REGS RomPrefetchRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("RomWaitStateRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(RomWaitStateRegs,"RomWaitStateRegsFile");
|
||||
#endif
|
||||
volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SciaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SciaRegs,"SciaRegsFile");
|
||||
#endif
|
||||
volatile struct SCI_REGS SciaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ScibRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ScibRegs,"ScibRegsFile");
|
||||
#endif
|
||||
volatile struct SCI_REGS ScibRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ScicRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ScicRegs,"ScicRegsFile");
|
||||
#endif
|
||||
volatile struct SCI_REGS ScicRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ScidRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ScidRegs,"ScidRegsFile");
|
||||
#endif
|
||||
volatile struct SCI_REGS ScidRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Sdfm1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile");
|
||||
#endif
|
||||
volatile struct SDFM_REGS Sdfm1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Sdfm2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Sdfm2Regs,"Sdfm2RegsFile");
|
||||
#endif
|
||||
volatile struct SDFM_REGS Sdfm2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SpiaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile");
|
||||
#endif
|
||||
volatile struct SPI_REGS SpiaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SpibRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SpibRegs,"SpibRegsFile");
|
||||
#endif
|
||||
volatile struct SPI_REGS SpibRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SpicRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SpicRegs,"SpicRegsFile");
|
||||
#endif
|
||||
volatile struct SPI_REGS SpicRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SyncSocRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile");
|
||||
#endif
|
||||
volatile struct SYNC_SOC_REGS SyncSocRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("UppRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(UppRegs,"UppRegsFile");
|
||||
#endif
|
||||
volatile struct UPP_REGS UppRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("WdRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(WdRegs,"WdRegsFile");
|
||||
#endif
|
||||
volatile struct WD_REGS WdRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("XbarRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(XbarRegs,"XbarRegsFile");
|
||||
#endif
|
||||
volatile struct XBAR_REGS XbarRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("XintRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(XintRegs,"XintRegsFile");
|
||||
#endif
|
||||
volatile struct XINT_REGS XintRegs;
|
||||
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
|
||||
|
|
@ -0,0 +1,506 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Gpio.c
|
||||
//
|
||||
// TITLE: GPIO module support functions
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
//Low-level functions for GPIO configuration (CPU1 only)
|
||||
//
|
||||
|
||||
#ifdef CPU1
|
||||
//
|
||||
// InitGpio - Sets all pins to be muxed to GPIO in input mode.
|
||||
// Also resets CPU control to CPU1 and disables open
|
||||
// drain and polarity inversion and sets the qualification to
|
||||
// synchronous. Also unlocks all GPIOs. Only one CPU should call
|
||||
// this function.
|
||||
//
|
||||
void InitGpio()
|
||||
{
|
||||
volatile Uint32 *gpioBaseAddr;
|
||||
Uint16 regOffset;
|
||||
|
||||
//
|
||||
//Disable pin locks
|
||||
//
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPALOCK.all = 0x00000000;
|
||||
GpioCtrlRegs.GPBLOCK.all = 0x00000000;
|
||||
GpioCtrlRegs.GPCLOCK.all = 0x00000000;
|
||||
GpioCtrlRegs.GPDLOCK.all = 0x00000000;
|
||||
GpioCtrlRegs.GPELOCK.all = 0x00000000;
|
||||
GpioCtrlRegs.GPFLOCK.all = 0x00000000;
|
||||
|
||||
//
|
||||
// Fill all registers with zeros. Writing to each register separately
|
||||
// for six GPIO modules would make this function *very* long.
|
||||
// Fortunately, we'd be writing them all with zeros anyway, so this
|
||||
// saves a lot of space.
|
||||
//
|
||||
gpioBaseAddr = (Uint32 *)&GpioCtrlRegs;
|
||||
for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++)
|
||||
{
|
||||
//
|
||||
//Hack to avoid enabling pull-ups on all pins. GPyPUD is offset
|
||||
//0x0C in each register group of 0x40 words. Since this is a
|
||||
//32-bit pointer, the addresses must be divided by 2.
|
||||
//
|
||||
if (regOffset % (0x40/2) != (0x0C/2))
|
||||
{
|
||||
gpioBaseAddr[regOffset] = 0x00000000;
|
||||
}
|
||||
}
|
||||
|
||||
gpioBaseAddr = (Uint32 *)&GpioDataRegs;
|
||||
for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++)
|
||||
{
|
||||
gpioBaseAddr[regOffset] = 0x00000000;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. The
|
||||
// appropriate parameters can be found in the GPIO Muxed
|
||||
// Pins table(4.4) in the datasheet. Use the GPIO index
|
||||
// row (0 to 15) to select a muxing option for the GPIO.
|
||||
//
|
||||
void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition)
|
||||
{
|
||||
volatile Uint32 *gpioBaseAddr;
|
||||
volatile Uint32 *mux, *gmux, *csel;
|
||||
Uint16 pin32, pin16, pin8;
|
||||
|
||||
pin32 = gpioNumber % 32;
|
||||
pin16 = gpioNumber % 16;
|
||||
pin8 = gpioNumber % 8;
|
||||
gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
|
||||
|
||||
//
|
||||
//Sanity check for valid cpu and peripheral values
|
||||
//
|
||||
if (cpu > GPIO_MUX_CPU2CLA || muxPosition > 0xF)
|
||||
return;
|
||||
|
||||
//
|
||||
//Create pointers to the appropriate registers. This is a workaround
|
||||
//for the way GPIO registers are defined. The standard definition
|
||||
//in the header file makes it very easy to do named accesses of one
|
||||
//register or bit, but hard to do arbitrary numerical accesses. It's
|
||||
//easier to have an array of GPIO modules with identical registers,
|
||||
//including arrays for multi-register groups like GPyCSEL1-4. But
|
||||
//the header file doesn't define anything we can turn into an array,
|
||||
//so manual pointer arithmetic is used instead.
|
||||
//
|
||||
mux = gpioBaseAddr + GPYMUX + pin32/16;
|
||||
gmux = gpioBaseAddr + GPYGMUX + pin32/16;
|
||||
csel = gpioBaseAddr + GPYCSEL + pin32/8;
|
||||
|
||||
//
|
||||
//Now for the actual function
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
//To change the muxing, set the peripheral mux to 0/GPIO first to avoid
|
||||
//glitches, then change the group mux, then set the peripheral mux to
|
||||
//its target value. Finally, set the CPU select. This procedure is
|
||||
//described in the TRM. Unfortunately, since we don't know the pin in
|
||||
//advance we can't hardcode a bitfield reference, so there's some
|
||||
//tricky bit twiddling here.
|
||||
//
|
||||
*mux &= ~(0x3UL << (2*pin16));
|
||||
*gmux &= ~(0x3UL << (2*pin16));
|
||||
*gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16);
|
||||
*mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16);
|
||||
|
||||
*csel &= ~(0x3L << (4*pin8));
|
||||
*csel |= (Uint32)(cpu & 0x3L) << (4*pin8);
|
||||
|
||||
//
|
||||
//WARNING: This code does not touch the analog mode select registers,
|
||||
//which are needed to give the USB module control of its IOs.
|
||||
//
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_SetupPinOptions - Setup up the GPIO input/output options for the
|
||||
// specified pin.
|
||||
//
|
||||
//The flags are a 16-bit mask produced by ORing together options.
|
||||
//For input pins, the valid flags are:
|
||||
//GPIO_PULLUP Enable pull-up
|
||||
//GPIO_INVERT Enable input polarity inversion
|
||||
//GPIO_SYNC Synchronize the input latch to PLLSYSCLK
|
||||
// (default -- you don't need to specify this)
|
||||
//GPIO_QUAL3 Use 3-sample qualification
|
||||
//GPIO_QUAL6 Use 6-sample qualification
|
||||
//GPIO_ASYNC Do not use synchronization or qualification
|
||||
//(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed)
|
||||
//
|
||||
//For output pins, the valid flags are:
|
||||
//GPIO_OPENDRAIN Output in open drain mode
|
||||
//GPIO_PULLUP If open drain enabled, also enable the pull-up
|
||||
//and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above.
|
||||
//
|
||||
//With no flags, the default input state is synchronous with no
|
||||
//pull-up or polarity inversion. The default output state is
|
||||
//the standard digital output.
|
||||
//
|
||||
void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags)
|
||||
{
|
||||
volatile Uint32 *gpioBaseAddr;
|
||||
volatile Uint32 *dir, *pud, *inv, *odr, *qsel;
|
||||
Uint32 pin32, pin16, pinMask, qual;
|
||||
|
||||
pin32 = gpioNumber % 32;
|
||||
pin16 = gpioNumber % 16;
|
||||
pinMask = 1UL << pin32;
|
||||
gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
|
||||
|
||||
//
|
||||
//Create pointers to the appropriate registers. This is a workaround
|
||||
//for the way GPIO registers are defined. The standard definition
|
||||
//in the header file makes it very easy to do named accesses of one
|
||||
//register or bit, but hard to do arbitrary numerical accesses. It's
|
||||
//easier to have an array of GPIO modules with identical registers,
|
||||
//including arrays for multi-register groups like GPyQSEL1-2. But
|
||||
//the header file doesn't define anything we can turn into an array,
|
||||
//so manual pointer arithmetic is used instead.
|
||||
//
|
||||
dir = gpioBaseAddr + GPYDIR;
|
||||
pud = gpioBaseAddr + GPYPUD;
|
||||
inv = gpioBaseAddr + GPYINV;
|
||||
odr = gpioBaseAddr + GPYODR;
|
||||
qsel = gpioBaseAddr + GPYQSEL + pin32/16;
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
//Set the data direction
|
||||
//
|
||||
*dir &= ~pinMask;
|
||||
if (output == 1)
|
||||
{
|
||||
//
|
||||
//Output, with optional open drain mode and pull-up
|
||||
//
|
||||
*dir |= pinMask;
|
||||
|
||||
//
|
||||
//Enable open drain if necessary
|
||||
//
|
||||
if (flags & GPIO_OPENDRAIN)
|
||||
{
|
||||
*odr |= pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
*odr &= ~pinMask;
|
||||
}
|
||||
|
||||
//
|
||||
//Enable pull-up if necessary. Open drain mode must be active.
|
||||
//
|
||||
if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP))
|
||||
{
|
||||
*pud &= ~pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pud |= pinMask;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
//Input, with optional pull-up, qualification, and polarity
|
||||
//inversion
|
||||
//
|
||||
*dir &= ~pinMask;
|
||||
|
||||
//
|
||||
//Enable pull-up if necessary
|
||||
//
|
||||
if (flags & GPIO_PULLUP)
|
||||
{
|
||||
*pud &= ~pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pud |= pinMask;
|
||||
}
|
||||
|
||||
//
|
||||
//Invert polarity if necessary
|
||||
//
|
||||
if (flags & GPIO_INVERT)
|
||||
{
|
||||
*inv |= pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
*inv &= ~pinMask;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
//Extract the qualification parameter and load it into the register.
|
||||
//This is also needed for open drain outputs, so we might as well do it
|
||||
//all the time.
|
||||
//
|
||||
qual = (flags & GPIO_ASYNC) / GPIO_QUAL3;
|
||||
*qsel &= ~(0x3L << (2 * pin16));
|
||||
if (qual != 0x0)
|
||||
{
|
||||
*qsel |= qual << (2 * pin16);
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_SetupLock - Enable or disable the GPIO register bit lock for the
|
||||
// specified pin.
|
||||
// The valid flags are:
|
||||
// GPIO_UNLOCK - Unlock the pin setup register bits for
|
||||
// the specified pin
|
||||
// GPIO_LOCK - Lock the pin setup register bits for the
|
||||
// specified pin
|
||||
//
|
||||
void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags)
|
||||
{
|
||||
volatile Uint32 *gpioBaseAddr;
|
||||
volatile Uint32 *lock;
|
||||
Uint32 pin32, pinMask;
|
||||
|
||||
pin32 = gpioNumber % 32;
|
||||
pinMask = 1UL << pin32;
|
||||
gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
|
||||
|
||||
//
|
||||
//Create pointers to the appropriate registers. This is a workaround
|
||||
//for the way GPIO registers are defined. The standard definition
|
||||
//in the header file makes it very easy to do named accesses of one
|
||||
//register or bit, but hard to do arbitrary numerical accesses. It's
|
||||
//easier to have an array of GPIO modules with identical registers,
|
||||
//including arrays for multi-register groups like GPyQSEL1-2. But
|
||||
//the header file doesn't define anything we can turn into an array,
|
||||
//so manual pointer arithmetic is used instead.
|
||||
//
|
||||
lock = gpioBaseAddr + GPYLOCK;
|
||||
|
||||
EALLOW;
|
||||
if(flags)
|
||||
{
|
||||
//Lock the pin
|
||||
*lock |= pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
//Unlock the pin
|
||||
*lock &= ~pinMask;
|
||||
}
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
//External interrupt setup
|
||||
//
|
||||
void GPIO_SetupXINT1Gpio(Uint16 gpioNumber)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT4SELECT = gpioNumber; //Set XINT1 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
void GPIO_SetupXINT2Gpio(Uint16 gpioNumber)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT5SELECT = gpioNumber; //Set XINT2 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
void GPIO_SetupXINT3Gpio(Uint16 gpioNumber)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT6SELECT = gpioNumber; //Set XINT3 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
void GPIO_SetupXINT4Gpio(Uint16 gpioNumber)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT13SELECT = gpioNumber; //Set XINT4 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
void GPIO_SetupXINT5Gpio(Uint16 gpioNumber)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT14SELECT = gpioNumber; //Set XINT5 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
//GPIO_EnableUnbondedIOPullupsFor176Pin - Enable pullups for the unbonded
|
||||
// GPIOs on the 176PTP package:
|
||||
// GPIOs Grp Bits
|
||||
// 95-132 C 31
|
||||
// D 31:0
|
||||
// E 4:0
|
||||
// 134-168 E 31:6
|
||||
// F 8:0
|
||||
//
|
||||
void GPIO_EnableUnbondedIOPullupsFor176Pin()
|
||||
{
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95
|
||||
GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127
|
||||
GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF; //GPIOs 128-159 except for 133
|
||||
GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_EnableUnbondedIOPullupsFor100Pin - Enable pullups for the unbonded
|
||||
// GPIOs on the 100PZ package:
|
||||
// GPIOs Grp Bits
|
||||
// 0-1 A 1:0
|
||||
// 5-9 A 9:5
|
||||
// 22-40 A 31:22
|
||||
// B 8:0
|
||||
// 44-57 B 25:12
|
||||
// 67-68 C 4:3
|
||||
// 74-77 C 13:10
|
||||
// 79-83 C 19:15
|
||||
// 93-168 C 31:29
|
||||
// D 31:0
|
||||
// E 31:0
|
||||
// F 8:0
|
||||
//
|
||||
void GPIO_EnableUnbondedIOPullupsFor100Pin()
|
||||
{
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPAPUD.all = ~0xFFC003E3; //GPIOs 0-1, 5-9, 22-31
|
||||
GpioCtrlRegs.GPBPUD.all = ~0x03FFF1FF; //GPIOs 32-40, 44-57
|
||||
GpioCtrlRegs.GPCPUD.all = ~0xE10FBC18; //GPIOs 67-68, 74-77, 79-83, 93-95
|
||||
GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127
|
||||
GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFFF; //GPIOs 128-159
|
||||
GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_EnableUnbondedIOPullups - InitSysCtrl would call this function
|
||||
// this takes care of enabling IO pullups.
|
||||
//
|
||||
void GPIO_EnableUnbondedIOPullups()
|
||||
{
|
||||
//
|
||||
//bits 8-10 have pin count
|
||||
//
|
||||
unsigned char pin_count = ((DevCfgRegs.PARTIDL.all & 0x00000700) >> 8) ;
|
||||
|
||||
//
|
||||
//5 = 100 pin
|
||||
//6 = 176 pin
|
||||
//7 = 337 pin
|
||||
//
|
||||
if(pin_count == 5)
|
||||
{
|
||||
GPIO_EnableUnbondedIOPullupsFor100Pin();
|
||||
}
|
||||
else if (pin_count == 6)
|
||||
{
|
||||
GPIO_EnableUnbondedIOPullupsFor176Pin();
|
||||
}
|
||||
else
|
||||
{
|
||||
//do nothing - this is 337 pin package
|
||||
}
|
||||
}
|
||||
|
||||
#endif //CPU1
|
||||
|
||||
//
|
||||
// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. Note that
|
||||
// this returns the actual state of the pin, not the state of
|
||||
// the output latch.
|
||||
//
|
||||
Uint16 GPIO_ReadPin(Uint16 gpioNumber)
|
||||
{
|
||||
volatile Uint32 *gpioDataReg;
|
||||
Uint16 pinVal;
|
||||
|
||||
gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET;
|
||||
pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1;
|
||||
|
||||
return pinVal;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_WritePin - Set the GPyDAT register bit for the specified pin.
|
||||
//
|
||||
void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal)
|
||||
{
|
||||
volatile Uint32 *gpioDataReg;
|
||||
Uint32 pinMask;
|
||||
|
||||
gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET;
|
||||
pinMask = 1UL << (gpioNumber % 32);
|
||||
|
||||
if (outVal == 0)
|
||||
{
|
||||
gpioDataReg[GPYCLEAR] = pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
gpioDataReg[GPYSET] = pinMask;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
|
@ -0,0 +1,121 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_PieCtrl.c
|
||||
//
|
||||
// TITLE: F2837xD Device PIE Control Register Initialization Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h" // F2837xD Headerfile Include File
|
||||
#include "F2837xD_Examples.h" // F2837xD Examples Include File
|
||||
|
||||
//
|
||||
// InitPieCtrl - This function initializes the PIE control registers to a
|
||||
// known state.
|
||||
//
|
||||
void InitPieCtrl(void)
|
||||
{
|
||||
//
|
||||
// Disable Interrupts at the CPU level:
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Disable the PIE
|
||||
//
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
|
||||
|
||||
//
|
||||
// Clear all PIEIER registers:
|
||||
//
|
||||
PieCtrlRegs.PIEIER1.all = 0;
|
||||
PieCtrlRegs.PIEIER2.all = 0;
|
||||
PieCtrlRegs.PIEIER3.all = 0;
|
||||
PieCtrlRegs.PIEIER4.all = 0;
|
||||
PieCtrlRegs.PIEIER5.all = 0;
|
||||
PieCtrlRegs.PIEIER6.all = 0;
|
||||
PieCtrlRegs.PIEIER7.all = 0;
|
||||
PieCtrlRegs.PIEIER8.all = 0;
|
||||
PieCtrlRegs.PIEIER9.all = 0;
|
||||
PieCtrlRegs.PIEIER10.all = 0;
|
||||
PieCtrlRegs.PIEIER11.all = 0;
|
||||
PieCtrlRegs.PIEIER12.all = 0;
|
||||
|
||||
//
|
||||
// Clear all PIEIFR registers:
|
||||
//
|
||||
PieCtrlRegs.PIEIFR1.all = 0;
|
||||
PieCtrlRegs.PIEIFR2.all = 0;
|
||||
PieCtrlRegs.PIEIFR3.all = 0;
|
||||
PieCtrlRegs.PIEIFR4.all = 0;
|
||||
PieCtrlRegs.PIEIFR5.all = 0;
|
||||
PieCtrlRegs.PIEIFR6.all = 0;
|
||||
PieCtrlRegs.PIEIFR7.all = 0;
|
||||
PieCtrlRegs.PIEIFR8.all = 0;
|
||||
PieCtrlRegs.PIEIFR9.all = 0;
|
||||
PieCtrlRegs.PIEIFR10.all = 0;
|
||||
PieCtrlRegs.PIEIFR11.all = 0;
|
||||
PieCtrlRegs.PIEIFR12.all = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// EnableInterrupts - This function enables the PIE module and CPU __interrupts
|
||||
//
|
||||
void EnableInterrupts()
|
||||
{
|
||||
//
|
||||
// Enable the PIE
|
||||
//
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
//
|
||||
// Enables PIE to drive a pulse into the CPU
|
||||
//
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF;
|
||||
|
||||
//
|
||||
// Enable Interrupts at the CPU level
|
||||
//
|
||||
EINT;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
|
@ -0,0 +1,320 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_PieVect.c
|
||||
//
|
||||
// TITLE: F2837xD Device PIE Vector Initialization Functions
|
||||
//
|
||||
//###########################################################################
|
||||
// $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
const struct PIE_VECT_TABLE PieVectTableInit = {
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
TIMER1_ISR, // CPU Timer 1 Interrupt
|
||||
TIMER2_ISR, // CPU Timer 2 Interrupt
|
||||
DATALOG_ISR, // Datalogging Interrupt
|
||||
RTOS_ISR, // RTOS Interrupt
|
||||
EMU_ISR, // Emulation Interrupt
|
||||
NMI_ISR, // Non-Maskable Interrupt
|
||||
ILLEGAL_ISR, // Illegal Operation Trap
|
||||
USER1_ISR, // User Defined Trap 1
|
||||
USER2_ISR, // User Defined Trap 2
|
||||
USER3_ISR, // User Defined Trap 3
|
||||
USER4_ISR, // User Defined Trap 4
|
||||
USER5_ISR, // User Defined Trap 5
|
||||
USER6_ISR, // User Defined Trap 6
|
||||
USER7_ISR, // User Defined Trap 7
|
||||
USER8_ISR, // User Defined Trap 8
|
||||
USER9_ISR, // User Defined Trap 9
|
||||
USER10_ISR, // User Defined Trap 10
|
||||
USER11_ISR, // User Defined Trap 11
|
||||
USER12_ISR, // User Defined Trap 12
|
||||
ADCA1_ISR, // 1.1 - ADCA Interrupt 1
|
||||
ADCB1_ISR, // 1.2 - ADCB Interrupt 1
|
||||
ADCC1_ISR, // 1.3 - ADCC Interrupt 1
|
||||
XINT1_ISR, // 1.4 - XINT1 Interrupt
|
||||
XINT2_ISR, // 1.5 - XINT2 Interrupt
|
||||
ADCD1_ISR, // 1.6 - ADCD Interrupt 1
|
||||
TIMER0_ISR, // 1.7 - Timer 0 Interrupt
|
||||
WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt
|
||||
EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt
|
||||
EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt
|
||||
EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt
|
||||
EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt
|
||||
EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt
|
||||
EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt
|
||||
EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt
|
||||
EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt
|
||||
EPWM1_ISR, // 3.1 - ePWM1 Interrupt
|
||||
EPWM2_ISR, // 3.2 - ePWM2 Interrupt
|
||||
EPWM3_ISR, // 3.3 - ePWM3 Interrupt
|
||||
EPWM4_ISR, // 3.4 - ePWM4 Interrupt
|
||||
EPWM5_ISR, // 3.5 - ePWM5 Interrupt
|
||||
EPWM6_ISR, // 3.6 - ePWM6 Interrupt
|
||||
EPWM7_ISR, // 3.7 - ePWM7 Interrupt
|
||||
EPWM8_ISR, // 3.8 - ePWM8 Interrupt
|
||||
ECAP1_ISR, // 4.1 - eCAP1 Interrupt
|
||||
ECAP2_ISR, // 4.2 - eCAP2 Interrupt
|
||||
ECAP3_ISR, // 4.3 - eCAP3 Interrupt
|
||||
ECAP4_ISR, // 4.4 - eCAP4 Interrupt
|
||||
ECAP5_ISR, // 4.5 - eCAP5 Interrupt
|
||||
ECAP6_ISR, // 4.6 - eCAP6 Interrupt
|
||||
PIE_RESERVED_ISR, // 4.7 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.8 - Reserved
|
||||
EQEP1_ISR, // 5.1 - eQEP1 Interrupt
|
||||
EQEP2_ISR, // 5.2 - eQEP2 Interrupt
|
||||
EQEP3_ISR, // 5.3 - eQEP3 Interrupt
|
||||
PIE_RESERVED_ISR, // 5.4 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.5 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.6 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.7 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.8 - Reserved
|
||||
SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt
|
||||
SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt
|
||||
SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt
|
||||
SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt
|
||||
MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt
|
||||
MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt
|
||||
MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt
|
||||
MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt
|
||||
DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt
|
||||
DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt
|
||||
DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt
|
||||
DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt
|
||||
DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt
|
||||
DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt
|
||||
PIE_RESERVED_ISR, // 7.7 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.8 - Reserved
|
||||
I2CA_ISR, // 8.1 - I2CA Interrupt 1
|
||||
I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2
|
||||
I2CB_ISR, // 8.3 - I2CB Interrupt 1
|
||||
I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2
|
||||
SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt
|
||||
SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt
|
||||
SCID_RX_ISR, // 8.7 - SCID Receive Interrupt
|
||||
SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt
|
||||
SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt
|
||||
SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt
|
||||
SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt
|
||||
SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt
|
||||
CANA0_ISR, // 9.5 - CANA Interrupt 0
|
||||
CANA1_ISR, // 9.6 - CANA Interrupt 1
|
||||
CANB0_ISR, // 9.7 - CANB Interrupt 0
|
||||
CANB1_ISR, // 9.8 - CANB Interrupt 1
|
||||
ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt
|
||||
ADCA2_ISR, // 10.2 - ADCA Interrupt 2
|
||||
ADCA3_ISR, // 10.3 - ADCA Interrupt 3
|
||||
ADCA4_ISR, // 10.4 - ADCA Interrupt 4
|
||||
ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt
|
||||
ADCB2_ISR, // 10.6 - ADCB Interrupt 2
|
||||
ADCB3_ISR, // 10.7 - ADCB Interrupt 3
|
||||
ADCB4_ISR, // 10.8 - ADCB Interrupt 4
|
||||
CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1
|
||||
CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2
|
||||
CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3
|
||||
CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4
|
||||
CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5
|
||||
CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6
|
||||
CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7
|
||||
CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8
|
||||
XINT3_ISR, // 12.1 - XINT3 Interrupt
|
||||
XINT4_ISR, // 12.2 - XINT4 Interrupt
|
||||
XINT5_ISR, // 12.3 - XINT5 Interrupt
|
||||
PIE_RESERVED_ISR, // 12.4 - Reserved
|
||||
PIE_RESERVED_ISR, // 12.5 - Reserved
|
||||
VCU_ISR, // 12.6 - VCU Interrupt
|
||||
FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt
|
||||
FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt
|
||||
PIE_RESERVED_ISR, // 1.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 1.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 1.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 1.12 - Reserved
|
||||
IPC0_ISR, // 1.13 - IPC Interrupt 0
|
||||
IPC1_ISR, // 1.14 - IPC Interrupt 1
|
||||
IPC2_ISR, // 1.15 - IPC Interrupt 2
|
||||
IPC3_ISR, // 1.16 - IPC Interrupt 3
|
||||
EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt
|
||||
EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt
|
||||
EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt
|
||||
EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt
|
||||
PIE_RESERVED_ISR, // 2.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 2.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 2.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 2.16 - Reserved
|
||||
EPWM9_ISR, // 3.9 - ePWM9 Interrupt
|
||||
EPWM10_ISR, // 3.10 - ePWM10 Interrupt
|
||||
EPWM11_ISR, // 3.11 - ePWM11 Interrupt
|
||||
EPWM12_ISR, // 3.12 - ePWM12 Interrupt
|
||||
PIE_RESERVED_ISR, // 3.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 3.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 3.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 3.16 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.16 - Reserved
|
||||
SD1_ISR, // 5.9 - SD1 Interrupt
|
||||
SD2_ISR, // 5.10 - SD2 Interrupt
|
||||
PIE_RESERVED_ISR, // 5.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.16 - Reserved
|
||||
SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt
|
||||
SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt
|
||||
PIE_RESERVED_ISR, // 6.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.16 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.16 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.14 - Reserved
|
||||
#ifdef CPU1
|
||||
UPPA_ISR, // 8.15 - uPPA Interrupt
|
||||
PIE_RESERVED_ISR, // 8.16 - Reserved
|
||||
#elif defined(CPU2)
|
||||
PIE_RESERVED_ISR, // 8.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.16 - Reserved
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 9.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.14 - Reserved
|
||||
#ifdef CPU1
|
||||
USBA_ISR, // 9.15 - USBA Interrupt
|
||||
#elif defined(CPU2)
|
||||
PIE_RESERVED_ISR, // 9.15 - Reserved
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 9.16 - Reserved
|
||||
ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt
|
||||
ADCC2_ISR, // 10.10 - ADCC Interrupt 2
|
||||
ADCC3_ISR, // 10.11 - ADCC Interrupt 3
|
||||
ADCC4_ISR, // 10.12 - ADCC Interrupt 4
|
||||
ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt
|
||||
ADCD2_ISR, // 10.14 - ADCD Interrupt 2
|
||||
ADCD3_ISR, // 10.15 - ADCD Interrupt 3
|
||||
ADCD4_ISR, // 10.16 - ADCD Interrupt 4
|
||||
PIE_RESERVED_ISR, // 11.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.16 - Reserved
|
||||
EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt
|
||||
RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt
|
||||
FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt
|
||||
RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt
|
||||
SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt
|
||||
AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt
|
||||
CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt
|
||||
CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt
|
||||
};
|
||||
|
||||
//
|
||||
// InitPieVectTable - This function initializes the PIE vector table to a
|
||||
// known state and must be executed after boot time.
|
||||
//
|
||||
void InitPieVectTable(void)
|
||||
{
|
||||
Uint16 i;
|
||||
Uint32 *Source = (void *) &PieVectTableInit;
|
||||
Uint32 *Dest = (void *) &PieVectTable;
|
||||
|
||||
//
|
||||
// Do not write over first 3 32-bit locations (these locations are
|
||||
// initialized by Boot ROM with boot variables)
|
||||
//
|
||||
Source = Source + 3;
|
||||
Dest = Dest + 3;
|
||||
|
||||
EALLOW;
|
||||
for(i = 0; i < 221; i++)
|
||||
{
|
||||
*Dest++ = *Source++;
|
||||
}
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Enable the PIE Vector Table
|
||||
//
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,109 @@
|
|||
;//###########################################################################
|
||||
;//
|
||||
;// FILE: F2837xD_usDelay.asm
|
||||
;//
|
||||
;// TITLE: Simple delay function
|
||||
;//
|
||||
;// DESCRIPTION:
|
||||
;// This is a simple delay function that can be used to insert a specified
|
||||
;// delay into code.
|
||||
;// This function is only accurate if executed from internal zero-waitstate
|
||||
;// SARAM. If it is executed from waitstate memory then the delay will be
|
||||
;// longer then specified.
|
||||
;// To use this function:
|
||||
;// 1 - update the CPU clock speed in the F2837xD_Examples.h
|
||||
;// file. For example:
|
||||
;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed
|
||||
;// 2 - Call this function by using the DELAY_US(A) macro
|
||||
;// that is defined in the F2837xD_Device.h file. This macro
|
||||
;// will convert the number of microseconds specified
|
||||
;// into a loop count for use with this function.
|
||||
;// This count will be based on the CPU frequency you specify.
|
||||
;// 3 - For the most accurate delay
|
||||
;// - Execute this function in 0 waitstate RAM.
|
||||
;// - Disable interrupts before calling the function
|
||||
;// If you do not disable interrupts, then think of
|
||||
;// this as an "at least" delay function as the actual
|
||||
;// delay may be longer.
|
||||
;// The C assembly call from the DELAY_US(time) macro will
|
||||
;// look as follows:
|
||||
;// extern void Delay(long LoopCount);
|
||||
;// MOV AL,#LowLoopCount
|
||||
;// MOV AH,#HighLoopCount
|
||||
;// LCR _Delay
|
||||
;// Or as follows (if count is less then 16-bits):
|
||||
;// MOV ACC,#LoopCount
|
||||
;// LCR _Delay
|
||||
;//
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// $Release Date: $
|
||||
;// $Copyright:
|
||||
;// Copyright (C) 2013-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
;//
|
||||
;// Redistribution and use in source and binary forms, with or without
|
||||
;// modification, are permitted provided that the following conditions
|
||||
;// are met:
|
||||
;//
|
||||
;// Redistributions of source code must retain the above copyright
|
||||
;// notice, this list of conditions and the following disclaimer.
|
||||
;//
|
||||
;// Redistributions in binary form must reproduce the above copyright
|
||||
;// notice, this list of conditions and the following disclaimer in the
|
||||
;// documentation and/or other materials provided with the
|
||||
;// distribution.
|
||||
;//
|
||||
;// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
;// its contributors may be used to endorse or promote products derived
|
||||
;// from this software without specific prior written permission.
|
||||
;//
|
||||
;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;// $
|
||||
;//###########################################################################
|
||||
|
||||
.if __TI_EABI__
|
||||
.asg F28x_usDelay, _F28x_usDelay
|
||||
.endif
|
||||
|
||||
.def _F28x_usDelay
|
||||
|
||||
.cdecls LIST ;;Used to populate __TI_COMPILER_VERSION__ macro
|
||||
%{
|
||||
%}
|
||||
|
||||
.if __TI_COMPILER_VERSION__
|
||||
.if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.sect ".TI.ramfunc" ;;Used with compiler v15.9.0 and newer
|
||||
.else
|
||||
.sect "ramfuncs" ;;Used with compilers older than v15.9.0
|
||||
.endif
|
||||
.endif
|
||||
|
||||
.global __F28x_usDelay
|
||||
_F28x_usDelay:
|
||||
SUB ACC,#1
|
||||
BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0
|
||||
LRETR
|
||||
|
||||
;There is a 9/10 cycle overhead and each loop
|
||||
;takes five cycles. The LoopCount is given by
|
||||
;the following formula:
|
||||
; DELAY_CPU_CYCLES = 9 + 5*LoopCount
|
||||
; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
|
||||
; The macro DELAY_US(A) performs this calculation for you
|
||||
;
|
||||
;
|
||||
|
||||
;//
|
||||
;// End of file
|
||||
;//
|
|
@ -0,0 +1,706 @@
|
|||
//#############################################################################
|
||||
//
|
||||
// FILE: device.c
|
||||
//
|
||||
// TITLE: Device setup for examples.
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "device.h"
|
||||
#include "driverlib.h"
|
||||
#include "inc/hw_ipc.h"
|
||||
|
||||
#ifdef CMDTOOL
|
||||
#include "device_cmd.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
using std::memcpy;
|
||||
#endif
|
||||
|
||||
#define PASS 0
|
||||
#define FAIL 1
|
||||
|
||||
uint32_t Example_Result = FAIL;
|
||||
uint32_t Example_PassCount = 0;
|
||||
uint32_t Example_Fail = 0;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to initialize the device. Primarily initializes system control to a
|
||||
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
|
||||
// and enabling the clocks to the peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_init(void)
|
||||
{
|
||||
//
|
||||
// Disable the watchdog
|
||||
//
|
||||
SysCtl_disableWatchdog();
|
||||
|
||||
#ifdef CMDTOOL
|
||||
CMD_init();
|
||||
#endif
|
||||
|
||||
#ifdef _FLASH
|
||||
#ifndef CMDTOOL
|
||||
//
|
||||
// Copy time critical code and flash setup code to RAM. This includes the
|
||||
// following functions: InitFlash();
|
||||
//
|
||||
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
|
||||
// are created by the linker. Refer to the device .cmd file.
|
||||
//
|
||||
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
|
||||
#endif
|
||||
|
||||
//
|
||||
// Call Flash Initialization to setup flash waitstates. This function must
|
||||
// reside in RAM.
|
||||
//
|
||||
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
|
||||
#endif
|
||||
#ifdef CPU1
|
||||
|
||||
//
|
||||
// Configure Analog Trim in case of untrimmed or TMX sample
|
||||
//
|
||||
if((SysCtl_getDeviceParametric(SYSCTL_DEVICE_QUAL) == 0x0U) &&
|
||||
(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) == 0x0U))
|
||||
{
|
||||
Device_configureTMXAnalogTrim();
|
||||
}
|
||||
|
||||
//
|
||||
// Set up PLL control and clock dividers
|
||||
//
|
||||
SysCtl_setClock(DEVICE_SETCLOCK_CFG);
|
||||
|
||||
//
|
||||
// Make sure the LSPCLK divider is set to the default (divide by 4)
|
||||
//
|
||||
SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4);
|
||||
|
||||
//
|
||||
// These asserts will check that the #defines for the clock rates in
|
||||
// device.h match the actual rates that have been configured. If they do
|
||||
// not match, check that the calculations of DEVICE_SYSCLK_FREQ and
|
||||
// DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
|
||||
// expected if these are not correct.
|
||||
//
|
||||
ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
|
||||
ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
|
||||
|
||||
#ifndef _FLASH
|
||||
//
|
||||
// Call Device_cal function when run using debugger
|
||||
// This function is called as part of the Boot code. The function is called
|
||||
// in the Device_init function since during debug time resets, the boot code
|
||||
// will not be executed and the gel script will reinitialize all the
|
||||
// registers and the calibrated values will be lost.
|
||||
// Sysctl_deviceCal is a wrapper function for Device_Cal
|
||||
//
|
||||
SysCtl_deviceCal();
|
||||
#endif
|
||||
|
||||
#endif
|
||||
//
|
||||
// Turn on all peripherals
|
||||
//
|
||||
Device_enableAllPeripherals();
|
||||
|
||||
//
|
||||
// Initialize result parameter as FAIL
|
||||
//
|
||||
Example_Result = FAIL;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to turn on all peripherals, enabling reads and writes to the
|
||||
// peripherals' registers.
|
||||
//
|
||||
// Note that to reduce power, unused peripherals should be disabled.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_enableAllPeripherals(void)
|
||||
{
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2);
|
||||
#ifdef CPU1
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM);
|
||||
#endif
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
|
||||
|
||||
#ifdef CPU1
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2);
|
||||
#endif
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB);
|
||||
|
||||
#ifdef CPU1
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA);
|
||||
#endif
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to disable pin locks on GPIOs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_initGPIO(void)
|
||||
{
|
||||
//
|
||||
// Disable pin locks.
|
||||
//
|
||||
GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
|
||||
GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
|
||||
GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF);
|
||||
GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF);
|
||||
GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF);
|
||||
GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF);
|
||||
|
||||
//
|
||||
// Enable GPIO Pullups
|
||||
//
|
||||
Device_enableUnbondedGPIOPullups();
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to enable pullups for the unbonded GPIOs on the 176PTP package:
|
||||
// GPIOs Grp Bits
|
||||
// 95-132 C 31
|
||||
// D 31:0
|
||||
// E 4:0
|
||||
// 134-168 E 31:6
|
||||
// F 8:0
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
void Device_enableUnbondedGPIOPullupsFor176Pin(void)
|
||||
{
|
||||
EALLOW;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to enable pullups for the unbonded GPIOs on the 100PZ package:
|
||||
// GPIOs Grp Bits
|
||||
// 0-1 A 1:0
|
||||
// 5-9 A 9:5
|
||||
// 22-40 A 31:22
|
||||
// B 8:0
|
||||
// 44-57 B 25:12
|
||||
// 67-68 C 4:3
|
||||
// 74-77 C 13:10
|
||||
// 79-83 C 19:15
|
||||
// 93-168 C 31:29
|
||||
// D 31:0
|
||||
// E 31:0
|
||||
// F 8:0
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_enableUnbondedGPIOPullupsFor100Pin(void)
|
||||
{
|
||||
EALLOW;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to enable pullups for the unbonded GPIOs on the 100PZ or
|
||||
// 176PTP package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_enableUnbondedGPIOPullups(void)
|
||||
{
|
||||
//
|
||||
// bits 8-10 have pin count
|
||||
//
|
||||
uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
|
||||
(uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >>
|
||||
SYSCTL_PARTIDL_PIN_COUNT_S);
|
||||
|
||||
/*
|
||||
* 5 = 100 pin
|
||||
* 6 = 176 pin
|
||||
* 7 = 337 pin
|
||||
*/
|
||||
if(pinCount == 5)
|
||||
{
|
||||
Device_enableUnbondedGPIOPullupsFor100Pin();
|
||||
}
|
||||
else if(pinCount == 6)
|
||||
{
|
||||
Device_enableUnbondedGPIOPullupsFor176Pin();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Do nothing - this is 337 pin package
|
||||
//
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CPU1
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to implement Analog trim of TMX devices
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_configureTMXAnalogTrim(void)
|
||||
{
|
||||
//
|
||||
// Enable ADC clock
|
||||
//
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
|
||||
|
||||
//
|
||||
// Configure ADC reference trim for TMX devices
|
||||
//
|
||||
EALLOW;
|
||||
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) = 0x7BDDU;
|
||||
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMB) = 0x7BDDU;
|
||||
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMC) = 0x7BDDU;
|
||||
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMD) = 0x7BDDU;
|
||||
|
||||
//
|
||||
// Configure ADC offset trim. The user should generate the trim values
|
||||
// by following the instructions in the "ADC Zero Offset Calibration"
|
||||
// section in device TRM. The below lines needs to be uncommented and
|
||||
// updated with the correct trim values.
|
||||
//
|
||||
// HWREGH(ADCA_BASE + ADC_O_OFFTRIM) = 0x0U;
|
||||
// HWREGH(ADCB_BASE + ADC_O_OFFTRIM) = 0x0U;
|
||||
// HWREGH(ADCC_BASE + ADC_O_OFFTRIM) = 0x0U;
|
||||
// HWREGH(ADCD_BASE + ADC_O_OFFTRIM) = 0x0U;
|
||||
|
||||
//
|
||||
// Configure internal oscillator trim. If the internal oscillator trim
|
||||
// contains all zeros, the user can adjust the lowest 10 bits of the
|
||||
// oscillator trim register between 1 (minimum) and 1023 (maximum)
|
||||
// while observing the system clock on the XCLOCKOUT pin. The below
|
||||
// lines needs to be uncommented and updated with the correct trim values.
|
||||
//
|
||||
// if(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) == 0x0U)
|
||||
// {
|
||||
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) = 0x0U;
|
||||
// }
|
||||
// if( HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U)
|
||||
// {
|
||||
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U;
|
||||
// }
|
||||
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Disable ADC clock
|
||||
//
|
||||
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
|
||||
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
|
||||
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
|
||||
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//! Executes a CPU02 control system bootloader.
|
||||
//!
|
||||
//! \param bootMode specifies which CPU02 control system boot mode to execute.
|
||||
//!
|
||||
//! This function will allow the CPU01 master system to boot the CPU02 control
|
||||
//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI,
|
||||
//! SCI, I2C, or parallel I/O. This function blocks and waits until the
|
||||
//! control system boot ROM is configured and ready to receive CPU01 to CPU02
|
||||
//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and
|
||||
//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the
|
||||
//! command to execute the selected bootloader.
|
||||
//!
|
||||
//! The \e bootMode parameter accepts one of the following values:
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH
|
||||
//!
|
||||
//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is
|
||||
//! invalid and command was not sent.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint16_t
|
||||
Device_bootCPU2(uint32_t bootMode)
|
||||
{
|
||||
uint32_t bootStatus;
|
||||
uint16_t pin;
|
||||
uint16_t returnStatus = STATUS_PASS;
|
||||
|
||||
//
|
||||
// If CPU2 has already booted, return a fail to let the application
|
||||
// know that something is out of the ordinary.
|
||||
//
|
||||
bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & 0x0000000FU;
|
||||
|
||||
if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK)
|
||||
{
|
||||
//
|
||||
// Check if MSB is set as well
|
||||
//
|
||||
bootStatus = ((uint32_t)(HWREG(IPC_BASE + IPC_O_BOOTSTS) &
|
||||
0x80000000U)) >> 31U;
|
||||
|
||||
if(bootStatus != 0)
|
||||
{
|
||||
returnStatus = STATUS_FAIL;
|
||||
|
||||
return returnStatus;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Wait until CPU02 control system boot ROM is ready to receive
|
||||
// CPU01 to CPU02 INT1 interrupts.
|
||||
//
|
||||
do
|
||||
{
|
||||
bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) &
|
||||
C2_BOOTROM_BOOTSTS_SYSTEM_READY;
|
||||
} while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY));
|
||||
|
||||
//
|
||||
// Loop until CPU02 control system IPC flags 1 and 32 are available
|
||||
//
|
||||
while (((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC0) != 0U) ||
|
||||
((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC31) != 0U))
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
if (bootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE)
|
||||
{
|
||||
returnStatus = STATUS_FAIL;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Based on boot mode, enable pull-ups on peripheral pins and
|
||||
// give GPIO pin control to CPU02 control system.
|
||||
//
|
||||
switch (bootMode)
|
||||
{
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI:
|
||||
|
||||
//
|
||||
//SCIA connected to CPU02
|
||||
//
|
||||
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL5_SCI, 1,
|
||||
SYSCTL_CPUSEL_CPU2);
|
||||
|
||||
//
|
||||
//Allows CPU02 bootrom to take control of clock
|
||||
//configuration registers
|
||||
//
|
||||
EALLOW;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U;
|
||||
EDIS;
|
||||
|
||||
GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT);
|
||||
GPIO_setQualificationMode(29, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_29_SCITXDA);
|
||||
GPIO_setMasterCore(29, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(28, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(28, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_28_SCIRXDA);
|
||||
GPIO_setMasterCore(28, GPIO_CORE_CPU2);
|
||||
|
||||
break;
|
||||
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI:
|
||||
|
||||
//
|
||||
//SPI-A connected to CPU02
|
||||
//
|
||||
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL6_SPI, 1,
|
||||
SYSCTL_CPUSEL_CPU2);
|
||||
|
||||
//
|
||||
//Allows CPU02 bootrom to take control of clock configuration
|
||||
// registers
|
||||
//
|
||||
EALLOW;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
|
||||
EDIS;
|
||||
|
||||
GPIO_setDirectionMode(16, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(16, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_16_SPISIMOA);
|
||||
GPIO_setMasterCore(16, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(17, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(17, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_17_SPISOMIA);
|
||||
GPIO_setMasterCore(17, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(18, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(18, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_18_SPICLKA);
|
||||
GPIO_setMasterCore(18, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(19, GPIO_DIR_MODE_OUT);
|
||||
GPIO_setQualificationMode(19, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_19_GPIO19);
|
||||
GPIO_setMasterCore(19, GPIO_CORE_CPU2);
|
||||
|
||||
break;
|
||||
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C:
|
||||
|
||||
//
|
||||
//I2CA connected to CPU02
|
||||
//
|
||||
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL7_I2C, 1,
|
||||
SYSCTL_CPUSEL_CPU2);
|
||||
|
||||
//
|
||||
//Allows CPU2 bootrom to take control of clock
|
||||
//configuration registers
|
||||
//
|
||||
EALLOW;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U;
|
||||
EDIS;
|
||||
|
||||
GPIO_setDirectionMode(32, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(32, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_32_SDAA);
|
||||
GPIO_setMasterCore(32, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(33, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(33, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_33_SCLA);
|
||||
GPIO_setMasterCore(33, GPIO_CORE_CPU2);
|
||||
|
||||
break;
|
||||
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL:
|
||||
|
||||
for(pin=58;pin<=65;pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
GPIO_setMasterCore(pin, GPIO_CORE_CPU2);
|
||||
}
|
||||
|
||||
GPIO_setDirectionMode(69, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(69, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_69_GPIO69);
|
||||
GPIO_setMasterCore(69, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(70, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_70_GPIO70);
|
||||
GPIO_setMasterCore(70, GPIO_CORE_CPU2);
|
||||
|
||||
break;
|
||||
|
||||
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN:
|
||||
//
|
||||
//Set up the GPIO mux to bring out CANATX on GPIO71
|
||||
//and CANARX on GPIO70
|
||||
//
|
||||
GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU);
|
||||
|
||||
GPIO_setMasterCore(71, GPIO_CORE_CPU2);
|
||||
GPIO_setPinConfig(GPIO_71_CANTXA);
|
||||
GPIO_setQualificationMode(71, GPIO_QUAL_ASYNC);
|
||||
|
||||
GPIO_setMasterCore(70, GPIO_CORE_CPU2);
|
||||
GPIO_setPinConfig(GPIO_70_CANRXA);
|
||||
GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC);
|
||||
|
||||
|
||||
GPIO_lockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU);
|
||||
|
||||
//
|
||||
// Set CANA Bit-Clock Source Select = SYSCLK and enable CAN
|
||||
//
|
||||
EALLOW;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &=
|
||||
SYSCTL_CLKSRCCTL2_CANABCLKSEL_M;
|
||||
EDIS;
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA);
|
||||
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
//CPU01 to CPU02 IPC Boot Mode Register
|
||||
//
|
||||
HWREG(IPC_BASE + IPC_O_BOOTMODE) = bootMode;
|
||||
|
||||
//
|
||||
// CPU01 To CPU02 IPC Command Register
|
||||
//
|
||||
HWREG(IPC_BASE + IPC_O_SENDCOM) = BROM_IPC_EXECUTE_BOOTMODE_CMD;
|
||||
|
||||
//
|
||||
// CPU01 to CPU02 IPC flag register
|
||||
//
|
||||
HWREG(IPC_BASE + IPC_O_SET) = 0x80000001U;
|
||||
|
||||
}
|
||||
return returnStatus;
|
||||
}
|
||||
#endif // #ifdef CPU1
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Error handling function to be called when an ASSERT is violated
|
||||
//
|
||||
//*****************************************************************************
|
||||
void __error__(const char *filename, uint32_t line)
|
||||
{
|
||||
//
|
||||
// An ASSERT condition was evaluated as false. You can use the filename and
|
||||
// line parameters to determine what went wrong.
|
||||
//
|
||||
ESTOP0;
|
||||
}
|
||||
|
||||
void Example_setResultPass(void)
|
||||
{
|
||||
Example_Result = PASS;
|
||||
}
|
||||
|
||||
void Example_setResultFail(void)
|
||||
{
|
||||
Example_Result = FAIL;
|
||||
}
|
||||
|
||||
void Example_done(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
|
@ -0,0 +1,394 @@
|
|||
//#############################################################################
|
||||
//
|
||||
// FILE: device.h
|
||||
//
|
||||
// TITLE: Device setup for examples.
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
|
||||
#if (!defined(CPU1) && !defined(CPU2))
|
||||
#error "You must define CPU1 or CPU2 in your project properties. Otherwise, \
|
||||
the offsets in your header files will be inaccurate."
|
||||
#endif
|
||||
|
||||
#if (defined(CPU1) && defined(CPU2))
|
||||
#error "You have defined both CPU1 and CPU2 in your project properties. Only \
|
||||
a single CPU should be defined."
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for pin numbers and other GPIO configuration
|
||||
//
|
||||
//*****************************************************************************
|
||||
//
|
||||
// LEDs
|
||||
//
|
||||
#ifdef _LAUNCHXL_F28379D
|
||||
#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD10
|
||||
#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD9
|
||||
#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD10
|
||||
#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD9
|
||||
#else
|
||||
#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2
|
||||
#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3
|
||||
#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2
|
||||
#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// SCI for USB-to-UART adapter on FTDI chip
|
||||
//
|
||||
#ifdef _LAUNCHXL_F28379D
|
||||
#define DEVICE_GPIO_PIN_SCIRXDA 43U // GPIO number for SCI RX
|
||||
#define DEVICE_GPIO_PIN_SCITXDA 42U // GPIO number for SCI TX
|
||||
#define DEVICE_GPIO_CFG_SCIRXDA GPIO_43_SCIRXDA // "pinConfig" for SCI RX
|
||||
#define DEVICE_GPIO_CFG_SCITXDA GPIO_42_SCITXDA // "pinConfig" for SCI TX
|
||||
#else
|
||||
#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX
|
||||
#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX
|
||||
#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX
|
||||
#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX
|
||||
#endif
|
||||
|
||||
//
|
||||
// GPIO assignment for CAN-A and CAN-B
|
||||
//
|
||||
#ifdef _LAUNCHXL_F28379D
|
||||
#define DEVICE_GPIO_CFG_CANRXA GPIO_36_CANRXA // "pinConfig" for CANA RX
|
||||
#define DEVICE_GPIO_CFG_CANTXA GPIO_37_CANTXA // "pinConfig" for CANA TX
|
||||
#define DEVICE_GPIO_CFG_CANRXB GPIO_17_CANRXB // "pinConfig" for CANB RX
|
||||
#define DEVICE_GPIO_CFG_CANTXB GPIO_12_CANTXB // "pinConfig" for CANB TX
|
||||
#else
|
||||
#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX
|
||||
#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX
|
||||
#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX
|
||||
#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX
|
||||
|
||||
//I2CA GPIO pins
|
||||
#define DEVICE_GPIO_PIN_SDAA 104
|
||||
#define DEVICE_GPIO_PIN_SCLA 105
|
||||
|
||||
#define DEVICE_GPIO_CFG_SDAA GPIO_104_SDAA
|
||||
#define DEVICE_GPIO_CFG_SCLA GPIO_105_SCLA
|
||||
|
||||
|
||||
//I2CB GPIO pins
|
||||
#define DEVICE_GPIO_PIN_SDAB 40
|
||||
#define DEVICE_GPIO_PIN_SCLB 41
|
||||
|
||||
#define DEVICE_GPIO_CFG_SDAB GPIO_40_SDAB
|
||||
#define DEVICE_GPIO_CFG_SCLB GPIO_41_SCLB
|
||||
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines related to clock configuration
|
||||
//
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Launchpad Configuration
|
||||
//
|
||||
#ifdef _LAUNCHXL_F28379D
|
||||
|
||||
//
|
||||
// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock().
|
||||
//
|
||||
#define DEVICE_OSCSRC_FREQ 10000000U
|
||||
|
||||
//
|
||||
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
|
||||
// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
|
||||
//
|
||||
#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \
|
||||
SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
|
||||
SYSCTL_PLL_ENABLE)
|
||||
|
||||
//
|
||||
// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
|
||||
// code below if a different clock configuration is used!
|
||||
//
|
||||
#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2)
|
||||
|
||||
//
|
||||
// ControlCARD Configuration
|
||||
//
|
||||
#else
|
||||
|
||||
//
|
||||
// 20MHz XTAL on controlCARD. For use with SysCtl_getClock().
|
||||
//
|
||||
#define DEVICE_OSCSRC_FREQ 20000000U
|
||||
|
||||
//
|
||||
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
|
||||
// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
|
||||
//
|
||||
#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) | \
|
||||
SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
|
||||
SYSCTL_PLL_ENABLE)
|
||||
|
||||
//
|
||||
// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
|
||||
// code below if a different clock configuration is used!
|
||||
//
|
||||
#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2)
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
|
||||
// low speed peripheral clock divider of 4. Update the code below if a
|
||||
// different LSPCLK divider is used!
|
||||
//
|
||||
#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro
|
||||
// will convert the desired delay in microseconds to the count value expected
|
||||
// by the function. \b x is the number of microseconds to delay.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \
|
||||
(long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L)
|
||||
|
||||
//
|
||||
// The macros that can be used as parameter to the function Device_bootCPU2
|
||||
//
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000AU
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000BU
|
||||
|
||||
//
|
||||
// Other macros that are needed for the Device_bootCPU2 function
|
||||
//
|
||||
#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000CU
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000U
|
||||
#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001U
|
||||
#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002U
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003U
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004U
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005U
|
||||
|
||||
//
|
||||
// Macros used as return value by the Device_bootCPU2 function
|
||||
//
|
||||
#define STATUS_FAIL 0x0001
|
||||
#define STATUS_PASS 0x0000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines, Globals, and Header Includes related to Flash Support
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef _FLASH
|
||||
#include <stddef.h>
|
||||
|
||||
extern uint16_t RamfuncsLoadStart;
|
||||
extern uint16_t RamfuncsLoadEnd;
|
||||
extern uint16_t RamfuncsLoadSize;
|
||||
extern uint16_t RamfuncsRunStart;
|
||||
extern uint16_t RamfuncsRunEnd;
|
||||
extern uint16_t RamfuncsRunSize;
|
||||
|
||||
#define DEVICE_FLASH_WAITSTATES 3
|
||||
|
||||
#endif
|
||||
|
||||
extern uint32_t Example_PassCount;
|
||||
extern uint32_t Example_Fail;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup device_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! @brief Function to initialize the device. Primarily initializes system control to a
|
||||
//! known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
|
||||
//! and enabling the clocks to the peripherals.
|
||||
//!
|
||||
//! \param None.
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_init(void);
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//!
|
||||
//! @brief Function to turn on all peripherals, enabling reads and writes to the
|
||||
//! peripherals' registers.
|
||||
//!
|
||||
//! Note that to reduce power, unused peripherals should be disabled.
|
||||
//!
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_enableAllPeripherals(void);
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//!
|
||||
//! @brief Function to disable pin locks on GPIOs.
|
||||
//!
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_initGPIO(void);
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//! @brief Function to enable pullups for the unbonded GPIOs on the 176PTP package:
|
||||
//! GPIOs Grp Bits
|
||||
//! 95-132 C 31
|
||||
//! D 31:0
|
||||
//! E 4:0
|
||||
//! 134-168 E 31:6
|
||||
//! F 8:0
|
||||
//!
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_enableUnbondedGPIOPullupsFor176Pin(void);
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//! @brief Function to enable pullups for the unbonded GPIOs on the 100PZ package:
|
||||
//! GPIOs Grp Bits
|
||||
//! 0-1 A 1:0
|
||||
//! 5-9 A 9:5
|
||||
//! 22-40 A 31:22
|
||||
//! B 8:0
|
||||
//! 44-57 B 25:12
|
||||
//! 67-68 C 4:3
|
||||
//! 74-77 C 13:10
|
||||
//! 79-83 C 19:15
|
||||
//! 93-168 C 31:29
|
||||
//! D 31:0
|
||||
//! E 31:0
|
||||
//! F 8:0
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_enableUnbondedGPIOPullupsFor100Pin(void);
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//! @brief Function to enable pullups for the unbonded GPIOs on the
|
||||
//! 176PTP package.
|
||||
//!
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_enableUnbondedGPIOPullups(void);
|
||||
#ifdef CPU1
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//! @brief Function to implement Analog trim of TMX devices
|
||||
//!
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_configureTMXAnalogTrim(void);
|
||||
//*****************************************************************************
|
||||
//! @brief Executes a CPU02 control system bootloader.
|
||||
//!
|
||||
//! \param bootMode specifies which CPU02 control system boot mode to execute.
|
||||
//!
|
||||
//! This function will allow the CPU01 master system to boot the CPU02 control
|
||||
//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI,
|
||||
//! SCI, I2C, or parallel I/O. This function blocks and waits until the
|
||||
//! control system boot ROM is configured and ready to receive CPU01 to CPU02
|
||||
//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and
|
||||
//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the
|
||||
//! command to execute the selected bootloader.
|
||||
//!
|
||||
//! The \e bootMode parameter accepts one of the following values:
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH
|
||||
//!
|
||||
//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is
|
||||
//! invalid and command was not sent.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern uint16_t Device_bootCPU2(uint32_t ulBootMode);
|
||||
#endif
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//! @brief Error handling function to be called when an ASSERT is violated
|
||||
//!
|
||||
//! @param *filename File name in which the error has occurred
|
||||
//! @param line Line number within the file
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void __error__(const char *filename, uint32_t line);
|
||||
extern void Example_setResultPass(void);
|
||||
extern void Example_setResultFail(void);
|
||||
extern void Example_done(void);
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
|
@ -0,0 +1,87 @@
|
|||
//#############################################################################
|
||||
//
|
||||
// FILE: driverlib.h
|
||||
//
|
||||
// TITLE: C28x Driverlib Header File
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
#ifndef DRIVERLIB_H
|
||||
#define DRIVERLIB_H
|
||||
|
||||
#include "inc/hw_memmap.h"
|
||||
|
||||
#include "adc.h"
|
||||
#include "asysctl.h"
|
||||
#include "can.h"
|
||||
#include "cla.h"
|
||||
#include "clb.h"
|
||||
#include "cmpss.h"
|
||||
#include "cpu.h"
|
||||
#include "cputimer.h"
|
||||
#include "dac.h"
|
||||
#include "dcsm.h"
|
||||
#include "debug.h"
|
||||
#include "dma.h"
|
||||
#include "ecap.h"
|
||||
#include "emif.h"
|
||||
#include "epwm.h"
|
||||
#include "eqep.h"
|
||||
#include "flash.h"
|
||||
#include "gpio.h"
|
||||
#include "hrpwm.h"
|
||||
#include "i2c.h"
|
||||
#include "interrupt.h"
|
||||
#include "ipc.h"
|
||||
#include "mcbsp.h"
|
||||
#include "memcfg.h"
|
||||
#include "pin_map.h"
|
||||
#include "pin_map_legacy.h"
|
||||
#include "sci.h"
|
||||
#include "sdfm.h"
|
||||
#include "spi.h"
|
||||
#include "sysctl.h"
|
||||
#include "upp.h"
|
||||
#include "version.h"
|
||||
#include "xbar.h"
|
||||
|
||||
#include "driver_inclusive_terminology_mapping.h"
|
||||
|
||||
#endif // end of DRIVERLIB_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
|
@ -0,0 +1,340 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: adc.c
|
||||
//
|
||||
// TITLE: C28x ADC driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "adc.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for locations of ADC calibration functions in OTP for use in
|
||||
// ADC_setMode() ONLY. Not intended for use by application code.
|
||||
//
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following functions calibrate the ADC linearity. Use them in the
|
||||
// ADC_setMode() function only.
|
||||
//
|
||||
#define ADC_calADCAINL 0x0703B4U
|
||||
#define ADC_calADCBINL 0x0703B2U
|
||||
#define ADC_calADCCINL 0x0703B0U
|
||||
#define ADC_calADCDINL 0x0703AEU
|
||||
|
||||
//
|
||||
// This function looks up the ADC offset trim for a given condition. Use this
|
||||
// in the ADC_setMode() function only.
|
||||
//
|
||||
#define ADC_getOffsetTrim 0x0703ACU
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// ADC_setMode
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ADC_setMode(uint32_t base, ADC_Resolution resolution,
|
||||
ADC_SignalMode signalMode)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ADC_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Check for correct signal mode & resolution. In this device:
|
||||
// Single ended signal conversions are supported in 12-bit mode only
|
||||
// Differential signal conversions are supported in 16-bit mode only
|
||||
//
|
||||
if(signalMode == ADC_MODE_SINGLE_ENDED)
|
||||
{
|
||||
ASSERT(resolution == ADC_RESOLUTION_12BIT);
|
||||
}
|
||||
else
|
||||
{
|
||||
ASSERT(resolution == ADC_RESOLUTION_16BIT);
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Apply the resolution and signalMode to the specified ADC.
|
||||
//
|
||||
EALLOW;
|
||||
HWREGH(base + ADC_O_CTL2) = (HWREGH(base + ADC_O_CTL2) &
|
||||
~(ADC_CTL2_RESOLUTION | ADC_CTL2_SIGNALMODE)) |
|
||||
((uint16_t)resolution | (uint16_t)signalMode);
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Apply INL and offset trims
|
||||
//
|
||||
ADC_setINLTrim(base);
|
||||
ADC_setOffsetTrim(base);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// ADC_setINLTrim
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ADC_setINLTrim(uint32_t base)
|
||||
{
|
||||
ADC_Resolution resolution;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ADC_isBaseValid(base));
|
||||
|
||||
resolution = (ADC_Resolution)
|
||||
(HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION);
|
||||
|
||||
EALLOW;
|
||||
switch(base)
|
||||
{
|
||||
case ADCA_BASE:
|
||||
if(HWREGH(ADC_calADCAINL) != 0xFFFFU)
|
||||
{
|
||||
//
|
||||
// Trim function is programmed into OTP, so call it
|
||||
//
|
||||
(*((void (*)(void))ADC_calADCAINL))();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Do nothing, no INL trim function populated
|
||||
//
|
||||
}
|
||||
break;
|
||||
case ADCB_BASE:
|
||||
if(HWREGH(ADC_calADCBINL) != 0xFFFFU)
|
||||
{
|
||||
//
|
||||
// Trim function is programmed into OTP, so call it
|
||||
//
|
||||
(*((void (*)(void))ADC_calADCBINL))();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Do nothing, no INL trim function populated
|
||||
//
|
||||
}
|
||||
break;
|
||||
case ADCC_BASE:
|
||||
if(HWREGH(ADC_calADCCINL) != 0xFFFFU)
|
||||
{
|
||||
//
|
||||
// Trim function is programmed into OTP, so call it
|
||||
//
|
||||
(*((void (*)(void))ADC_calADCCINL))();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Do nothing, no INL trim function populated
|
||||
//
|
||||
}
|
||||
break;
|
||||
case ADCD_BASE:
|
||||
if(HWREGH(ADC_calADCDINL) != 0xFFFFU)
|
||||
{
|
||||
//
|
||||
// Trim function is programmed into OTP, so call it
|
||||
//
|
||||
(*((void (*)(void))ADC_calADCDINL))();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Do nothing, no INL trim function populated
|
||||
//
|
||||
}
|
||||
break;
|
||||
default:
|
||||
//
|
||||
// Invalid base address! Do nothing!
|
||||
//
|
||||
break;
|
||||
}
|
||||
|
||||
//
|
||||
// Apply linearity trim workaround for 12-bit resolution
|
||||
//
|
||||
if(resolution == ADC_RESOLUTION_12BIT)
|
||||
{
|
||||
//
|
||||
// 12-bit linearity trim workaround
|
||||
//
|
||||
HWREG(base + ADC_O_INLTRIM1) &= 0xFFFF0000U;
|
||||
HWREG(base + ADC_O_INLTRIM2) &= 0xFFFF0000U;
|
||||
HWREG(base + ADC_O_INLTRIM4) &= 0xFFFF0000U;
|
||||
HWREG(base + ADC_O_INLTRIM5) &= 0xFFFF0000U;
|
||||
}
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// ADC_setOffsetTrim
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ADC_setOffsetTrim(uint32_t base)
|
||||
{
|
||||
uint16_t offsetIndex = 0U;
|
||||
uint16_t offsetTrim = 0U;
|
||||
ADC_Resolution resolution;
|
||||
ADC_SignalMode signalMode;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ADC_isBaseValid(base));
|
||||
|
||||
resolution = (ADC_Resolution)
|
||||
(HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION);
|
||||
signalMode = (ADC_SignalMode)
|
||||
(HWREGH(base + ADC_O_CTL2) & ADC_CTL2_SIGNALMODE);
|
||||
|
||||
switch(base)
|
||||
{
|
||||
case ADCA_BASE:
|
||||
offsetIndex = (uint16_t)(0U * 4U);
|
||||
break;
|
||||
case ADCB_BASE:
|
||||
offsetIndex = (uint16_t)(1U * 4U);
|
||||
break;
|
||||
case ADCC_BASE:
|
||||
offsetIndex = (uint16_t)(2U * 4U);
|
||||
break;
|
||||
case ADCD_BASE:
|
||||
offsetIndex = (uint16_t)(3U * 4U);
|
||||
break;
|
||||
default:
|
||||
//
|
||||
// Invalid base address!
|
||||
//
|
||||
offsetIndex = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
//
|
||||
// Offset trim function is programmed into OTP, so call it
|
||||
//
|
||||
if(HWREGH(ADC_getOffsetTrim) != 0xFFFFU)
|
||||
{
|
||||
//
|
||||
// Calculate the index into OTP table of offset trims and call
|
||||
// function to return the correct offset trim
|
||||
//
|
||||
offsetIndex += ((signalMode == ADC_MODE_DIFFERENTIAL) ? 1U : 0U) +
|
||||
(2U * ((resolution == ADC_RESOLUTION_16BIT) ? 1U : 0U));
|
||||
|
||||
offsetTrim =
|
||||
(*((uint16_t (*)(uint16_t index))ADC_getOffsetTrim))(offsetIndex);
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Offset trim function is not populated, so set offset trim to 0
|
||||
//
|
||||
offsetTrim = 0U;
|
||||
}
|
||||
|
||||
//
|
||||
// Apply the offset trim. Offset Trim is not updated here in case of TMX or
|
||||
// untrimmed devices. The default trims for TMX devices should be handled in
|
||||
// Device_init(). Refer to Device_init() and Device_configureTMXAnalogTrim()
|
||||
// APIs for more details.
|
||||
//
|
||||
if(offsetTrim > 0x0U)
|
||||
{
|
||||
EALLOW;
|
||||
HWREGH(base + ADC_O_OFFTRIM) = offsetTrim;
|
||||
EDIS;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// ADC_setPPBTripLimits
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber,
|
||||
int32_t tripHiLimit, int32_t tripLoLimit)
|
||||
{
|
||||
uint32_t ppbHiOffset;
|
||||
uint32_t ppbLoOffset;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ADC_isBaseValid(base));
|
||||
ASSERT((tripHiLimit <= 65535) && (tripHiLimit >= -65536));
|
||||
ASSERT((tripLoLimit <= 65535) && (tripLoLimit >= -65536));
|
||||
|
||||
//
|
||||
// Get the offset to the appropriate trip limit registers.
|
||||
//
|
||||
ppbHiOffset = (ADC_PPBxTRIPHI_STEP * (uint32_t)ppbNumber) +
|
||||
ADC_O_PPB1TRIPHI;
|
||||
ppbLoOffset = (ADC_PPBxTRIPLO_STEP * (uint32_t)ppbNumber) +
|
||||
ADC_O_PPB1TRIPLO;
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Set the trip high limit.
|
||||
//
|
||||
HWREG(base + ppbHiOffset) =
|
||||
(HWREG(base + ppbHiOffset) & ~ADC_PPBTRIP_MASK) |
|
||||
((uint32_t)tripHiLimit & ADC_PPBTRIP_MASK);
|
||||
|
||||
//
|
||||
// Set the trip low limit.
|
||||
//
|
||||
HWREG(base + ppbLoOffset) =
|
||||
(HWREG(base + ppbLoOffset) & ~ADC_PPBTRIP_MASK) |
|
||||
((uint32_t)tripLoLimit & ADC_PPBTRIP_MASK);
|
||||
|
||||
EDIS;
|
||||
}
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,42 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: asysctl.c
|
||||
//
|
||||
// TITLE: C28x Driver for Analog System Control.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "asysctl.h"
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: asysctl.h
|
||||
//
|
||||
// TITLE: C28x driver for Analog System Control.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef ASYSCTL_H
|
||||
#define ASYSCTL_H
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup asysctl_api ASysCtl
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "inc/hw_asysctl.h"
|
||||
#include "inc/hw_memmap.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "debug.h"
|
||||
#include "cpu.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enable temperature sensor.
|
||||
//!
|
||||
//! This function enables the temperature sensor output to the ADC.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
ASysCtl_enableTemperatureSensor(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Set the temperature sensor enable bit.
|
||||
//
|
||||
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) |= ASYSCTL_TSNSCTL_ENABLE;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disable temperature sensor.
|
||||
//!
|
||||
//! This function disables the temperature sensor output to the ADC.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
ASysCtl_disableTemperatureSensor(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Clear the temperature sensor enable bit.
|
||||
//
|
||||
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) &= ~(ASYSCTL_TSNSCTL_ENABLE);
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Locks the temperature sensor control register.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void ASysCtl_lockTemperatureSensor(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Write a 1 to the lock bit in the LOCK register.
|
||||
//
|
||||
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_LOCK) |= ASYSCTL_LOCK_TSNSCTL;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // ASYSCTL_H
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
@ -0,0 +1,46 @@
|
|||
<projectSpec>
|
||||
<project
|
||||
name="f2837xd_driverlib"
|
||||
device="Generic C28xx Device"
|
||||
cgtVersion="22.6.0.LTS"
|
||||
products="c2000ware_software_package"
|
||||
launchWizard="False"
|
||||
outputType="staticLibrary"
|
||||
location="."
|
||||
>
|
||||
<configuration name="Debug" compilerBuildOptions="--opt_level=off -I../ -v28 -ml -mt --float_support=fpu32 --define=DEBUG -g --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --gen_data_subsections=on --abi=coffabi" archiverBuildOptions="driverlib_coff.lib" outputFormat="COFF" postBuildStep="if exist driverlib_eabi.lib ${C2000_CG_ROOT}/bin/libinfo2000.exe -o driverlib.lib driverlib_eabi.lib driverlib_coff.lib"/>
|
||||
<configuration name="Debug_EABI" compilerBuildOptions="--opt_level=off -I../ -v28 -ml -mt --float_support=fpu32 --define=DEBUG -g --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --gen_data_subsections=on --abi=eabi" archiverBuildOptions="../Debug/driverlib_eabi.lib" outputFormat="ELF" postBuildStep="if exist ../Debug/driverlib_coff.lib ${C2000_CG_ROOT}/bin/libinfo2000.exe -o ../Debug/driverlib.lib ../Debug/driverlib_eabi.lib ../Debug/driverlib_coff.lib"/>
|
||||
<configuration name="Release" compilerBuildOptions="-O2 -I../ -v28 -ml -mt --float_support=fpu32 -g --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --gen_data_subsections=on --abi=coffabi" archiverBuildOptions="driverlib_coff.lib" outputFormat="COFF" postBuildStep="if exist driverlib_eabi.lib ${C2000_CG_ROOT}/bin/libinfo2000.exe -o driverlib.lib driverlib_eabi.lib driverlib_coff.lib" />
|
||||
<configuration name="Release_EABI" compilerBuildOptions="-O2 -I../ -v28 -ml -mt --float_support=fpu32 -g --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --gen_data_subsections=on --abi=eabi" archiverBuildOptions="../Release/driverlib_eabi.lib" outputFormat="ELF" postBuildStep="if exist ../Release/driverlib_coff.lib ${C2000_CG_ROOT}/bin/libinfo2000.exe -o ../Release/driverlib.lib ../Release/driverlib_eabi.lib ../Release/driverlib_coff.lib" />
|
||||
<file action="link" path="../adc.c" targetDirectory="." />
|
||||
<file action="link" path="../asysctl.c" targetDirectory="." />
|
||||
<file action="link" path="../can.c" targetDirectory="." />
|
||||
<file action="link" path="../cla.c" targetDirectory="." />
|
||||
<file action="link" path="../clb.c" targetDirectory="." />
|
||||
<file action="link" path="../cmpss.c" targetDirectory="." />
|
||||
<file action="link" path="../cputimer.c" targetDirectory="." />
|
||||
<file action="link" path="../dac.c" targetDirectory="." />
|
||||
<file action="link" path="../dcsm.c" targetDirectory="." />
|
||||
<file action="link" path="../dma.c" targetDirectory="." />
|
||||
<file action="link" path="../ecap.c" targetDirectory="." />
|
||||
<file action="link" path="../emif.c" targetDirectory="." />
|
||||
<file action="link" path="../epwm.c" targetDirectory="." />
|
||||
<file action="link" path="../eqep.c" targetDirectory="." />
|
||||
<file action="link" path="../flash.c" targetDirectory="." />
|
||||
<file action="link" path="../gpio.c" targetDirectory="." />
|
||||
<file action="link" path="../hrpwm.c" targetDirectory="." />
|
||||
<file action="link" path="../i2c.c" targetDirectory="." />
|
||||
<file action="link" path="../ipc.c" targetDirectory="." />
|
||||
<file action="link" path="../interrupt.c" targetDirectory="." />
|
||||
<file action="link" path="../mcbsp.c" targetDirectory="." />
|
||||
<file action="link" path="../memcfg.c" targetDirectory="." />
|
||||
<file action="link" path="../sci.c" targetDirectory="." />
|
||||
<file action="link" path="../sdfm.c" targetDirectory="." />
|
||||
<file action="link" path="../spi.c" targetDirectory="." />
|
||||
<file action="link" path="../sysctl.c" targetDirectory="." />
|
||||
<file action="link" path="../upp.c" targetDirectory="." />
|
||||
<file action="link" path="../usb.c" targetDirectory="." />
|
||||
<file action="link" path="../version.c" targetDirectory="." />
|
||||
<file action="link" path="../xbar.c" targetDirectory="." />
|
||||
</project>
|
||||
</projectSpec>
|
|
@ -0,0 +1,87 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: cla.c
|
||||
//
|
||||
// TITLE: CLA Driver Implementation File
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "cla.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// CLA_setTriggerSource()
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger)
|
||||
{
|
||||
uint32_t srcSelReg;
|
||||
uint32_t shiftVal;
|
||||
|
||||
//
|
||||
// Calculate the shift value for the specified task.
|
||||
//
|
||||
shiftVal = ((uint32_t)taskNumber * SYSCTL_CLA1TASKSRCSEL1_TASK2_S) % 32U;
|
||||
|
||||
//
|
||||
// Calculate the register address for the specified task.
|
||||
//
|
||||
if(taskNumber <= CLA_TASK_4)
|
||||
{
|
||||
//
|
||||
// Tasks 1-4
|
||||
//
|
||||
srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL1;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Tasks 5-8
|
||||
//
|
||||
srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL2;
|
||||
}
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Write trigger selection to the appropriate register.
|
||||
//
|
||||
HWREG(srcSelReg) &= ~((uint32_t)SYSCTL_CLA1TASKSRCSEL1_TASK1_M
|
||||
<< shiftVal);
|
||||
HWREG(srcSelReg) = HWREG(srcSelReg) | ((uint32_t)trigger << shiftVal);
|
||||
|
||||
EDIS;
|
||||
}
|
|
@ -0,0 +1,982 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: cla.h
|
||||
//
|
||||
// TITLE: CLA Driver Implementation File
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef CLA_H
|
||||
#define CLA_H
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup cla_api CLA
|
||||
//! \brief This module is used for configurating CLA.
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "cpu.h"
|
||||
#include "debug.h"
|
||||
#include "inc/hw_cla.h"
|
||||
#include "inc/hw_memmap.h"
|
||||
#include "inc/hw_sysctl.h"
|
||||
#include "inc/hw_types.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Useful defines used within the driver functions. Not intended for use by
|
||||
// application code.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CLA_NUM_EOT_INTERRUPTS (8U)
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to CLA_clearTaskFlags(), CLA_forceTasks(),
|
||||
// and CLA_enableTasks(), CLA_disableTasks(), and CLA_enableSoftwareInterrupt()
|
||||
// as the taskFlags parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CLA_TASKFLAG_1 (0x01U) //!< CLA Task 1 Flag
|
||||
#define CLA_TASKFLAG_2 (0x02U) //!< CLA Task 2 Flag
|
||||
#define CLA_TASKFLAG_3 (0x04U) //!< CLA Task 3 Flag
|
||||
#define CLA_TASKFLAG_4 (0x08U) //!< CLA Task 4 Flag
|
||||
#define CLA_TASKFLAG_5 (0x10U) //!< CLA Task 5 Flag
|
||||
#define CLA_TASKFLAG_6 (0x20U) //!< CLA Task 6 Flag
|
||||
#define CLA_TASKFLAG_7 (0x40U) //!< CLA Task 7 Flag
|
||||
#define CLA_TASKFLAG_8 (0x80U) //!< CLA Task 8 Flag
|
||||
#define CLA_TASKFLAG_ALL (0xFFU) //!< CLA All Task Flag
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values that can be passed to CLA_getPendingTaskFlag(),
|
||||
//! CLA_getTaskOverflowFlag(), CLA_getTaskRunStatus(), CLA_setTriggerSource(),
|
||||
//! CLA_registerEndOfTaskInterrupt(), and CLA_unregisterEndOfTaskInterrupt()
|
||||
//! as the taskNumber parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
CLA_TASK_1, //!< CLA Task 1
|
||||
CLA_TASK_2, //!< CLA Task 2
|
||||
CLA_TASK_3, //!< CLA Task 3
|
||||
CLA_TASK_4, //!< CLA Task 4
|
||||
CLA_TASK_5, //!< CLA Task 5
|
||||
CLA_TASK_6, //!< CLA Task 6
|
||||
CLA_TASK_7, //!< CLA Task 7
|
||||
CLA_TASK_8 //!< CLA Task 8
|
||||
} CLA_TaskNumber;
|
||||
|
||||
#ifdef __TMS320C28XX__ // These enums are only accessible by C28x
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values that can be passed to CLA_mapTaskVector() as the \e claIntVect
|
||||
//! parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
CLA_MVECT_1 = CLA_O_MVECT1, //!< Task Interrupt Vector 1
|
||||
CLA_MVECT_2 = CLA_O_MVECT2, //!< Task Interrupt Vector 2
|
||||
CLA_MVECT_3 = CLA_O_MVECT3, //!< Task Interrupt Vector 3
|
||||
CLA_MVECT_4 = CLA_O_MVECT4, //!< Task Interrupt Vector 4
|
||||
CLA_MVECT_5 = CLA_O_MVECT5, //!< Task Interrupt Vector 5
|
||||
CLA_MVECT_6 = CLA_O_MVECT6, //!< Task Interrupt Vector 6
|
||||
CLA_MVECT_7 = CLA_O_MVECT7, //!< Task Interrupt Vector 7
|
||||
CLA_MVECT_8 = CLA_O_MVECT8 //!< Task Interrupt Vector 8
|
||||
} CLA_MVECTNumber;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values that can be passed to CLA_setTriggerSource() as the \e trigger
|
||||
//! parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
CLA_TRIGGER_SOFTWARE = 0U, //!< CLA Task Trigger Source is Software
|
||||
|
||||
CLA_TRIGGER_ADCA1 = 1U, //!< CLA Task Trigger Source is ADCA1
|
||||
CLA_TRIGGER_ADCA2 = 2U, //!< CLA Task Trigger Source is ADCA2
|
||||
CLA_TRIGGER_ADCA3 = 3U, //!< CLA Task Trigger Source is ADCA3
|
||||
CLA_TRIGGER_ADCA4 = 4U, //!< CLA Task Trigger Source is ADCA4
|
||||
CLA_TRIGGER_ADCAEVT = 5U, //!< CLA Task Trigger Source is ADCAEVT
|
||||
CLA_TRIGGER_ADCB1 = 6U, //!< CLA Task Trigger Source is ADCB1
|
||||
CLA_TRIGGER_ADCB2 = 7U, //!< CLA Task Trigger Source is ADCB2
|
||||
CLA_TRIGGER_ADCB3 = 8U, //!< CLA Task Trigger Source is ADCB3
|
||||
CLA_TRIGGER_ADCB4 = 9U, //!< CLA Task Trigger Source is ADCB4
|
||||
CLA_TRIGGER_ADCBEVT = 10U, //!< CLA Task Trigger Source is ADCBEVT
|
||||
CLA_TRIGGER_ADCC1 = 11U, //!< CLA Task Trigger Source is ADCC1
|
||||
CLA_TRIGGER_ADCC2 = 12U, //!< CLA Task Trigger Source is ADCC2
|
||||
CLA_TRIGGER_ADCC3 = 13U, //!< CLA Task Trigger Source is ADCC3
|
||||
CLA_TRIGGER_ADCC4 = 14U, //!< CLA Task Trigger Source is ADCC4
|
||||
CLA_TRIGGER_ADCCEVT = 15U, //!< CLA Task Trigger Source is ADCCEVT
|
||||
CLA_TRIGGER_ADCD1 = 16U, //!< CLA Task Trigger Source is ADCD1
|
||||
CLA_TRIGGER_ADCD2 = 17U, //!< CLA Task Trigger Source is ADCD2
|
||||
CLA_TRIGGER_ADCD3 = 18U, //!< CLA Task Trigger Source is ADCD3
|
||||
CLA_TRIGGER_ADCD4 = 19U, //!< CLA Task Trigger Source is ADCD4
|
||||
CLA_TRIGGER_ADCDEVT = 20U, //!< CLA Task Trigger Source is ADCDEVT
|
||||
|
||||
CLA_TRIGGER_XINT1 = 29U, //!< CLA Task Trigger Source is XINT1
|
||||
CLA_TRIGGER_XINT2 = 30U, //!< CLA Task Trigger Source is XINT2
|
||||
CLA_TRIGGER_XINT3 = 31U, //!< CLA Task Trigger Source is XINT3
|
||||
CLA_TRIGGER_XINT4 = 32U, //!< CLA Task Trigger Source is XINT4
|
||||
CLA_TRIGGER_XINT5 = 33U, //!< CLA Task Trigger Source is XINT5
|
||||
|
||||
CLA_TRIGGER_EPWM1INT = 36U, //!< CLA Task Trigger Source is EPWM1INT
|
||||
CLA_TRIGGER_EPWM2INT = 37U, //!< CLA Task Trigger Source is EPWM2INT
|
||||
CLA_TRIGGER_EPWM3INT = 38U, //!< CLA Task Trigger Source is EPWM3INT
|
||||
CLA_TRIGGER_EPWM4INT = 39U, //!< CLA Task Trigger Source is EPWM4INT
|
||||
CLA_TRIGGER_EPWM5INT = 40U, //!< CLA Task Trigger Source is EPWM5INT
|
||||
CLA_TRIGGER_EPWM6INT = 41U, //!< CLA Task Trigger Source is EPWM6INT
|
||||
CLA_TRIGGER_EPWM7INT = 42U, //!< CLA Task Trigger Source is EPWM7INT
|
||||
CLA_TRIGGER_EPWM8INT = 43U, //!< CLA Task Trigger Source is EPWM8INT
|
||||
CLA_TRIGGER_EPWM9INT = 44U, //!< CLA Task Trigger Source is EPWM9INT
|
||||
CLA_TRIGGER_EPWM10INT = 45U, //!< CLA Task Trigger Source is EPWM10INT
|
||||
CLA_TRIGGER_EPWM11INT = 46U, //!< CLA Task Trigger Source is EPWM11INT
|
||||
CLA_TRIGGER_EPWM12INT = 47U, //!< CLA Task Trigger Source is EPWM12INT
|
||||
|
||||
|
||||
CLA_TRIGGER_TINT0 = 68U, //!< CLA Task Trigger Source is TINT0
|
||||
CLA_TRIGGER_TINT1 = 69U, //!< CLA Task Trigger Source is TINT1
|
||||
CLA_TRIGGER_TINT2 = 70U, //!< CLA Task Trigger Source is TINT2
|
||||
|
||||
CLA_TRIGGER_MXINTA = 71U, //!< CLA Task Trigger Source is MXINTA
|
||||
CLA_TRIGGER_MRINTA = 72U, //!< CLA Task Trigger Source is MRINTA
|
||||
CLA_TRIGGER_MXINTB = 73U, //!< CLA Task Trigger Source is MXINTB
|
||||
CLA_TRIGGER_MRINTB = 74U, //!< CLA Task Trigger Source is MRINTB
|
||||
|
||||
CLA_TRIGGER_ECAP1INT = 75U, //!< CLA Task Trigger Source is ECAP1INT
|
||||
CLA_TRIGGER_ECAP2INT = 76U, //!< CLA Task Trigger Source is ECAP2INT
|
||||
CLA_TRIGGER_ECAP3INT = 77U, //!< CLA Task Trigger Source is ECAP3INT
|
||||
CLA_TRIGGER_ECAP4INT = 78U, //!< CLA Task Trigger Source is ECAP4INT
|
||||
CLA_TRIGGER_ECAP5INT = 79U, //!< CLA Task Trigger Source is ECAP5INT
|
||||
CLA_TRIGGER_ECAP6INT = 80U, //!< CLA Task Trigger Source is ECAP6INT
|
||||
|
||||
CLA_TRIGGER_EQEP1INT = 83U, //!< CLA Task Trigger Source is EQEP1INT
|
||||
CLA_TRIGGER_EQEP2INT = 84U, //!< CLA Task Trigger Source is EQEP2INT
|
||||
CLA_TRIGGER_EQEP3INT = 85U, //!< CLA Task Trigger Source is EQEP3INT
|
||||
|
||||
|
||||
CLA_TRIGGER_SDFM1INT = 95U, //!< CLA Task Trigger Source is SDFM1INT
|
||||
CLA_TRIGGER_SDFM2INT = 96U, //!< CLA Task Trigger Source is SDFM2INT
|
||||
|
||||
|
||||
|
||||
CLA_TRIGGER_UPP1INT = 107U, //!< CLA Task Trigger Source is UPP1INT
|
||||
|
||||
CLA_TRIGGER_SPITXAINT = 109U, //!< CLA Task Trigger Source is SPITXAINT
|
||||
CLA_TRIGGER_SPIRXAINT = 110U, //!< CLA Task Trigger Source is SPIRXAINT
|
||||
CLA_TRIGGER_SPITXBINT = 111U, //!< CLA Task Trigger Source is SPITXBINT
|
||||
CLA_TRIGGER_SPIRXBINT = 112U, //!< CLA Task Trigger Source is SPIRXBINT
|
||||
CLA_TRIGGER_SPITXCINT = 113U, //!< CLA Task Trigger Source is SPITXCINT
|
||||
CLA_TRIGGER_SPIRXCINT = 114U, //!< CLA Task Trigger Source is SPIRXCINT
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
CLA_TRIGGER_CLB1INT = 127, //!< CLA Task Trigger Source is CLB1INT
|
||||
CLA_TRIGGER_CLB2INT = 128, //!< CLA Task Trigger Source is CLB2INT
|
||||
CLA_TRIGGER_CLB3INT = 129, //!< CLA Task Trigger Source is CLB3INT
|
||||
CLA_TRIGGER_CLB4INT = 130, //!< CLA Task Trigger Source is CLB4INT
|
||||
|
||||
} CLA_Trigger;
|
||||
#endif // __TMS320C28XX__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \internal
|
||||
//! Checks a CLA base address.
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//!
|
||||
//! This function determines if a CLA controller base address is valid.
|
||||
//!
|
||||
//! \return Returns \b true if the base address is valid and \b false
|
||||
//! otherwise.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef DEBUG
|
||||
static inline bool
|
||||
CLA_isBaseValid(uint32_t base)
|
||||
{
|
||||
return(base == CLA1_BASE);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef __TMS320C28XX__ // These functions are only accessible from the C28x
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Map CLA Task Interrupt Vector
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//! \param claIntVect is CLA interrupt vector (MVECT1 to MVECT8)
|
||||
//! the value of claIntVect can be any of the following:
|
||||
//! - \b CLA_MVECT_1 - Task Interrupt Vector 1
|
||||
//! - \b CLA_MVECT_2 - Task Interrupt Vector 2
|
||||
//! - \b CLA_MVECT_3 - Task Interrupt Vector 3
|
||||
//! - \b CLA_MVECT_4 - Task Interrupt Vector 4
|
||||
//! - \b CLA_MVECT_5 - Task Interrupt Vector 5
|
||||
//! - \b CLA_MVECT_6 - Task Interrupt Vector 6
|
||||
//! - \b CLA_MVECT_7 - Task Interrupt Vector 7
|
||||
//! - \b CLA_MVECT_8 - Task Interrupt Vector 8
|
||||
//! \param claTaskAddr is the start address of the code for task
|
||||
//!
|
||||
//! Each CLA Task (1 to 8) has its own MVECTx register. When a task is
|
||||
//! triggered, the CLA loads the MVECTx register of the task in question
|
||||
//! to the MPC (CLA program counter) and begins execution from that point.
|
||||
//! The CLA has a 16-bit address bus, and can therefore, access the lower
|
||||
//! 64 KW space. The MVECTx registers take an address anywhere in this space.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_mapTaskVector(uint32_t base, CLA_MVECTNumber claIntVect,
|
||||
uint16_t claTaskAddr)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Modify protected register
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
HWREGH(base + (uint16_t)claIntVect) = claTaskAddr;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Hard Reset
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//!
|
||||
//! This function will cause a hard reset of the CLA and set all CLA registers
|
||||
//! to their default state.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_performHardReset(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Modify protected register
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Hard reset of the CLA
|
||||
//
|
||||
HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_HARDRESET;
|
||||
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Wait for few cycles till the reset is complete
|
||||
//
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Soft Reset
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//!
|
||||
//! This function will cause a soft reset of the CLA. This will stop the
|
||||
//! current task, clear the MIRUN flag and clear all bits in the MIER register.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_performSoftReset(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Modify protected register
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Soft reset of the CLA
|
||||
//
|
||||
HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_SOFTRESET;
|
||||
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Wait for few cycles till the reset is complete
|
||||
//
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! IACK enable
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//!
|
||||
//! This function enables the main CPU to use the IACK #16bit instruction to
|
||||
//! set MIFR bits in the same manner as writing to the MIFRC register.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_enableIACK(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Modify protected register
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable the main CPU to use the IACK #16bit instruction
|
||||
//
|
||||
HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_IACKE;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! IACK disable
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//!
|
||||
//! This function disables the main CPU to use the IACK #16bit instruction to
|
||||
//! set MIFR bits in the same manner as writing to the MIFRC register.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_disableIACK(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Modify protected register
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable the main CPU to use the IACK #16bit instruction
|
||||
//
|
||||
HWREGH(base + CLA_O_MCTL) &= ~CLA_MCTL_IACKE;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Query task N to see if it is flagged and pending execution
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
|
||||
//! from 1 to 8. Do not use CLA_TASKFLAG_ALL.
|
||||
//!
|
||||
//! This function gets the status of each bit in the interrupt flag register
|
||||
//! corresponds to a CLA task. The corresponding bit is automatically set
|
||||
//! when the task is triggered (either from a peripheral, through software, or
|
||||
//! through the MIFRC register). The bit gets cleared when the CLA starts to
|
||||
//! execute the flagged task.
|
||||
//!
|
||||
//! \return \b True if the queried task has been triggered but pending
|
||||
//! execution.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline bool
|
||||
CLA_getPendingTaskFlag(uint32_t base, CLA_TaskNumber taskNumber)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Read the run status register and return the appropriate value.
|
||||
//
|
||||
return(((HWREGH(base + CLA_O_MIFR) >> (uint16_t)taskNumber) & 1U) != 0U);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Get status of All Task Interrupt Flag
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//!
|
||||
//! This function gets the value of the interrupt flag register (MIFR)
|
||||
//!
|
||||
//! \return the value of Interrupt Flag Register (MIFR)
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline uint16_t
|
||||
CLA_getAllPendingTaskFlags(uint32_t base)
|
||||
{
|
||||
uint16_t status;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Just return the Interrupt Flag Register (MIFR) since that is what was
|
||||
// requested.
|
||||
//
|
||||
status = HWREGH(base + CLA_O_MIFR);
|
||||
|
||||
//
|
||||
// Return the Interrupt Flag Register value
|
||||
//
|
||||
return(status);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Get status of Task n Interrupt Overflow Flag
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
|
||||
//! from 1 to 8. Do not use CLA_TASKFLAG_ALL.
|
||||
//!
|
||||
//! This function gets the status of each bit in the overflow flag register
|
||||
//! corresponds to a CLA task, This bit is set when an interrupt overflow event
|
||||
//! has occurred for the specific task.
|
||||
//!
|
||||
//! \return True if any of task interrupt overflow has occurred.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline bool
|
||||
CLA_getTaskOverflowFlag(uint32_t base, CLA_TaskNumber taskNumber)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Read the run status register and return the appropriate value.
|
||||
//
|
||||
return(((HWREGH(base + CLA_O_MIOVF) >> (uint16_t)taskNumber) & 1U) != 0U);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Get status of All Task Interrupt Overflow Flag
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//!
|
||||
//! This function gets the value of the Interrupt Overflow Flag Register
|
||||
//!
|
||||
//! \return the value of Interrupt Overflow Flag Register(MIOVF)
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline uint16_t
|
||||
CLA_getAllTaskOverflowFlags(uint32_t base)
|
||||
{
|
||||
uint16_t status;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Just return Interrupt Overflow Flag Register(MIOVF) since that is what
|
||||
// was requested.
|
||||
//
|
||||
status = HWREGH(base + CLA_O_MIOVF);
|
||||
|
||||
//
|
||||
// Return the Interrupt Overflow Flag Register
|
||||
//
|
||||
return(status);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Clear the task interrupt flag
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//! \param taskFlags is the bitwise OR of the tasks' flags to be cleared
|
||||
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
|
||||
//! to clear all flags.
|
||||
//!
|
||||
//! This function is used to manually clear bits in the interrupt
|
||||
//! flag (MIFR) register
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_clearTaskFlags(uint32_t base, uint16_t taskFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
//Modify protected register
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Clear the task interrupt flag
|
||||
//
|
||||
HWREGH(base + CLA_O_MICLR) |= taskFlags;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Force a CLA Task
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//! \param taskFlags is the bitwise OR of the tasks' flags to be forced
|
||||
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
|
||||
//! to force all tasks.
|
||||
//!
|
||||
//! This function forces a task through software.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_forceTasks(uint32_t base, uint16_t taskFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Modify protected register
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Force the task interrupt.
|
||||
//
|
||||
HWREGH(base + CLA_O_MIFRC) |= taskFlags;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enable CLA task(s)
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//! \param taskFlags is the bitwise OR of the tasks' flags to be enabled
|
||||
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
|
||||
//! to enable all tasks
|
||||
//!
|
||||
//! This function allows an incoming interrupt or main CPU software to
|
||||
//! start the corresponding CLA task.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_enableTasks(uint32_t base, uint16_t taskFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Modify protected register
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable CLA task
|
||||
//
|
||||
HWREGH(base + CLA_O_MIER) |= taskFlags;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disable CLA task interrupt
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//! \param taskFlags is the bitwise OR of the tasks' flags to be disabled
|
||||
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
|
||||
//! to disable all tasks
|
||||
//!
|
||||
//! This function disables CLA task interrupt by setting the MIER register bit
|
||||
//! to 0, while the corresponding task is executing this will have no effect
|
||||
//! on the task. The task will continue to run until it hits the MSTOP
|
||||
//! instruction.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_disableTasks(uint32_t base, uint16_t taskFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Modify protected register
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Disable CLA task interrupt
|
||||
//
|
||||
HWREGH(base + CLA_O_MIER) &= ~taskFlags;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Get the value of a task run status
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
|
||||
//! from 1 to 8. Do not use CLA_TASKFLAG_ALL.
|
||||
//!
|
||||
//! This function gets the status of each bit in the Interrupt Run Status
|
||||
//! Register which indicates whether the task is currently executing
|
||||
//!
|
||||
//! \return True if the task is executing.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline bool
|
||||
CLA_getTaskRunStatus(uint32_t base, CLA_TaskNumber taskNumber)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Read the run status register and return the appropriate value.
|
||||
//
|
||||
return(((HWREGH(base + CLA_O_MIRUN) >> (uint16_t)taskNumber) & 1U) != 0U);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Get the value of all task run status
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//!
|
||||
//! This function indicates which task is currently executing.
|
||||
//!
|
||||
//! \return the value of Interrupt Run Status Register (MIRUN)
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline uint16_t
|
||||
CLA_getAllTaskRunStatus(uint32_t base)
|
||||
{
|
||||
uint16_t status;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Just return the Interrupt Run Status Register since that is what was
|
||||
// requested.
|
||||
//
|
||||
status = HWREGH(base + CLA_O_MIRUN);
|
||||
|
||||
//
|
||||
// Return the Interrupt Run Status Register (MIRUN)
|
||||
//
|
||||
return(status);
|
||||
}
|
||||
#endif // #ifdef __TMS320C28XX__
|
||||
|
||||
//
|
||||
// These functions are accessible only from the CLA (Type - 1/2)
|
||||
//
|
||||
#if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__)
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enable the Software Interrupt for a given CLA Task
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//! \param taskFlags is the bitwise OR of the tasks for which software
|
||||
//! interrupts are to be enabled, CLA_TASKFLAG_N where N is the task number
|
||||
//! from 1 to 8, or CLA_TASKFLAG_ALL to enable software interrupts of all tasks
|
||||
//!
|
||||
//! This function enables the Software Interrupt for a single, or set of, CLA
|
||||
//! task(s). It does this by writing a 1 to the task's bit in the
|
||||
//! CLA1SOFTINTEN register. By setting a task's SOFTINT bit, you disable its
|
||||
//! ability to generate an end-of-task interrupt
|
||||
//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to
|
||||
//! generate an end-of-task interrupt, but now any running CLA task has the
|
||||
//! ability to force task 2's interrupt (through the CLA1INTFRC register) to
|
||||
//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt
|
||||
//! handler even though the interrupt was not caused by Task 2 running to
|
||||
//! completion. This allows programmers to generate interrupts while a control
|
||||
//! task is running.
|
||||
//!
|
||||
//! \note
|
||||
//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA.
|
||||
//! -# Enabling a given task's software interrupt enable bit disables that
|
||||
//! task's ability to generate an End-of-Task interrupt to the main CPU,
|
||||
//! however, should another task force its interrupt (through the CLA1INTFRC
|
||||
//! register), it will be handled by that task's End-of-Task Interrupt Handler.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_enableSoftwareInterrupt(uint32_t base, uint16_t taskFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Modify protected register
|
||||
//
|
||||
__meallow();
|
||||
|
||||
//
|
||||
// Enable Software Interrupt
|
||||
//
|
||||
HWREGH(base + CLA_O_SOFTINTEN) |= taskFlags;
|
||||
|
||||
__medis();
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disable the Software Interrupt for a given CLA Task
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//! \param taskFlags is the bitwise OR of the tasks for which software
|
||||
//! interrupts are to be disabled, CLA_TASKFLAG_N where N is the task number
|
||||
//! from 1 to 8, or CLA_TASKFLAG_ALL to disable software interrupts of all
|
||||
//! tasks
|
||||
//!
|
||||
//! This function disables the Software Interrupt for a single, or set of, CLA
|
||||
//! task(s). It does this by writing a 0 to the task's bit in the
|
||||
//! CLA1SOFTINTEN register.
|
||||
//!
|
||||
//! \note
|
||||
//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA.
|
||||
//! -# Disabling a given task's software interrupt ability allows that
|
||||
//! task to generate an End-of-Task interrupt to the main CPU.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_disableSoftwareInterrupt(uint32_t base, uint16_t taskFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Modify protected register
|
||||
//
|
||||
__meallow();
|
||||
|
||||
//
|
||||
// Enable Software Interrupt
|
||||
//
|
||||
HWREGH(base + CLA_O_SOFTINTEN) &= ~taskFlags;
|
||||
|
||||
__medis();
|
||||
}
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Force a particular Task's Software Interrupt
|
||||
//!
|
||||
//! \param base is the base address of the CLA controller.
|
||||
//! \param taskFlags is the bitwise OR of the task's whose software
|
||||
//! interrupts are to be forced, CLA_TASKFLAG_N where N is the task number
|
||||
//! from 1 to 8, or CLA_TASKFLAG_ALL to force software interrupts for all tasks
|
||||
//!
|
||||
//! This function forces the Software Interrupt for a single, or set of, CLA
|
||||
//! task(s). It does this by writing a 1 to the task's bit in the
|
||||
//! CLA1INTFRC register.
|
||||
//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to
|
||||
//! generate an end-of-task interrupt, but now any running CLA task has the
|
||||
//! ability to force task 2's interrupt (through the CLA1INTFRC register) to
|
||||
//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt
|
||||
//! handler even though the interrupt was not caused by Task 2 running to
|
||||
//! completion. This allows programmers to generate interrupts while a control
|
||||
//! task is running.
|
||||
//!
|
||||
//! \note
|
||||
//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA.
|
||||
//! -# Enabling a given task's software interrupt enable bit disables that
|
||||
//! task's ability to generate an End-of-Task interrupt to the main CPU,
|
||||
//! however, should another task force its interrupt (through the CLA1INTFRC
|
||||
//! register), it will be handled by that task's End-of-Task Interrupt Handler.
|
||||
//! -# This function will set the INTFRC bit for a task, but does not check
|
||||
//! that its SOFTINT bit is set. It falls to the user to ensure that software
|
||||
//! interrupt for a given task is enabled before it can be forced.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
CLA_forceSoftwareInterrupt(uint32_t base, uint16_t taskFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CLA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Modify protected register
|
||||
//
|
||||
__meallow();
|
||||
|
||||
//
|
||||
// Force Software Interrupt
|
||||
//
|
||||
HWREGH(base + CLA_O_SOFTINTFRC) |= taskFlags;
|
||||
|
||||
__medis();
|
||||
}
|
||||
|
||||
#endif // #if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__)
|
||||
|
||||
//
|
||||
// These functions can only be called from the C28x
|
||||
//
|
||||
#ifdef __TMS320C28XX__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Configures CLA task triggers.
|
||||
//!
|
||||
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
|
||||
//! from 1 to 8.
|
||||
//! \param trigger is the trigger source to be assigned to the selected task.
|
||||
//!
|
||||
//! This function configures the trigger source of a CLA task. The
|
||||
//! \e taskNumber parameter indicates which task is being configured, and the
|
||||
//! \e trigger parameter is the interrupt source from a specific peripheral
|
||||
//! interrupt (or software) that will trigger the task.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void
|
||||
CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger);
|
||||
|
||||
#endif //#ifdef __TMS320C28XX__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // CLA_H
|
|
@ -0,0 +1,143 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: clb.c
|
||||
//
|
||||
// TITLE: C28x CLB driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "clb.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// CLB_configCounterLoadMatch
|
||||
//
|
||||
//*****************************************************************************
|
||||
void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID,
|
||||
uint32_t load, uint32_t match1, uint32_t match2)
|
||||
{
|
||||
ASSERT(CLB_isBaseValid(base));
|
||||
|
||||
EALLOW;
|
||||
switch(counterID)
|
||||
{
|
||||
case CLB_CTR0:
|
||||
CLB_writeInterface(base, CLB_ADDR_COUNTER_0_LOAD, load);
|
||||
CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH1, match1);
|
||||
CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH2, match2);
|
||||
break;
|
||||
|
||||
case CLB_CTR1:
|
||||
CLB_writeInterface(base, CLB_ADDR_COUNTER_1_LOAD, load);
|
||||
CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH1, match1);
|
||||
CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH2, match2);
|
||||
break;
|
||||
|
||||
case CLB_CTR2:
|
||||
CLB_writeInterface(base, CLB_ADDR_COUNTER_2_LOAD, load);
|
||||
CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH1, match1);
|
||||
CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH2, match2);
|
||||
break;
|
||||
|
||||
default:
|
||||
//
|
||||
// Invalid counterID value
|
||||
//
|
||||
break;
|
||||
}
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// CLB_clearFIFOs
|
||||
//
|
||||
//*****************************************************************************
|
||||
void CLB_clearFIFOs(uint32_t base)
|
||||
{
|
||||
uint16_t i;
|
||||
|
||||
ASSERT(CLB_isBaseValid(base));
|
||||
|
||||
for(i = 0U; i < CLB_FIFO_SIZE; i++)
|
||||
{
|
||||
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(i)) = 0U;
|
||||
}
|
||||
|
||||
HWREG(base + CLB_LOGICCTL + CLB_O_BUF_PTR) = 0U;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// CLB_writeFIFOs
|
||||
//
|
||||
//*****************************************************************************
|
||||
void CLB_writeFIFOs(uint32_t base , const uint32_t pullData[])
|
||||
{
|
||||
ASSERT(CLB_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Clear the FIFO and pointer
|
||||
//
|
||||
CLB_clearFIFOs(base);
|
||||
|
||||
//
|
||||
// Write data into the FIFO.
|
||||
//
|
||||
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(0)) = pullData[0U];
|
||||
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(1)) = pullData[1U];
|
||||
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(2)) = pullData[2U];
|
||||
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(3)) = pullData[3U];
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// CLB_readFIFOs
|
||||
//
|
||||
//*****************************************************************************
|
||||
void CLB_readFIFOs(uint32_t base , uint32_t pushData[])
|
||||
{
|
||||
ASSERT(CLB_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Read data from the FIFO.
|
||||
//
|
||||
pushData[0U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(0)) ;
|
||||
pushData[1U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(1)) ;
|
||||
pushData[2U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(2)) ;
|
||||
pushData[3U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(3)) ;
|
||||
}
|
||||
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,221 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: cmpss.c
|
||||
//
|
||||
// TITLE: C28x CMPSS driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "cmpss.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// CMPSS_configFilterHigh
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale,
|
||||
uint16_t sampleWindow, uint16_t threshold)
|
||||
{
|
||||
uint16_t regValue;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CMPSS_isBaseValid(base));
|
||||
ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U));
|
||||
|
||||
//
|
||||
// Shift the sample window and threshold values into the correct positions
|
||||
// and write them to the appropriate register.
|
||||
//
|
||||
regValue = ((sampleWindow - 1U) << CMPSS_CTRIPHFILCTL_SAMPWIN_S) |
|
||||
((threshold - 1U) << CMPSS_CTRIPHFILCTL_THRESH_S);
|
||||
|
||||
EALLOW;
|
||||
|
||||
HWREGH(base + CMPSS_O_CTRIPHFILCTL) =
|
||||
(HWREGH(base + CMPSS_O_CTRIPHFILCTL) &
|
||||
~(CMPSS_CTRIPHFILCTL_SAMPWIN_M | CMPSS_CTRIPHFILCTL_THRESH_M)) |
|
||||
regValue;
|
||||
|
||||
//
|
||||
// Set the filter sample clock prescale for the high comparator.
|
||||
//
|
||||
HWREGH(base + CMPSS_O_CTRIPHFILCLKCTL) = samplePrescale;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// CMPSS_configFilterLow
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale,
|
||||
uint16_t sampleWindow, uint16_t threshold)
|
||||
{
|
||||
uint16_t regValue;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CMPSS_isBaseValid(base));
|
||||
ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U));
|
||||
|
||||
//
|
||||
// Shift the sample window and threshold values into the correct positions
|
||||
// and write them to the appropriate register.
|
||||
//
|
||||
regValue = ((sampleWindow - 1U) << CMPSS_CTRIPLFILCTL_SAMPWIN_S) |
|
||||
((threshold - 1U) << CMPSS_CTRIPLFILCTL_THRESH_S);
|
||||
|
||||
EALLOW;
|
||||
|
||||
HWREGH(base + CMPSS_O_CTRIPLFILCTL) =
|
||||
(HWREGH(base + CMPSS_O_CTRIPLFILCTL) &
|
||||
~(CMPSS_CTRIPLFILCTL_SAMPWIN_M | CMPSS_CTRIPLFILCTL_THRESH_M)) |
|
||||
regValue;
|
||||
|
||||
//
|
||||
// Set the filter sample clock prescale for the low comparator.
|
||||
//
|
||||
HWREGH(base + CMPSS_O_CTRIPLFILCLKCTL) = samplePrescale;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// CMPSS_configLatchOnPWMSYNC
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
CMPSS_configLatchOnPWMSYNC(uint32_t base, bool highEnable, bool lowEnable)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CMPSS_isBaseValid(base));
|
||||
|
||||
//
|
||||
// If the highEnable is true, set the bit that will enable PWMSYNC to reset
|
||||
// the high comparator digital filter latch. If not, clear the bit.
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
if(highEnable)
|
||||
{
|
||||
HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HSYNCCLREN;
|
||||
}
|
||||
else
|
||||
{
|
||||
HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_HSYNCCLREN;
|
||||
}
|
||||
|
||||
//
|
||||
// If the lowEnable is true, set the bit that will enable PWMSYNC to reset
|
||||
// the low comparator digital filter latch. If not, clear the bit.
|
||||
//
|
||||
if(lowEnable)
|
||||
{
|
||||
HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LSYNCCLREN;
|
||||
}
|
||||
else
|
||||
{
|
||||
HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_LSYNCCLREN;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// CMPSS_configRamp
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal,
|
||||
uint16_t delayVal, uint16_t pwmSyncSrc, bool useRampValShdw)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(CMPSS_isBaseValid(base));
|
||||
ASSERT(delayVal <= CMPSS_RAMPDLYS_DELAY_M);
|
||||
ASSERT((pwmSyncSrc >= 1U) && (pwmSyncSrc <= 12U));
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Write the ramp generator source to the register
|
||||
//
|
||||
HWREGH(base + CMPSS_O_COMPDACCTL) =
|
||||
(HWREGH(base + CMPSS_O_COMPDACCTL) &
|
||||
~CMPSS_COMPDACCTL_RAMPSOURCE_M) |
|
||||
((uint16_t)(pwmSyncSrc - 1U) << CMPSS_COMPDACCTL_RAMPSOURCE_S);
|
||||
|
||||
//
|
||||
// Set or clear the bit that determines from where the max ramp value
|
||||
// should be loaded.
|
||||
//
|
||||
if(useRampValShdw)
|
||||
{
|
||||
HWREGH(base + CMPSS_O_COMPDACCTL) |= CMPSS_COMPDACCTL_RAMPLOADSEL;
|
||||
}
|
||||
else
|
||||
{
|
||||
HWREGH(base + CMPSS_O_COMPDACCTL) &= ~CMPSS_COMPDACCTL_RAMPLOADSEL;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Write the maximum ramp value to the shadow register.
|
||||
//
|
||||
HWREGH(base + CMPSS_O_RAMPMAXREFS) = maxRampVal;
|
||||
|
||||
//
|
||||
// Write the ramp decrement value to the shadow register.
|
||||
//
|
||||
HWREGH(base + CMPSS_O_RAMPDECVALS) = decrementVal;
|
||||
|
||||
//
|
||||
// Write the ramp delay value to the shadow register.
|
||||
//
|
||||
HWREGH(base + CMPSS_O_RAMPDLYS) = delayVal;
|
||||
}
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,170 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: cpu.h
|
||||
//
|
||||
// TITLE: Useful C28x CPU defines.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef CPU_H
|
||||
#define CPU_H
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
//
|
||||
// External reference to the interrupt flag register (IFR) register
|
||||
//
|
||||
#ifndef __TMS320C28XX_CLA__
|
||||
extern __cregister volatile uint16_t IFR;
|
||||
#endif
|
||||
|
||||
//
|
||||
// External reference to the interrupt enable register (IER) register
|
||||
//
|
||||
#ifndef __TMS320C28XX_CLA__
|
||||
extern __cregister volatile uint16_t IER;
|
||||
#endif
|
||||
|
||||
//
|
||||
// Define to enable interrupts
|
||||
//
|
||||
#ifndef EINT
|
||||
#define EINT __asm(" clrc INTM")
|
||||
#endif
|
||||
|
||||
//
|
||||
// Define to disable interrupts
|
||||
//
|
||||
#ifndef DINT
|
||||
#define DINT __asm(" setc INTM")
|
||||
#endif
|
||||
|
||||
//
|
||||
// Define to enable debug events
|
||||
//
|
||||
#ifndef ERTM
|
||||
#define ERTM __asm(" clrc DBGM")
|
||||
#endif
|
||||
|
||||
//
|
||||
// Define to disable debug events
|
||||
//
|
||||
#ifndef DRTM
|
||||
#define DRTM __asm(" setc DBGM")
|
||||
#endif
|
||||
|
||||
//
|
||||
// Define to allow writes to protected registers
|
||||
//
|
||||
#ifndef EALLOW
|
||||
#ifndef __TMS320C28XX_CLA__
|
||||
#define EALLOW __eallow()
|
||||
#else
|
||||
#define EALLOW __meallow()
|
||||
#endif // __TMS320C28XX_CLA__
|
||||
#endif // EALLOW
|
||||
|
||||
//
|
||||
// Define to disable writes to protected registers
|
||||
//
|
||||
#ifndef EDIS
|
||||
#ifndef __TMS320C28XX_CLA__
|
||||
#define EDIS __edis()
|
||||
#else
|
||||
#define EDIS __medis()
|
||||
#endif // __TMS320C28XX_CLA__
|
||||
#endif // EDIS
|
||||
|
||||
//
|
||||
// Define for emulation stop
|
||||
//
|
||||
#ifndef ESTOP0
|
||||
#define ESTOP0 __asm(" ESTOP0")
|
||||
#endif
|
||||
|
||||
//
|
||||
// Define for emulation stop
|
||||
//
|
||||
#ifndef ESTOP1
|
||||
#define ESTOP1 __asm(" ESTOP1")
|
||||
#endif
|
||||
|
||||
//
|
||||
// Define for no operation
|
||||
//
|
||||
#ifndef NOP
|
||||
#define NOP __asm(" NOP")
|
||||
#endif
|
||||
|
||||
//
|
||||
// Define for putting processor into a low-power mode
|
||||
//
|
||||
#ifndef _DUAL_HEADERS
|
||||
#ifndef IDLE
|
||||
#define IDLE __asm(" IDLE")
|
||||
#endif
|
||||
#else
|
||||
#define IDLE_ASM __asm(" IDLE");
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Extern compiler intrinsic prototypes. See compiler User's Guide for details.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void __eallow(void);
|
||||
extern void __edis(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // CPU_H
|
|
@ -0,0 +1,59 @@
|
|||
//#############################################################################
|
||||
//
|
||||
// FILE: cputimer.c
|
||||
//
|
||||
// TITLE: C28x CPU timer Driver
|
||||
//
|
||||
//#############################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
#include "cputimer.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// CPUTimer_setEmulationMode
|
||||
//
|
||||
//*****************************************************************************
|
||||
void CPUTimer_setEmulationMode(uint32_t base, CPUTimer_EmulationMode mode)
|
||||
{
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
//
|
||||
// Write to FREE_SOFT bits of register TCR
|
||||
//
|
||||
HWREGH(base + CPUTIMER_O_TCR) =
|
||||
(HWREGH(base + CPUTIMER_O_TCR) &
|
||||
~(CPUTIMER_TCR_FREE | CPUTIMER_TCR_SOFT)) |
|
||||
(uint16_t)mode;
|
||||
}
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
//#############################################################################
|
||||
//
|
||||
// FILE: cputimer.h
|
||||
//
|
||||
// TITLE: C28x CPU timer Driver
|
||||
//
|
||||
//#############################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
#ifndef CPUTIMER_H
|
||||
#define CPUTIMER_H
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#ifdef __TMS320C28XX__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup cputimer_api CPUTimer
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_memmap.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "inc/hw_cputimer.h"
|
||||
#include "debug.h"
|
||||
#include "sysctl.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for the API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values that can be passed to CPUTimer_setEmulationMode() as the
|
||||
//! \e mode parameter.
|
||||
//
|
||||
//****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
//! Denotes that the timer will stop after the next decrement
|
||||
CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT = 0x0000,
|
||||
//! Denotes that the timer will stop when it reaches zero
|
||||
CPUTIMER_EMULATIONMODE_STOPATZERO = 0x0400,
|
||||
//! Denotes that the timer will run free
|
||||
CPUTIMER_EMULATIONMODE_RUNFREE = 0x0800
|
||||
}CPUTimer_EmulationMode;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! The following are values that can be passed to
|
||||
//! CPUTimer_selectClockSource() as the \e source parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
//! System Clock Source
|
||||
CPUTIMER_CLOCK_SOURCE_SYS = 0x0,
|
||||
//! Internal Oscillator 1 Clock Source
|
||||
CPUTIMER_CLOCK_SOURCE_INTOSC1 = 0x1,
|
||||
//! Internal Oscillator 2 Clock Source
|
||||
CPUTIMER_CLOCK_SOURCE_INTOSC2 = 0x2,
|
||||
//! External Clock Source
|
||||
CPUTIMER_CLOCK_SOURCE_XTAL = 0x3,
|
||||
//! Auxiliary PLL Clock Source
|
||||
CPUTIMER_CLOCK_SOURCE_AUX = 0x6
|
||||
} CPUTimer_ClockSource;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! The following are values that can be passed to
|
||||
//! CPUTimer_selectClockSource() as the \e prescaler parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
CPUTIMER_CLOCK_PRESCALER_1 = 0, //!< Prescaler value of / 1
|
||||
CPUTIMER_CLOCK_PRESCALER_2 = 1, //!< Prescaler value of / 2
|
||||
CPUTIMER_CLOCK_PRESCALER_4 = 2, //!< Prescaler value of / 4
|
||||
CPUTIMER_CLOCK_PRESCALER_8 = 3, //!< Prescaler value of / 8
|
||||
CPUTIMER_CLOCK_PRESCALER_16 = 4 //!< Prescaler value of / 16
|
||||
} CPUTimer_Prescaler;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \internal
|
||||
//! Checks CPU timer base address.
|
||||
//!
|
||||
//! \param base specifies the Timer module base address.
|
||||
//!
|
||||
//! This function determines if a CPU timer module base address is valid.
|
||||
//!
|
||||
//! \return Returns \b true if the base address is valid and \b false
|
||||
//! otherwise.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef DEBUG
|
||||
static inline bool CPUTimer_isBaseValid(uint32_t base)
|
||||
{
|
||||
return((base == CPUTIMER0_BASE) || (base == CPUTIMER1_BASE) ||
|
||||
(base == CPUTIMER2_BASE));
|
||||
}
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Clears CPU timer overflow flag.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//!
|
||||
//! This function clears the CPU timer overflow flag.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void CPUTimer_clearOverflowFlag(uint32_t base)
|
||||
{
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Set TIF bit of TCR register
|
||||
//
|
||||
HWREGH(base + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables CPU timer interrupt.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//!
|
||||
//! This function disables the CPU timer interrupt.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void CPUTimer_disableInterrupt(uint32_t base)
|
||||
{
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Clear TIE bit of TCR register
|
||||
//
|
||||
HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TIE;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables CPU timer interrupt.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//!
|
||||
//! This function enables the CPU timer interrupt.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void CPUTimer_enableInterrupt(uint32_t base)
|
||||
{
|
||||
uint16_t tcrValue = 0;
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Set TIE bit of TCR register
|
||||
//
|
||||
tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF);
|
||||
HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TIE;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Reloads CPU timer counter.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//!
|
||||
//! This function reloads the CPU timer counter with the values contained in
|
||||
//! the CPU timer period register.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void CPUTimer_reloadTimerCounter(uint32_t base)
|
||||
{
|
||||
uint16_t tcrValue = 0;
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Set TRB bit of register TCR
|
||||
//
|
||||
tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF);
|
||||
HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Stops CPU timer.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//!
|
||||
//! This function stops the CPU timer.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void CPUTimer_stopTimer(uint32_t base)
|
||||
{
|
||||
uint16_t tcrValue = 0;
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Set TSS bit of register TCR
|
||||
//
|
||||
tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF);
|
||||
HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TSS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Starts(restarts) CPU timer.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//!
|
||||
//! This function starts (restarts) the CPU timer.
|
||||
//!
|
||||
//! \b Note: This function doesn't reset the timer counter.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void CPUTimer_resumeTimer(uint32_t base)
|
||||
{
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Clear TSS bit of register TCR
|
||||
//
|
||||
HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Starts(restarts) CPU timer.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//!
|
||||
//! This function starts (restarts) the CPU timer.
|
||||
//!
|
||||
//! \b Note: This function reloads the timer counter.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void CPUTimer_startTimer(uint32_t base)
|
||||
{
|
||||
uint16_t tcrValue = 0;
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Reload the timer counter
|
||||
//
|
||||
tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF);
|
||||
HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB;
|
||||
|
||||
//
|
||||
// Clear TSS bit of register TCR
|
||||
//
|
||||
HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets CPU timer period.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//! \param periodCount is the CPU timer period count.
|
||||
//!
|
||||
//! This function sets the CPU timer period count.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void CPUTimer_setPeriod(uint32_t base, uint32_t periodCount)
|
||||
{
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Load the MSB period Count
|
||||
//
|
||||
HWREG(base + CPUTIMER_O_PRD) = periodCount;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the current CPU timer counter value.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//!
|
||||
//! This function returns the current CPU timer counter value.
|
||||
//!
|
||||
//! \return Returns the current CPU timer count value.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline uint32_t CPUTimer_getTimerCount(uint32_t base)
|
||||
{
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Get the TIMH:TIM registers value
|
||||
//
|
||||
return(HWREG(base + CPUTIMER_O_TIM));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Set CPU timer pre-scaler value.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//! \param prescaler is the CPU timer pre-scaler value.
|
||||
//!
|
||||
//! This function sets the pre-scaler value for the CPU timer. For every value
|
||||
//! of (prescaler + 1), the CPU timer counter decrements by 1.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void CPUTimer_setPreScaler(uint32_t base, uint16_t prescaler)
|
||||
{
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Writes to TPR.TDDR and TPRH.TDDRH bits
|
||||
//
|
||||
HWREGH(base + CPUTIMER_O_TPRH) = prescaler >> 8U;
|
||||
HWREGH(base + CPUTIMER_O_TPR) = (prescaler & CPUTIMER_TPR_TDDR_M) ;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Return the CPU timer overflow status.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//!
|
||||
//! This function returns the CPU timer overflow status.
|
||||
//!
|
||||
//! \return Returns true if the CPU timer has overflowed, false if not.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline bool CPUTimer_getTimerOverflowStatus(uint32_t base)
|
||||
{
|
||||
ASSERT(CPUTimer_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Check if TIF bits of register TCR are set
|
||||
//
|
||||
return(((HWREGH(base + CPUTIMER_O_TCR) & CPUTIMER_TCR_TIF) ==
|
||||
CPUTIMER_TCR_TIF) ? true : false);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Select CPU Timer 2 Clock Source and Prescaler
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//! \param source is the clock source to use for CPU Timer 2
|
||||
//! \param prescaler is the value that configures the selected clock source
|
||||
//! relative to the system clock
|
||||
//!
|
||||
//! This function selects the specified clock source and prescaler value
|
||||
//! for the CPU timer (CPU timer 2 only).
|
||||
//!
|
||||
//! The \e source parameter can be any one of the following:
|
||||
//! - \b CPUTIMER_CLOCK_SOURCE_SYS - System Clock
|
||||
//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC1 - Internal Oscillator 1 Clock
|
||||
//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC2 - Internal Oscillator 2 Clock
|
||||
//! - \b CPUTIMER_CLOCK_SOURCE_XTAL - External Clock
|
||||
//! - \b CPUTIMER_CLOCK_SOURCE_AUX - Auxiliary PLL Clock
|
||||
//!
|
||||
//! The \e prescaler parameter can be any one of the following:
|
||||
//! - \b CPUTIMER_CLOCK_PRESCALER_1 - Prescaler value of / 1
|
||||
//! - \b CPUTIMER_CLOCK_PRESCALER_2 - Prescaler value of / 2
|
||||
//! - \b CPUTIMER_CLOCK_PRESCALER_4 - Prescaler value of / 4
|
||||
//! - \b CPUTIMER_CLOCK_PRESCALER_8 - Prescaler value of / 8
|
||||
//! - \b CPUTIMER_CLOCK_PRESCALER_16 - Prescaler value of / 16
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void CPUTimer_selectClockSource(uint32_t base,
|
||||
CPUTimer_ClockSource source,
|
||||
CPUTimer_Prescaler prescaler)
|
||||
{
|
||||
ASSERT(base == CPUTIMER2_BASE);
|
||||
|
||||
//
|
||||
// Set source and prescaler for CPU Timer 2
|
||||
//
|
||||
if(base == CPUTIMER2_BASE)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Set Clock Source
|
||||
//
|
||||
HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) &=
|
||||
~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M;
|
||||
|
||||
HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= (uint16_t)source;
|
||||
|
||||
//
|
||||
// Set Clock Prescaler
|
||||
//
|
||||
HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) &=
|
||||
~SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M;
|
||||
|
||||
HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= ((uint16_t)prescaler <<
|
||||
SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_S);
|
||||
|
||||
EDIS;
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets Emulation mode for CPU timer.
|
||||
//!
|
||||
//! \param base is the base address of the timer module.
|
||||
//! \param mode is the emulation mode of the timer.
|
||||
//!
|
||||
//! This function sets the behaviour of CPU timer during emulation. Valid
|
||||
//! values mode are: CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT,
|
||||
//! CPUTIMER_EMULATIONMODE_STOPATZERO and CPUTIMER_EMULATIONMODE_RUNFREE.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void CPUTimer_setEmulationMode(uint32_t base,
|
||||
CPUTimer_EmulationMode mode);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#endif // #ifdef __TMS320C28XX__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // CPUTIMER_H
|
|
@ -0,0 +1,91 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: dac.c
|
||||
//
|
||||
// TITLE: C28x DAC driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "dac.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DAC_tuneOffsetTrim()
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
void
|
||||
DAC_tuneOffsetTrim(uint32_t base, float32_t referenceVoltage)
|
||||
{
|
||||
uint16_t oldOffsetTrim;
|
||||
float32_t newOffsetTrim;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
ASSERT(referenceVoltage > 0U);
|
||||
|
||||
//
|
||||
// Get the sign-extended offset trim value
|
||||
//
|
||||
oldOffsetTrim = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M);
|
||||
oldOffsetTrim = ((oldOffsetTrim & (uint16_t)DAC_REG_BYTE_MASK) ^
|
||||
(uint16_t)0x80) - (uint16_t)0x80;
|
||||
|
||||
//
|
||||
// Calculate new offset trim value if DAC is operating at a reference
|
||||
// voltage other than 2.5v.
|
||||
//
|
||||
newOffsetTrim = ((float32_t)(2.5 / referenceVoltage) *
|
||||
(int16_t)oldOffsetTrim);
|
||||
|
||||
//
|
||||
// Check if the new offset trim value is valid
|
||||
//
|
||||
ASSERT(((int16_t)newOffsetTrim > -129) && ((int16_t)newOffsetTrim < 128));
|
||||
|
||||
//
|
||||
// Set the new offset trim value
|
||||
//
|
||||
EALLOW;
|
||||
HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) &
|
||||
~DAC_TRIM_OFFSET_TRIM_M) |
|
||||
(int16_t)newOffsetTrim;
|
||||
|
||||
EDIS;
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,601 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: dac.h
|
||||
//
|
||||
// TITLE: C28x DAC driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DAC_H
|
||||
#define DAC_H
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup dac_api DAC
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_dac.h"
|
||||
#include "inc/hw_memmap.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "cpu.h"
|
||||
#include "debug.h"
|
||||
|
||||
//
|
||||
// A 8-bit register mask
|
||||
//
|
||||
#define DAC_REG_BYTE_MASK (0xFFU) //!< Register Byte Mask
|
||||
|
||||
//
|
||||
// Lock Key
|
||||
//
|
||||
#define DAC_LOCK_KEY (0xA000U) //!< DAC Lock Key
|
||||
|
||||
#ifndef DOXYGEN_PDF_IGNORE
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the reg parameter of the
|
||||
// DAC_lockRegister() and DAC_isRegisterLocked() functions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DAC_LOCK_CONTROL (0x1U) //!< Lock the control register
|
||||
#define DAC_LOCK_SHADOW (0x2U) //!< Lock the shadow value register
|
||||
#define DAC_LOCK_OUTPUT (0x4U) //!< Lock the output enable register
|
||||
|
||||
#endif // DOXYGEN_PDF_IGNORE
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values that can be passed to DAC_setReferenceVoltage() as the \e source
|
||||
//! parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
DAC_REF_VDAC = 0, //!< VDAC reference voltage
|
||||
DAC_REF_ADC_VREFHI = 1 //!< ADC VREFHI reference voltage
|
||||
}DAC_ReferenceVoltage;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values that can be passed to DAC_setLoadMode() as the \e mode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
DAC_LOAD_SYSCLK = 0, //!< Load on next SYSCLK
|
||||
DAC_LOAD_PWMSYNC = 4 //!< Load on next PWMSYNC specified by SYNCSEL
|
||||
}DAC_LoadMode;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \internal
|
||||
//! Checks DAC base address.
|
||||
//!
|
||||
//! \param base specifies the DAC module base address.
|
||||
//!
|
||||
//! This function determines if an DAC module base address is valid.
|
||||
//!
|
||||
//! \return Returns \b true if the base address is valid and \b false
|
||||
//! otherwise.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef DEBUG
|
||||
static inline bool
|
||||
DAC_isBaseValid(uint32_t base)
|
||||
{
|
||||
return(
|
||||
(base == DACA_BASE) ||
|
||||
(base == DACB_BASE) ||
|
||||
(base == DACC_BASE)
|
||||
);
|
||||
}
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Get the DAC Revision value
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//!
|
||||
//! This function gets the DAC revision value.
|
||||
//!
|
||||
//! \return Returns the DAC revision value.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline uint16_t
|
||||
DAC_getRevision(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Get the revision value.
|
||||
//
|
||||
return(HWREGH(base + DAC_O_REV) & DAC_REV_REV_M);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the DAC Reference Voltage
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//! \param source is the selected reference voltage
|
||||
//!
|
||||
//! This function sets the DAC reference voltage.
|
||||
//!
|
||||
//! The \e source parameter can have one of two values:
|
||||
//! - \b DAC_REF_VDAC - The VDAC reference voltage
|
||||
//! - \b DAC_REF_ADC_VREFHI - The ADC VREFHI reference voltage
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
DAC_setReferenceVoltage(uint32_t base, DAC_ReferenceVoltage source)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Set the reference voltage
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) &
|
||||
~DAC_CTL_DACREFSEL) | (uint16_t)source;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the DAC Load Mode
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//! \param mode is the selected load mode
|
||||
//!
|
||||
//! This function sets the DAC load mode.
|
||||
//!
|
||||
//! The \e mode parameter can have one of two values:
|
||||
//! - \b DAC_LOAD_SYSCLK - Load on next SYSCLK
|
||||
//! - \b DAC_LOAD_PWMSYNC - Load on next PWMSYNC specified by SYNCSEL
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
DAC_setLoadMode(uint32_t base, DAC_LoadMode mode)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Set the load mode
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) &
|
||||
~DAC_CTL_LOADMODE) | (uint16_t)mode;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the DAC PWMSYNC Signal
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//! \param signal is the selected PWM signal
|
||||
//!
|
||||
//! This function sets the DAC PWMSYNC signal.
|
||||
//!
|
||||
//! The \e signal parameter must be set to a number that represents the PWM
|
||||
//! signal that will be set. For instance, passing 2 into \e signal will
|
||||
//! select PWM sync signal 2.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
DAC_setPWMSyncSignal(uint32_t base, uint16_t signal)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
ASSERT((signal > 0U) && (signal < 17U));
|
||||
|
||||
//
|
||||
// Set the PWM sync signal
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) &
|
||||
~DAC_CTL_SYNCSEL_M) |
|
||||
((uint16_t)(signal - 1U) << DAC_CTL_SYNCSEL_S);
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Get the DAC Active Output Value
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//!
|
||||
//! This function gets the DAC active output value.
|
||||
//!
|
||||
//! \return Returns the DAC active output value.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline uint16_t
|
||||
DAC_getActiveValue(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Get the active value
|
||||
//
|
||||
return(HWREGH(base + DAC_O_VALA) & DAC_VALA_DACVALA_M);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Set the DAC Shadow Output Value
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//! \param value is the 12-bit code to be loaded into the active value register
|
||||
//!
|
||||
//! This function sets the DAC shadow output value.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
DAC_setShadowValue(uint32_t base, uint16_t value)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
ASSERT(value <= DAC_VALS_DACVALS_M);
|
||||
|
||||
//
|
||||
// Set the shadow value
|
||||
//
|
||||
HWREGH(base + DAC_O_VALS) = (HWREGH(base + DAC_O_VALS) &
|
||||
~DAC_VALS_DACVALS_M) |
|
||||
(uint16_t)(value & DAC_VALS_DACVALS_M);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Get the DAC Shadow Output Value
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//!
|
||||
//! This function gets the DAC shadow output value.
|
||||
//!
|
||||
//! \return Returns the DAC shadow output value.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline uint16_t
|
||||
DAC_getShadowValue(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Get the shadow value
|
||||
//
|
||||
return(HWREGH(base + DAC_O_VALS) & DAC_VALS_DACVALS_M);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enable the DAC Output
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//!
|
||||
//! This function enables the DAC output.
|
||||
//!
|
||||
//! \note A delay is required after enabling the DAC. Further details
|
||||
//! regarding the exact delay time length can be found in the device datasheet.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
DAC_enableOutput(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Enable the output
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
HWREGH(base + DAC_O_OUTEN) |= DAC_OUTEN_DACOUTEN;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disable the DAC Output
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//!
|
||||
//! This function disables the DAC output.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
DAC_disableOutput(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Disable the output
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
HWREGH(base + DAC_O_OUTEN) &= ~DAC_OUTEN_DACOUTEN;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Set DAC Offset Trim
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//! \param offset is the specified value for the offset trim
|
||||
//!
|
||||
//! This function sets the DAC offset trim. The \e offset value should be a
|
||||
//! signed number in the range of -128 to 127.
|
||||
//!
|
||||
//! \note The offset should not be modified unless specifically indicated by
|
||||
//! TI Errata or other documentation. Modifying the offset value could cause
|
||||
//! this module to operate outside of the datasheet specifications.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
DAC_setOffsetTrim(uint32_t base, int16_t offset)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
ASSERT((offset > -129) && (offset < 128));
|
||||
|
||||
//
|
||||
// Set the offset trim value
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) &
|
||||
~DAC_TRIM_OFFSET_TRIM_M) | (int16_t)offset;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Get DAC Offset Trim
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//!
|
||||
//! This function gets the DAC offset trim value.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline int16_t
|
||||
DAC_getOffsetTrim(uint32_t base)
|
||||
{
|
||||
uint16_t value;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Get the sign-extended offset trim value
|
||||
//
|
||||
value = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M);
|
||||
value = ((value & (uint16_t)DAC_REG_BYTE_MASK) ^ (uint16_t)0x80) -
|
||||
(uint16_t)0x80;
|
||||
|
||||
return((int16_t)value);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Lock write-access to DAC Register
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//! \param reg is the selected DAC registers
|
||||
//!
|
||||
//! This function locks the write-access to the specified DAC register. Only a
|
||||
//! system reset can unlock the register once locked.
|
||||
//!
|
||||
//! The \e reg parameter can be an ORed combination of any of the following
|
||||
//! values:
|
||||
//! - \b DAC_LOCK_CONTROL - Lock the DAC control register
|
||||
//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register
|
||||
//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
DAC_lockRegister(uint32_t base, uint16_t reg)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW |
|
||||
DAC_LOCK_OUTPUT)) == 0U);
|
||||
|
||||
//
|
||||
// Lock the specified registers
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
HWREGH(base + DAC_O_LOCK) |= reg;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Check if DAC Register is locked
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//! \param reg is the selected DAC register locks to check
|
||||
//!
|
||||
//! This function checks if write-access has been locked on the specified DAC
|
||||
//! register.
|
||||
//!
|
||||
//! The \e reg parameter can be an ORed combination of any of the following
|
||||
//! values:
|
||||
//! - \b DAC_LOCK_CONTROL - Lock the DAC control register
|
||||
//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register
|
||||
//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register
|
||||
//!
|
||||
//! \return Returns \b true if any of the registers specified are locked, and
|
||||
//! \b false if all specified registers aren't locked.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline bool
|
||||
DAC_isRegisterLocked(uint32_t base, uint16_t reg)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DAC_isBaseValid(base));
|
||||
ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW |
|
||||
DAC_LOCK_OUTPUT)) == 0U);
|
||||
|
||||
//
|
||||
// Return the lock status on the specified registers
|
||||
//
|
||||
return((bool)((HWREGH(base + DAC_O_LOCK) & reg) != 0U));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Tune DAC Offset Trim
|
||||
//!
|
||||
//! \param base is the DAC module base address
|
||||
//! \param referenceVoltage is the reference voltage the DAC
|
||||
//! module is operating at.
|
||||
//!
|
||||
//! This function adjusts/tunes the DAC offset trim. The \e referenceVoltage
|
||||
//! value should be a floating point number in the range specified in the
|
||||
//! device data manual.
|
||||
//!
|
||||
//! \note Use this function to adjust the DAC offset trim if operating
|
||||
//! at a reference voltage other than 2.5v. Since this function modifies
|
||||
//! the DAC offset trim register, it should only be called once after
|
||||
//! Device_cal. If it is called multiple times after Device_cal, the offset
|
||||
//! value scaled would be the wrong value.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void
|
||||
DAC_tuneOffsetTrim(uint32_t base, float32_t referenceVoltage);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // DAC_H
|
|
@ -0,0 +1,375 @@
|
|||
//#############################################################################
|
||||
//
|
||||
// FILE: dcsm.c
|
||||
//
|
||||
// TITLE: C28x Driver for the DCSM security module.
|
||||
//
|
||||
//#############################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
#include "dcsm.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DCSM_unlockZone1CSM
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey)
|
||||
{
|
||||
uint32_t linkPointer;
|
||||
uint32_t zsbBase = (DCSM_Z1OTP_BASE + 0x20U); // base address of the ZSB
|
||||
int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer)
|
||||
int32_t zeroFound = 0;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(psCMDKey != NULL);
|
||||
|
||||
linkPointer = HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTER);
|
||||
|
||||
//
|
||||
// Bits 31 and 30 as most-significant 0 are invalid LinkPointer options
|
||||
//
|
||||
linkPointer = linkPointer << 3;
|
||||
|
||||
//
|
||||
// Zone-Select Block (ZSB) selection using Link-Pointers
|
||||
// and 0's bit position within the Link pointer
|
||||
//
|
||||
while((zeroFound == 0) && (bitPos > -1))
|
||||
{
|
||||
//
|
||||
// The most significant bit position in the resolved link pointer
|
||||
// which is 0, defines the valid base address for the ZSB.
|
||||
//
|
||||
if((linkPointer & 0x80000000U) == 0U)
|
||||
{
|
||||
zeroFound = 1;
|
||||
//
|
||||
// Base address of the ZSB is calculated using
|
||||
// 0x10 as the slope/step with which zsbBase expands with
|
||||
// change in the bitPos and 3*0x10 is the offset
|
||||
//
|
||||
zsbBase = (DCSM_Z1OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U));
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Move through the linkPointer to find the most significant
|
||||
// bit position of 0
|
||||
//
|
||||
bitPos--;
|
||||
linkPointer = linkPointer << 1;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Perform dummy reads on the 128-bit password
|
||||
// Using linkPointer because it is no longer needed
|
||||
//
|
||||
linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD0);
|
||||
linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD1);
|
||||
linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD2);
|
||||
linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD3);
|
||||
|
||||
if(psCMDKey != NULL)
|
||||
{
|
||||
HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY0) = psCMDKey->csmKey0;
|
||||
HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY1) = psCMDKey->csmKey1;
|
||||
HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY2) = psCMDKey->csmKey2;
|
||||
HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY3) = psCMDKey->csmKey3;
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DCSM_unlockZone2CSM
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey)
|
||||
{
|
||||
uint32_t linkPointer;
|
||||
uint32_t zsbBase = (DCSM_Z2OTP_BASE + 0x20U); // base address of the ZSB
|
||||
int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer)
|
||||
int32_t zeroFound = 0;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(psCMDKey != NULL);
|
||||
|
||||
linkPointer = HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTER);
|
||||
|
||||
//
|
||||
// Bits 31 and 30 as most-significant 0 are invalid LinkPointer options
|
||||
//
|
||||
linkPointer = linkPointer << 3;
|
||||
|
||||
//
|
||||
// Zone-Select Block (ZSB) selection using Link-Pointers
|
||||
// and 0's bit position within the Link pointer
|
||||
//
|
||||
while((zeroFound == 0) && (bitPos > -1))
|
||||
{
|
||||
//
|
||||
// The most significant bit position in the resolved link pointer
|
||||
// which is 0, defines the valid base address for the ZSB.
|
||||
//
|
||||
if((linkPointer & 0x80000000U) == 0U)
|
||||
{
|
||||
zeroFound = 1;
|
||||
//
|
||||
// Base address of the ZSB is calculated using
|
||||
// 0x10 as the slope/step with which zsbBase expands with
|
||||
// change in the bitPos and 3*0x10 is the offset
|
||||
//
|
||||
zsbBase = (DCSM_Z2OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U));
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Move through the linkPointer to find the most significant
|
||||
// bit position of 0
|
||||
//
|
||||
bitPos--;
|
||||
linkPointer = linkPointer << 1;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Perform dummy reads on the 128-bit password
|
||||
// Using linkPointer because it is no longer needed
|
||||
//
|
||||
linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD0);
|
||||
linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD1);
|
||||
linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD2);
|
||||
linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD3);
|
||||
|
||||
if(psCMDKey != NULL)
|
||||
{
|
||||
HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY0) = psCMDKey->csmKey0;
|
||||
HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY1) = psCMDKey->csmKey1;
|
||||
HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY2) = psCMDKey->csmKey2;
|
||||
HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY3) = psCMDKey->csmKey3;
|
||||
}
|
||||
}
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DCSM_getZone1FlashEXEStatus
|
||||
//
|
||||
//*****************************************************************************
|
||||
DCSM_EXEOnlyStatus
|
||||
DCSM_getZone1FlashEXEStatus(DCSM_Sector sector)
|
||||
{
|
||||
uint16_t regValue;
|
||||
DCSM_EXEOnlyStatus status;
|
||||
|
||||
//
|
||||
// Check if sector belongs to this zone
|
||||
//
|
||||
if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE1)
|
||||
{
|
||||
status = DCSM_INCORRECT_ZONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Get the EXE status register
|
||||
//
|
||||
regValue = HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYSECTR);
|
||||
//
|
||||
// Get the EXE status of the Flash Sector
|
||||
//
|
||||
status = (DCSM_EXEOnlyStatus)((uint16_t)
|
||||
((regValue >> (uint16_t)sector) &
|
||||
0x01U));
|
||||
}
|
||||
return(status);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DCSM_getZone1RAMEXEStatus
|
||||
//
|
||||
//*****************************************************************************
|
||||
DCSM_EXEOnlyStatus
|
||||
DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module)
|
||||
{
|
||||
ASSERT(module != DCSM_CLA);
|
||||
uint32_t status;
|
||||
|
||||
//
|
||||
// Check if module belongs to this zone
|
||||
//
|
||||
if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE1)
|
||||
{
|
||||
status = DCSM_INCORRECT_ZONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Get the EXE status of the RAM Module
|
||||
//
|
||||
status = (uint16_t)((HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYRAMR) >>
|
||||
(uint16_t)module) & 0x01U);
|
||||
}
|
||||
return((DCSM_EXEOnlyStatus)status);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DCSM_getZone2FlashEXEStatus
|
||||
//
|
||||
//*****************************************************************************
|
||||
DCSM_EXEOnlyStatus
|
||||
DCSM_getZone2FlashEXEStatus(DCSM_Sector sector)
|
||||
{
|
||||
uint16_t regValue;
|
||||
DCSM_EXEOnlyStatus status;
|
||||
|
||||
//
|
||||
// Check if sector belongs to this zone
|
||||
//
|
||||
if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE2)
|
||||
{
|
||||
status = DCSM_INCORRECT_ZONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Get the EXE status register
|
||||
//
|
||||
regValue = HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_EXEONLYSECTR);
|
||||
//
|
||||
// Get the EXE status of the Flash Sector
|
||||
//
|
||||
status = (DCSM_EXEOnlyStatus)((uint16_t)((regValue >>
|
||||
(uint16_t)sector) & 0x01U));
|
||||
}
|
||||
|
||||
return(status);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DCSM_getZone2RAMEXEStatus
|
||||
//
|
||||
//*****************************************************************************
|
||||
DCSM_EXEOnlyStatus
|
||||
DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module)
|
||||
{
|
||||
ASSERT(module != DCSM_CLA);
|
||||
uint32_t status;
|
||||
|
||||
//
|
||||
// Check if module belongs to this zone
|
||||
//
|
||||
if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE2)
|
||||
{
|
||||
status = DCSM_INCORRECT_ZONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Get the EXE status of the RAM Module
|
||||
//
|
||||
status = (uint16_t)((HWREGH(DCSM_Z2_BASE +
|
||||
DCSM_O_Z2_EXEONLYRAMR) >> (uint16_t)module) & 0x01U);
|
||||
}
|
||||
return((DCSM_EXEOnlyStatus)status);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DCSM_claimZoneSemaphore
|
||||
//
|
||||
//*****************************************************************************
|
||||
bool
|
||||
DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone)
|
||||
{
|
||||
//
|
||||
// FLSEM register address.
|
||||
//
|
||||
uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM;
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Write 0xA5 to the key and write the zone that is attempting to claim the
|
||||
// Flash Pump Semaphore to the semaphore bits.
|
||||
//
|
||||
HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S) |
|
||||
(uint16_t)zone;
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// If the calling function was unable to claim the zone semaphore, then
|
||||
// return false
|
||||
//
|
||||
return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == (uint16_t)zone) ?
|
||||
true : false);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DCSM_releaseZoneSemaphore
|
||||
//
|
||||
//*****************************************************************************
|
||||
bool
|
||||
DCSM_releaseZoneSemaphore(void)
|
||||
{
|
||||
//
|
||||
// FLSEM register address.
|
||||
//
|
||||
uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM;
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Write 0xA5 to the key and write the zone that is attempting to claim the
|
||||
// Flash Pump Semaphore to the semaphore bits.
|
||||
//
|
||||
HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S);
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// If the calling function was unable to release the zone semaphore, then
|
||||
// return false
|
||||
//
|
||||
return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == 0x0U) ? true : false);
|
||||
}
|
||||
|
|
@ -0,0 +1,667 @@
|
|||
//#############################################################################
|
||||
//
|
||||
// FILE: dcsm.h
|
||||
//
|
||||
// TITLE: C28x Driver for the DCSM security module.
|
||||
//
|
||||
//#############################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
#ifndef DCSM_H
|
||||
#define DCSM_H
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup dcsm_api DCSM
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_dcsm.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "inc/hw_memmap.h"
|
||||
#include "inc/hw_sysctl.h"
|
||||
#include "cpu.h"
|
||||
#include "debug.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for the unlockZone1CSM() and unlockZone2CSM().
|
||||
// These are not parameters for any function.
|
||||
// These are not intended for application code.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#define DCSM_O_Z1_CSMPSWD0 0x08U //!< Z1 CSMPSWD0 offset
|
||||
#define DCSM_O_Z1_CSMPSWD1 0x0AU //!< Z1 CSMPSWD1 offset
|
||||
#define DCSM_O_Z1_CSMPSWD2 0x0CU //!< Z1 CSMPSWD2 offset
|
||||
#define DCSM_O_Z1_CSMPSWD3 0x0EU //!< Z1 CSMPSWD3 offset
|
||||
#define DCSM_O_Z2_CSMPSWD0 0x08U //!< Z2 CSMPSWD0 offset
|
||||
#define DCSM_O_Z2_CSMPSWD1 0x0AU //!< Z2 CSMPSWD1 offset
|
||||
#define DCSM_O_Z2_CSMPSWD2 0x0CU //!< Z2 CSMPSWD2 offset
|
||||
#define DCSM_O_Z2_CSMPSWD3 0x0EU //!< Z2 CSMPSWD3 offset
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Register key defines.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLSEM_KEY 0xA5U //!< Zone semaphore key
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Data structures to hold password keys.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef struct
|
||||
{
|
||||
uint32_t csmKey0;
|
||||
uint32_t csmKey1;
|
||||
uint32_t csmKey2;
|
||||
uint32_t csmKey3;
|
||||
} DCSM_CSMPasswordKey;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values to distinguish the status of RAM or FLASH sectors. These values
|
||||
//! describe which zone the memory location belongs too.
|
||||
//! These values can be returned from DCSM_getRAMZone(),
|
||||
//! DCSM_getFlashSectorZone().
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
DCSM_MEMORY_INACCESSIBLE, //!< Inaccessible
|
||||
DCSM_MEMORY_ZONE1, //!< Zone 1
|
||||
DCSM_MEMORY_ZONE2, //!< Zone 2
|
||||
DCSM_MEMORY_FULL_ACCESS //!< Full access
|
||||
} DCSM_MemoryStatus;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values to pass to DCSM_claimZoneSemaphore(). These values are used
|
||||
//! to describe the zone that can write to Flash Wrapper registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
DCSM_FLSEM_ZONE1 = 0x01U, //!< Flash semaphore Zone 1
|
||||
DCSM_FLSEM_ZONE2 = 0x02U //!< Flash semaphore Zone 2
|
||||
} DCSM_SemaphoreZone;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values to distinguish the security status of the zones.
|
||||
//! These values can be returned from DCSM_getZone1CSMSecurityStatus(),
|
||||
//! DCSM_getZone2CSMSecurityStatus().
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
DCSM_STATUS_SECURE, //!< Secure
|
||||
DCSM_STATUS_UNSECURE, //!< Unsecure
|
||||
DCSM_STATUS_LOCKED, //!< Locked
|
||||
} DCSM_SecurityStatus;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values to distinguish the status of the Control Registers. These values
|
||||
// describe can be used with the return values of
|
||||
// DCSM_getZone1ControlStatus(), and DCSM_getZone2ControlStatus().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DCSM_ALLZERO 0x08U //!< CSM Passwords all zeros
|
||||
#define DCSM_ALLONE 0x10U //!< CSM Passwords all ones
|
||||
#define DCSM_UNSECURE 0x20U //!< Zone is secure/unsecure
|
||||
#define DCSM_ARMED 0x40U //!< CSM is armed
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values to decribe the EXEONLY Status.
|
||||
//! These values are returned from to DCSM_getZone1RAMEXEStatus(),
|
||||
//! DCSM_getZone2RAMEXEStatus(), DCSM_getZone1FlashEXEStatus(),
|
||||
//! DCSM_getZone2FlashEXEStatus().
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
DCSM_PROTECTED, //!< Protected
|
||||
DCSM_UNPROTECTED, //!< Unprotected
|
||||
DCSM_INCORRECT_ZONE //!< Incorrect Zone
|
||||
}DCSM_EXEOnlyStatus;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values to distinguish RAM Module.
|
||||
//! These values can be passed to DCSM_getZone1RAMEXEStatus()
|
||||
//! DCSM_getZone2RAMEXEStatus(), DCSM_getRAMZone().
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
//
|
||||
//C28x RAMs
|
||||
//
|
||||
DCSM_RAMLS0, //!< RAMLS0
|
||||
DCSM_RAMLS1, //!< RAMLS1
|
||||
DCSM_RAMLS2, //!< RAMLS2
|
||||
DCSM_RAMLS3, //!< RAMLS3
|
||||
DCSM_RAMLS4, //!< RAMLS4
|
||||
DCSM_RAMLS5, //!< RAMLS5
|
||||
DCSM_RAMD0, //!< RAMD0
|
||||
DCSM_RAMD1, //!< RAMD1
|
||||
DCSM_CLA = 14U //!<Offset of CLA field in in RAMSTAT divided by two
|
||||
} DCSM_RAMModule;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Values to distinguish Flash Sector.
|
||||
//! These values can be passed to DCSM_getZone1FlashEXEStatus()
|
||||
//! DCSM_getZone2FlashEXEStatus(), DCSM_getFlashSectorZone().
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
DCSM_SECTOR_A, //!< Sector A
|
||||
DCSM_SECTOR_B, //!< Sector B
|
||||
DCSM_SECTOR_C, //!< Sector C
|
||||
DCSM_SECTOR_D, //!< Sector D
|
||||
DCSM_SECTOR_E, //!< Sector E
|
||||
DCSM_SECTOR_F, //!< Sector F
|
||||
DCSM_SECTOR_G, //!< Sector G
|
||||
DCSM_SECTOR_H, //!< Sector H
|
||||
DCSM_SECTOR_I, //!< Sector I
|
||||
DCSM_SECTOR_J, //!< Sector J
|
||||
DCSM_SECTOR_K, //!< Sector K
|
||||
DCSM_SECTOR_L, //!< Sector L
|
||||
DCSM_SECTOR_M, //!< Sector M
|
||||
DCSM_SECTOR_N, //!< Sector N
|
||||
} DCSM_Sector;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DCSM functions
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Secures zone 1 by setting the FORCESEC bit of Z1_CR register
|
||||
//!
|
||||
//! This function resets the state of the zone. If the zone is unlocked,
|
||||
//! it will lock(secure) the zone and also reset all the bits in the
|
||||
//! Control Register.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
DCSM_secureZone1(void)
|
||||
{
|
||||
//
|
||||
// Write to the FORCESEC bit.
|
||||
//
|
||||
HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_CR)|= DCSM_Z1_CR_FORCESEC;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Secures zone 2 by setting the FORCESEC bit of Z2_CR register
|
||||
//!
|
||||
//! This function resets the state of the zone. If the zone is unlocked,
|
||||
//! it will lock(secure) the zone and also reset all the bits in the
|
||||
//! Control Register.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline void
|
||||
DCSM_secureZone2(void)
|
||||
{
|
||||
//
|
||||
// Write to the FORCESEC bit.
|
||||
//
|
||||
HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_CR)|= DCSM_Z2_CR_FORCESEC;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the CSM security status of zone 1
|
||||
//!
|
||||
//! This function returns the security status of zone 1 CSM
|
||||
//!
|
||||
//! \return Returns security status as an enumerated type DCSM_SecurityStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline DCSM_SecurityStatus
|
||||
DCSM_getZone1CSMSecurityStatus(void)
|
||||
{
|
||||
uint16_t status;
|
||||
DCSM_SecurityStatus returnStatus;
|
||||
status = HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_CR);
|
||||
|
||||
//
|
||||
// if ARMED bit is set and UNSECURED bit or ALLONE bit or both UNSECURED
|
||||
// and ALLONE bits are set then CSM is unsecured. Else it is secure.
|
||||
//
|
||||
if(((status & DCSM_Z1_CR_ARMED) != 0U) &&
|
||||
(((status & DCSM_Z1_CR_UNSECURE) != 0U) ||
|
||||
((status & DCSM_Z1_CR_ALLONE) != 0U )))
|
||||
{
|
||||
returnStatus = DCSM_STATUS_UNSECURE;
|
||||
}
|
||||
else if((status & DCSM_Z1_CR_ALLZERO) == DCSM_Z1_CR_ALLZERO)
|
||||
{
|
||||
returnStatus = DCSM_STATUS_LOCKED;
|
||||
}
|
||||
else
|
||||
{
|
||||
returnStatus = DCSM_STATUS_SECURE;
|
||||
}
|
||||
|
||||
return(returnStatus);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the CSM security status of zone 2
|
||||
//!
|
||||
//! This function returns the security status of zone 2 CSM
|
||||
//!
|
||||
//! \return Returns security status as an enumerated type DCSM_SecurityStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline DCSM_SecurityStatus
|
||||
DCSM_getZone2CSMSecurityStatus(void)
|
||||
{
|
||||
uint16_t status;
|
||||
DCSM_SecurityStatus returnStatus;
|
||||
status = HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_CR);
|
||||
|
||||
//
|
||||
// if ARMED bit is set and UNSECURED bit or ALLONE bit or both UNSECURED
|
||||
// and ALLONE bits are set then CSM is unsecured. Else it is secure.
|
||||
//
|
||||
if(((status & DCSM_Z2_CR_ARMED) != 0U) &&
|
||||
(((status & DCSM_Z2_CR_UNSECURE) != 0U) ||
|
||||
((status & DCSM_Z2_CR_ALLONE) != 0U )))
|
||||
{
|
||||
returnStatus = DCSM_STATUS_UNSECURE;
|
||||
}
|
||||
else if((status & DCSM_Z2_CR_ALLZERO) == DCSM_Z2_CR_ALLZERO)
|
||||
{
|
||||
returnStatus = DCSM_STATUS_LOCKED;
|
||||
}
|
||||
else
|
||||
{
|
||||
returnStatus = DCSM_STATUS_SECURE;
|
||||
}
|
||||
|
||||
return(returnStatus);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the Control Status of zone 1
|
||||
//!
|
||||
//! This function returns the Control Status of zone 1 CSM
|
||||
//!
|
||||
//! \return Returns the contents of the Control Register which can be
|
||||
//! used with provided defines.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline uint16_t
|
||||
DCSM_getZone1ControlStatus(void)
|
||||
{
|
||||
//
|
||||
// Return the contents of the CR register.
|
||||
//
|
||||
return(HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_CR));
|
||||
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the Control Status of zone 2
|
||||
//!
|
||||
//! This function returns the Control Status of zone 2 CSM
|
||||
//!
|
||||
//! \return Returns the contents of the Control Register which can be
|
||||
//! used with the provided defines.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline uint16_t
|
||||
DCSM_getZone2ControlStatus(void)
|
||||
{
|
||||
//
|
||||
// Return the contents of the CR register.
|
||||
//
|
||||
return(HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_CR));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the security zone a RAM section belongs to
|
||||
//!
|
||||
//! \param module is the RAM module value. Valid values are type DCSM_RAMModule
|
||||
//! C28x RAMs :
|
||||
//! - \b DCSM_RAMLS0
|
||||
//! - \b DCSM_RAMLS1
|
||||
//! - \b DCSM_RAMLS2
|
||||
//! - \b DCSM_RAMLS3
|
||||
//! - \b DCSM_RAMLS4
|
||||
//! - \b DCSM_RAMLS5
|
||||
//! - \b DCSM_RAMD0
|
||||
//! - \b DCSM_RAMD1
|
||||
//!
|
||||
//! This function returns the security zone a RAM section belongs to.
|
||||
//!
|
||||
//! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible,
|
||||
//! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if
|
||||
//! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section
|
||||
//! doesn't belong to any zone (or if the section is unsecure).
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline DCSM_MemoryStatus
|
||||
DCSM_getRAMZone(DCSM_RAMModule module)
|
||||
{
|
||||
uint16_t shift = (uint16_t)module * 2U;
|
||||
uint32_t ramStatus;
|
||||
//
|
||||
//Read the RAMSTAT register for the specific RAM Module.
|
||||
//
|
||||
ramStatus = ((HWREG(DCSMCOMMON_BASE + DCSM_O_RAMSTAT) >>
|
||||
shift) & 0x03U);
|
||||
return((DCSM_MemoryStatus)ramStatus);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the security zone a flash sector belongs to
|
||||
//!
|
||||
//! \param sector is the flash sector value. Use DCSM_Sector type.
|
||||
//!
|
||||
//! This function returns the security zone a flash sector belongs to.
|
||||
//!
|
||||
//! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible ,
|
||||
//! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if
|
||||
//! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section
|
||||
//! doesn't belong to any zone (or if the section is unsecure)..
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline DCSM_MemoryStatus
|
||||
DCSM_getFlashSectorZone(DCSM_Sector sector)
|
||||
{
|
||||
uint32_t sectStat;
|
||||
uint16_t shift;
|
||||
|
||||
//
|
||||
// Get the Sector status register for the specific bank
|
||||
//
|
||||
sectStat = HWREG(DCSMCOMMON_BASE + DCSM_O_SECTSTAT);
|
||||
shift = (uint16_t)sector * 2U;
|
||||
|
||||
//
|
||||
//Read the SECTSTAT register for the specific Flash Sector.
|
||||
//
|
||||
return((DCSM_MemoryStatus)((uint16_t)((sectStat >> shift) & 0x3U)));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Read Zone 1 Link Pointer Error
|
||||
//!
|
||||
//! A non-zero value indicates an error on the bit position that is set to 1.
|
||||
//!
|
||||
//! \return Returns the value of the Zone 1 Link Pointer error.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline uint32_t
|
||||
DCSM_getZone1LinkPointerError(void)
|
||||
{
|
||||
//
|
||||
// Return the LinkPointer Error for specific bank
|
||||
//
|
||||
return(HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTERERR));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Read Zone 2 Link Pointer Error
|
||||
//!
|
||||
//! A non-zero value indicates an error on the bit position that is set to 1.
|
||||
//!
|
||||
//! \return Returns the value of the Zone 2 Link Pointer error.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static inline uint32_t
|
||||
DCSM_getZone2LinkPointerError(void)
|
||||
{
|
||||
//
|
||||
// Return the LinkPointer Error for specific bank
|
||||
//
|
||||
return(HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTERERR));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unlocks Zone 1 CSM.
|
||||
//!
|
||||
//! \param psCMDKey is a pointer to the DCSM_CSMPasswordKey struct that has the
|
||||
//! CSM password for zone 1.
|
||||
//!
|
||||
//! This function unlocks the CSM password. It first reads the
|
||||
//! four password locations in the User OTP. If any of the password values is
|
||||
//! different from 0xFFFFFFFF, it unlocks the device by writing the provided
|
||||
//! passwords into CSM Key registers
|
||||
//!
|
||||
//! \return None.
|
||||
//!
|
||||
//! \note This function should not be called in an actual application,
|
||||
//! should only be used for once to program the OTP memory. Ensure flash data
|
||||
//! cache is disabled before calling this function(Flash_disableCache).
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void
|
||||
DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unlocks Zone 2 CSM.
|
||||
//!
|
||||
//! \param psCMDKey is a pointer to the CSMPSWDKEY that has the CSM
|
||||
//! password for zone 2.
|
||||
//!
|
||||
//! This function unlocks the CSM password. It first reads
|
||||
//! the four password locations in the User OTP. If any of the password values
|
||||
//! is different from 0xFFFFFFFF, it unlocks the device by writing the
|
||||
//! provided passwords into CSM Key registers
|
||||
//!
|
||||
//! \return None.
|
||||
//!
|
||||
//! \note This function should not be called in an actual application,
|
||||
//! should only be used for once to program the OTP memory. Ensure flash data
|
||||
//! cache is disabled before calling this function(Flash_disableCache).
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void
|
||||
DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey);
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the EXE-ONLY status of zone 1 for a flash sector
|
||||
//!
|
||||
//! \param sector is the flash sector value. Use DCSM_Sector type.
|
||||
//!
|
||||
//! This function takes in a valid sector value and returns the status of EXE
|
||||
//! ONLY security protection for the sector.
|
||||
//!
|
||||
//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected,
|
||||
//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected,
|
||||
//! DCSM_INCORRECT_ZONE if sector does not belong to this zone.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern DCSM_EXEOnlyStatus
|
||||
DCSM_getZone1FlashEXEStatus(DCSM_Sector sector);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the EXE-ONLY status of zone 1 for a RAM module
|
||||
//!
|
||||
//! \param module is the RAM module value. Valid values are type DCSM_RAMModule
|
||||
//! C28x RAMs :
|
||||
//! - \b DCSM_RAMLS0
|
||||
//! - \b DCSM_RAMLS1
|
||||
//! - \b DCSM_RAMLS2
|
||||
//! - \b DCSM_RAMLS3
|
||||
//! - \b DCSM_RAMLS4
|
||||
//! - \b DCSM_RAMLS5
|
||||
//! - \b DCSM_RAMD0
|
||||
//! - \b DCSM_RAMD1
|
||||
//!
|
||||
//! This function takes in a valid module value and returns the status of EXE
|
||||
//! ONLY security protection for that module. DCSM_CLA is an invalid module
|
||||
//! value. There is no EXE-ONLY available for DCSM_CLA.
|
||||
//!
|
||||
//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected,
|
||||
//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected,
|
||||
//! DCSM_INCORRECT_ZONE if module does not belong to this zone.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern DCSM_EXEOnlyStatus
|
||||
DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the EXE-ONLY status of zone 2 for a flash sector
|
||||
//!
|
||||
//! \param sector is the flash sector value. Use DCSM_Sector type.
|
||||
//!
|
||||
//! This function takes in a valid sector value and returns the status of EXE
|
||||
//! ONLY security protection for the sector.
|
||||
//!
|
||||
//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected,
|
||||
//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected,
|
||||
//! DCSM_INCORRECT_ZONE if sector does not belong to this zone.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern DCSM_EXEOnlyStatus
|
||||
DCSM_getZone2FlashEXEStatus(DCSM_Sector sector);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the EXE-ONLY status of zone 2 for a RAM module
|
||||
//!
|
||||
//! \param module is the RAM module value. Valid values are type DCSM_RAMModule
|
||||
//! C28x RAMs :
|
||||
//! - \b DCSM_RAMLS0
|
||||
//! - \b DCSM_RAMLS1
|
||||
//! - \b DCSM_RAMLS2
|
||||
//! - \b DCSM_RAMLS3
|
||||
//! - \b DCSM_RAMLS4
|
||||
//! - \b DCSM_RAMLS5
|
||||
//! - \b DCSM_RAMD0
|
||||
//! - \b DCSM_RAMD1
|
||||
//!
|
||||
//! This function takes in a valid module value and returns the status of EXE
|
||||
//! ONLY security protection for that module. DCSM_CLA is an invalid module
|
||||
//! value. There is no EXE-ONLY available for DCSM_CLA.
|
||||
//!
|
||||
//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected,
|
||||
//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected,
|
||||
//! DCSM_INCORRECT_ZONE if module does not belong to this zone.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern DCSM_EXEOnlyStatus
|
||||
DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Claims the zone semaphore which allows access to the Flash Wrapper register
|
||||
//! for that zone.
|
||||
//!
|
||||
//! \param zone is the zone which is trying to claim the semaphore which allows
|
||||
//! access to the Flash Wrapper registers.
|
||||
//!
|
||||
//! \return Returns true for a successful semaphore capture, false if it was
|
||||
//! unable to capture the semaphore.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern bool
|
||||
DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Releases the zone semaphore.
|
||||
//!
|
||||
//! \return Returns true if it was successful in releasing the zone semaphore
|
||||
//! and false if it was unsuccessful in releasing the zone semaphore.
|
||||
//!
|
||||
//! \note If the calling function is not in the right zone to be able
|
||||
//! to access this register, it will return a false.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern bool
|
||||
DCSM_releaseZoneSemaphore(void);
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // DCSM_H
|
|
@ -0,0 +1,89 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: debug.h
|
||||
//
|
||||
// TITLE: Assert definition macro for debug.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DEBUG_H
|
||||
#define DEBUG_H
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototype for the function that is called when an invalid argument is passed
|
||||
// to an API. This is only used when doing a DEBUG build. It is the
|
||||
// application's responsibility to define the __error__ function.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void __error__(const char *filename, uint32_t line);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The ASSERT macro, which does the actual assertion checking. Typically, this
|
||||
// will be for procedure arguments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef DEBUG
|
||||
#ifdef __TMS320C28XX__
|
||||
//
|
||||
// When called from C28x application
|
||||
//
|
||||
#define ASSERT(expr) do \
|
||||
{ \
|
||||
if(!(expr)) \
|
||||
{ \
|
||||
__error__(__FILE__, __LINE__); \
|
||||
} \
|
||||
} \
|
||||
while((_Bool)0)
|
||||
#else
|
||||
//
|
||||
// When called from CLA application. Update as needed.
|
||||
//
|
||||
#define ASSERT(expr) do \
|
||||
{ \
|
||||
if(!(expr)) \
|
||||
{ \
|
||||
__mdebugstop(); \
|
||||
} \
|
||||
} \
|
||||
while((_Bool)0)
|
||||
#endif
|
||||
#else
|
||||
#define ASSERT(expr)
|
||||
#endif
|
||||
|
||||
#endif // DEBUG_H
|
|
@ -0,0 +1,356 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: dma.c
|
||||
//
|
||||
// TITLE: C28x DMA driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "dma.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DMA_configAddresses
|
||||
//
|
||||
//*****************************************************************************
|
||||
void DMA_configAddresses(uint32_t base, const void *destAddr,
|
||||
const void *srcAddr)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DMA_isBaseValid(base));
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Set up SOURCE address.
|
||||
//
|
||||
HWREG(base + DMA_O_SRC_BEG_ADDR_SHADOW) = (uint32_t)srcAddr;
|
||||
HWREG(base + DMA_O_SRC_ADDR_SHADOW) = (uint32_t)srcAddr;
|
||||
|
||||
//
|
||||
// Set up DESTINATION address.
|
||||
//
|
||||
HWREG(base + DMA_O_DST_BEG_ADDR_SHADOW) = (uint32_t)destAddr;
|
||||
HWREG(base + DMA_O_DST_ADDR_SHADOW) = (uint32_t)destAddr;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DMA_configBurst
|
||||
//
|
||||
//*****************************************************************************
|
||||
void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep,
|
||||
int16_t destStep)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DMA_isBaseValid(base));
|
||||
ASSERT((size >= 1U) && (size <= 32U));
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Set up BURST registers.
|
||||
//
|
||||
HWREGH(base + DMA_O_BURST_SIZE) = size - 1U;
|
||||
HWREGH(base + DMA_O_SRC_BURST_STEP) = srcStep;
|
||||
HWREGH(base + DMA_O_DST_BURST_STEP) = destStep;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DMA_configTransfer
|
||||
//
|
||||
//*****************************************************************************
|
||||
void DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep,
|
||||
int16_t destStep)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DMA_isBaseValid(base));
|
||||
ASSERT(transferSize <= 0x10000U);
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Set up TRANSFER registers.
|
||||
//
|
||||
HWREGH(base + DMA_O_TRANSFER_SIZE) = (uint16_t)(transferSize - 1U);
|
||||
HWREGH(base + DMA_O_SRC_TRANSFER_STEP) = srcStep;
|
||||
HWREGH(base + DMA_O_DST_TRANSFER_STEP) = destStep;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DMA_configWrap
|
||||
//
|
||||
//*****************************************************************************
|
||||
void DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep,
|
||||
uint32_t destWrapSize, int16_t destStep)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DMA_isBaseValid(base));
|
||||
ASSERT((srcWrapSize <= 0x10000U) || (destWrapSize <= 0x10000U));
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Set up WRAP registers.
|
||||
//
|
||||
HWREGH(base + DMA_O_SRC_WRAP_SIZE) = (uint16_t)(srcWrapSize - 1U);
|
||||
HWREGH(base + DMA_O_SRC_WRAP_STEP) = srcStep;
|
||||
|
||||
HWREGH(base + DMA_O_DST_WRAP_SIZE) = (uint16_t)(destWrapSize - 1U);
|
||||
HWREGH(base + DMA_O_DST_WRAP_STEP) = destStep;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DMA_configMode
|
||||
//
|
||||
//*****************************************************************************
|
||||
void DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DMA_isBaseValid(base));
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Set up trigger selection in the CMA/CLA trigger source selection
|
||||
// registers. These are considered part of system control.
|
||||
//
|
||||
switch(base)
|
||||
{
|
||||
case DMA_CH1_BASE:
|
||||
//
|
||||
// Channel 1
|
||||
//
|
||||
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) =
|
||||
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) &
|
||||
~((uint32_t)SYSCTL_DMACHSRCSEL1_CH1_M)) |
|
||||
((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH1_S);
|
||||
|
||||
//
|
||||
// Set peripheral interrupt select bits to the channel number.
|
||||
//
|
||||
HWREGH(DMA_CH1_BASE + DMA_O_MODE) =
|
||||
(HWREGH(DMA_CH1_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 1U;
|
||||
break;
|
||||
|
||||
case DMA_CH2_BASE:
|
||||
//
|
||||
// Channel 2
|
||||
//
|
||||
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) =
|
||||
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) &
|
||||
~((uint32_t)SYSCTL_DMACHSRCSEL1_CH2_M)) |
|
||||
((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH2_S);
|
||||
|
||||
//
|
||||
// Set peripheral interrupt select bits to the channel number.
|
||||
//
|
||||
HWREGH(DMA_CH2_BASE + DMA_O_MODE) =
|
||||
(HWREGH(DMA_CH2_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 2U;
|
||||
break;
|
||||
|
||||
case DMA_CH3_BASE:
|
||||
//
|
||||
// Channel 3
|
||||
//
|
||||
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) =
|
||||
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) &
|
||||
~((uint32_t)SYSCTL_DMACHSRCSEL1_CH3_M)) |
|
||||
((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH3_S);
|
||||
|
||||
//
|
||||
// Set peripheral interrupt select bits to the channel number.
|
||||
//
|
||||
HWREGH(DMA_CH3_BASE + DMA_O_MODE) =
|
||||
(HWREGH(DMA_CH3_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 3U;
|
||||
break;
|
||||
|
||||
case DMA_CH4_BASE:
|
||||
//
|
||||
// Channel 4
|
||||
//
|
||||
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) =
|
||||
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) &
|
||||
~((uint32_t)SYSCTL_DMACHSRCSEL1_CH4_M)) |
|
||||
((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH4_S);
|
||||
|
||||
//
|
||||
// Set peripheral interrupt select bits to the channel number.
|
||||
//
|
||||
HWREGH(DMA_CH4_BASE + DMA_O_MODE) =
|
||||
(HWREGH(DMA_CH4_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 4U;
|
||||
break;
|
||||
|
||||
case DMA_CH5_BASE:
|
||||
//
|
||||
// Channel 5
|
||||
//
|
||||
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) =
|
||||
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) &
|
||||
~((uint32_t)SYSCTL_DMACHSRCSEL2_CH5_M)) |
|
||||
((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH5_S);
|
||||
|
||||
//
|
||||
// Set peripheral interrupt select bits to the channel number.
|
||||
//
|
||||
HWREGH(DMA_CH5_BASE + DMA_O_MODE) =
|
||||
(HWREGH(DMA_CH5_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 5U;
|
||||
break;
|
||||
|
||||
case DMA_CH6_BASE:
|
||||
//
|
||||
// Channel 6
|
||||
//
|
||||
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) =
|
||||
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) &
|
||||
~((uint32_t)SYSCTL_DMACHSRCSEL2_CH6_M)) |
|
||||
((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH6_S);
|
||||
|
||||
//
|
||||
// Set peripheral interrupt select bits to the channel number.
|
||||
//
|
||||
HWREGH(DMA_CH6_BASE + DMA_O_MODE) =
|
||||
(HWREGH(DMA_CH6_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 6U;
|
||||
break;
|
||||
|
||||
default:
|
||||
//
|
||||
// Invalid base.
|
||||
//
|
||||
break;
|
||||
}
|
||||
|
||||
//
|
||||
// Write the configuration to the mode register.
|
||||
//
|
||||
HWREGH(base + DMA_O_MODE) &= ~(DMA_MODE_DATASIZE | DMA_MODE_CONTINUOUS |
|
||||
DMA_MODE_ONESHOT);
|
||||
HWREGH(base + DMA_O_MODE) |= config;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DMA_configChannel
|
||||
//
|
||||
//*****************************************************************************
|
||||
void DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(DMA_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Configure DMA Channel
|
||||
//
|
||||
DMA_configAddresses(base, (const void *)transfParams->destAddr,
|
||||
(const void *)transfParams->srcAddr);
|
||||
|
||||
//
|
||||
// Configure the size of each burst and the address step size
|
||||
//
|
||||
DMA_configBurst(base, transfParams->burstSize, transfParams->srcBurstStep,
|
||||
transfParams->destBurstStep);
|
||||
|
||||
//
|
||||
// Configure the transfer size and the address step that is
|
||||
// made after each burst.
|
||||
//
|
||||
DMA_configTransfer(base, transfParams->transferSize,
|
||||
transfParams->srcTransferStep,
|
||||
transfParams->destTransferStep);
|
||||
|
||||
//
|
||||
// Configure the DMA channel's wrap settings
|
||||
//
|
||||
DMA_configWrap(base, transfParams->srcWrapSize, transfParams->srcWrapStep,
|
||||
transfParams->destWrapSize, transfParams->destWrapStep);
|
||||
|
||||
//
|
||||
// Configure the DMA channel's trigger and mode
|
||||
//
|
||||
DMA_configMode(base, transfParams->transferTrigger,
|
||||
transfParams->transferMode | transfParams->reinitMode |
|
||||
transfParams->configSize);
|
||||
|
||||
//
|
||||
// Enable the selected peripheral trigger to start a DMA transfer
|
||||
//
|
||||
DMA_enableTrigger(base);
|
||||
|
||||
if(transfParams->enableInterrupt)
|
||||
{
|
||||
//
|
||||
// Set the channel interrupt mode
|
||||
//
|
||||
DMA_setInterruptMode(base, transfParams->interruptMode);
|
||||
|
||||
//
|
||||
// Enable the indicated DMA channel interrupt source
|
||||
//
|
||||
DMA_enableInterrupt(base);
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Disable the indicated DMA channel interrupt source
|
||||
//
|
||||
DMA_disableInterrupt(base);
|
||||
}
|
||||
}
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,109 @@
|
|||
#ifndef DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_
|
||||
#define DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// CLB
|
||||
//*****************************************************************************
|
||||
#define CLB_LOCAL_IN_MUX_SPISIMO_SLAVE CLB_LOCAL_IN_MUX_SPIPICO_PERIPHERAL
|
||||
#define CLB_LOCAL_IN_MUX_SPISIMO_MASTER CLB_LOCAL_IN_MUX_SPIPICO_CONTROLLER
|
||||
#define CLB_GLOBAL_IN_MUX_SPI1_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI1_SPIPOCI_CONTROLLER
|
||||
#define CLB_GLOBAL_IN_MUX_SPI1_SPISTE CLB_GLOBAL_IN_MUX_SPI1_SPIPTE
|
||||
#define CLB_GLOBAL_IN_MUX_SPI2_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI2_SPIPOCI_CONTROLLER
|
||||
#define CLB_GLOBAL_IN_MUX_SPI2_SPISTE CLB_GLOBAL_IN_MUX_SPI2_SPIPTE
|
||||
#define CLB_GLOBAL_IN_MUX_SPI3_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI3_SPIPOCI_CONTROLLER
|
||||
#define CLB_GLOBAL_IN_MUX_SPI3_SPISTE CLB_GLOBAL_IN_MUX_SPI3_SPIPTE
|
||||
#define CLB_GLOBAL_IN_MUX_SPI4_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI4_SPIPOCI_CONTROLLER
|
||||
#define CLB_GLOBAL_IN_MUX_SPI4_SPISTE CLB_GLOBAL_IN_MUX_SPI4_SPIPTE
|
||||
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// SPI
|
||||
//*****************************************************************************
|
||||
#define SPI_MODE_SLAVE SPI_MODE_PERIPHERAL
|
||||
#define SPI_MODE_MASTER SPI_MODE_CONTROLLER
|
||||
#define SPI_MODE_SLAVE_OD SPI_MODE_PERIPHERAL_OD
|
||||
#define SPI_MODE_MASTER_OD SPI_MODE_CONTROLLER_OD
|
||||
|
||||
#define SPI_STE_ACTIVE_LOW SPI_PTE_ACTIVE_LOW
|
||||
#define SPI_STE_ACTIVE_HIGH SPI_PTE_ACTIVE_HIGH
|
||||
|
||||
#define SPI_setSTESignalPolarity SPI_setPTESignalPolarity
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// Interrupt
|
||||
//*****************************************************************************
|
||||
#define Interrupt_enableMaster Interrupt_enableGlobal
|
||||
#define Interrupt_disableMaster Interrupt_disableGlobal
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// SysCtrl
|
||||
//*****************************************************************************
|
||||
#define SysCtl_AccessMaster SysCtl_AccessController
|
||||
#define SYSCTL_SEC_MASTER_CLA SYSCTL_SEC_CONTROLLER_CLA
|
||||
#define SYSCTL_SEC_MASTER_DMA SYSCTL_SEC_CONTROLLER_DMA
|
||||
#define SysCtl_selectSecMaster SysCtl_selectSecController
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// GPIO
|
||||
//*****************************************************************************
|
||||
#define GPIO_setMasterCore GPIO_setControllerCore
|
||||
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// Memcfg
|
||||
//*****************************************************************************
|
||||
#define MemCfg_LSRAMMMasterSel MemCfg_LSRAMMControllerSel
|
||||
#define MEMCFG_LSRAMMASTER_CPU_ONLY MEMCFG_LSRAMCONTROLLER_CPU_ONLY
|
||||
#define MEMCFG_LSRAMMASTER_CPU_CLA1 MEMCFG_LSRAMCONTROLLER_CPU_CLA1
|
||||
#define MemCfg_setLSRAMMasterSel MemCfg_setLSRAMControllerSel
|
||||
|
||||
#define MemCfg_GSRAMMasterSel MemCfg_GSRAMControllerSel
|
||||
#define MEMCFG_GSRAMMASTER_CPU1 MEMCFG_GSRAMCONTROLLER_CPU1
|
||||
#define MEMCFG_GSRAMMASTER_CPU2 MEMCFG_GSRAMCONTROLLER_CPU2
|
||||
#define MemCfg_setGSRAMMasterSel MemCfg_setGSRAMControllerSel
|
||||
|
||||
//*****************************************************************************
|
||||
// EMIF
|
||||
//*****************************************************************************
|
||||
#define EMIF_MasterSelect EMIF_ControllerSelect
|
||||
#define EMIF_selectMaster EMIF_selectController
|
||||
#define EMIF_MASTER_CPU1_NG EMIF_CONTROLLER_CPU1_NG
|
||||
#define EMIF_MASTER_CPU1_G EMIF_CONTROLLER_CPU1_G
|
||||
#define EMIF_MASTER_CPU2_G EMIF_CONTROLLER_CPU2_G
|
||||
#define EMIF_MASTER_CPU1_NG2 EMIF_CONTROLLER_CPU1_NG2
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// I2C
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_SEND_MODE I2C_CONTROLLER_SEND_MODE
|
||||
#define I2C_MASTER_RECEIVE_MODE I2C_CONTROLLER_RECEIVE_MODE
|
||||
#define I2C_SLAVE_SEND_MODE I2C_TARGET_SEND_MODE
|
||||
#define I2C_SLAVE_RECEIVE_MODE I2C_TARGET_RECEIVE_MODE
|
||||
#define I2C_INT_ADDR_SLAVE I2C_INT_ADDR_TARGET
|
||||
#define I2C_STS_ADDR_SLAVE I2C_STS_ADDR_TARGET
|
||||
#define I2C_STS_SLAVE_DIR I2C_STS_TARGET_DIR
|
||||
#define I2C_INTSRC_ADDR_SLAVE I2C_INTSRC_ADDR_TARGET
|
||||
|
||||
#define I2C_initMaster I2C_initController
|
||||
#define I2C_setSlaveAddress I2C_setTargetAddress
|
||||
#define I2C_setOwnSlaveAddress I2C_setOwnAddress
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// SDFM
|
||||
//*****************************************************************************
|
||||
#define SDFM_enableMasterInterrupt SDFM_enableMainInterrupt
|
||||
#define SDFM_disableMasterInterrupt SDFM_disableMainInterrupt
|
||||
#define SDFM_enableMasterFilter SDFM_enableMainFilter
|
||||
#define SDFM_disableMasterFilter SDFM_disableMainFilter
|
||||
|
||||
#define SDFM_MASTER_INTERRUPT_FLAG SDFM_MAIN_INTERRUPT_FLAG
|
||||
|
||||
#endif /* DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ */
|
|
@ -0,0 +1,59 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: ecap.c
|
||||
//
|
||||
// TITLE: C28x ECAP driver
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "ecap.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// ECAP_setEmulationMode
|
||||
//
|
||||
//*****************************************************************************
|
||||
void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode)
|
||||
{
|
||||
ASSERT(ECAP_isBaseValid(base));
|
||||
|
||||
|
||||
//
|
||||
// Write to FREE/SOFT bit
|
||||
//
|
||||
HWREGH(base + ECAP_O_ECCTL1) =
|
||||
((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_FREE_SOFT_M)) |
|
||||
((uint16_t)mode << ECAP_ECCTL1_FREE_SOFT_S));
|
||||
}
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,44 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: emif.c
|
||||
//
|
||||
// TITLE: C28x EMIF driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "emif.h"
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,361 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: epwm.c
|
||||
//
|
||||
// TITLE: C28x EPWM driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "epwm.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// EPWM_setEmulationMode
|
||||
//
|
||||
//*****************************************************************************
|
||||
void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(EPWM_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Write to FREE_SOFT bits
|
||||
//
|
||||
HWREGH(base + EPWM_O_TBCTL) =
|
||||
((HWREGH(base + EPWM_O_TBCTL) & (~EPWM_TBCTL_FREE_SOFT_M)) |
|
||||
((uint16_t)emulationMode << EPWM_TBCTL_FREE_SOFT_S));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// EPWM_configureSignal
|
||||
//
|
||||
//*****************************************************************************
|
||||
void EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams)
|
||||
{
|
||||
float32_t tbClkInHz = 0.0F;
|
||||
uint16_t tbPrdVal = 0U, cmpAVal = 0U, cmpBVal = 0U;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(EPWM_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Valid values in the function for TBCTR Mode are UP, DOWN
|
||||
// and UP-DOWN count.
|
||||
//
|
||||
ASSERT((uint16_t)signalParams->tbCtrMode <= 2U);
|
||||
|
||||
//
|
||||
// Configure EPWM clock Divider
|
||||
//
|
||||
SysCtl_setEPWMClockDivider(signalParams->epwmClkDiv);
|
||||
|
||||
//
|
||||
// Configure Time Base counter Clock
|
||||
//
|
||||
EPWM_setClockPrescaler(base, signalParams->tbClkDiv,
|
||||
signalParams->tbHSClkDiv);
|
||||
|
||||
//
|
||||
// Configure Time Base Counter Mode
|
||||
//
|
||||
EPWM_setTimeBaseCounterMode(base, signalParams->tbCtrMode);
|
||||
|
||||
//
|
||||
// Calculate TBCLK, TBPRD and CMPx values to be configured for
|
||||
// achieving desired signal
|
||||
//
|
||||
tbClkInHz = ((float32_t)signalParams->sysClkInHz /
|
||||
(float32_t)(1U << ((uint16_t)signalParams->epwmClkDiv +
|
||||
(uint16_t)signalParams->tbClkDiv)));
|
||||
|
||||
if(signalParams->tbHSClkDiv <= EPWM_HSCLOCK_DIVIDER_4)
|
||||
{
|
||||
tbClkInHz /= (float32_t)(1U << (uint16_t)signalParams->tbHSClkDiv);
|
||||
}
|
||||
else
|
||||
{
|
||||
tbClkInHz /= (float32_t)(2U * (uint16_t)signalParams->tbHSClkDiv);
|
||||
}
|
||||
|
||||
if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP)
|
||||
{
|
||||
tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f);
|
||||
cmpAVal = (uint16_t)(signalParams->dutyValA *
|
||||
(float32_t)(tbPrdVal + 1U));
|
||||
cmpBVal = (uint16_t)(signalParams->dutyValB *
|
||||
(float32_t)(tbPrdVal + 1U));
|
||||
}
|
||||
else if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN)
|
||||
{
|
||||
tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f);
|
||||
cmpAVal = (uint16_t)((float32_t)(tbPrdVal + 1U) -
|
||||
(signalParams->dutyValA * (float32_t)(tbPrdVal + 1U)));
|
||||
cmpBVal = (uint16_t)((float32_t)(tbPrdVal + 1U) -
|
||||
(signalParams->dutyValB * (float32_t)(tbPrdVal + 1U)));
|
||||
}
|
||||
else
|
||||
{
|
||||
tbPrdVal = (uint16_t)(tbClkInHz / (2.0f * signalParams->freqInHz));
|
||||
cmpAVal = (uint16_t)(((float32_t)tbPrdVal -
|
||||
((signalParams->dutyValA *
|
||||
(float32_t)tbPrdVal))) + 0.5f);
|
||||
cmpBVal = (uint16_t)(((float32_t)tbPrdVal -
|
||||
((signalParams->dutyValB *
|
||||
(float32_t)tbPrdVal))) + 0.5f);
|
||||
}
|
||||
|
||||
//
|
||||
// Configure TBPRD value
|
||||
//
|
||||
EPWM_setTimeBasePeriod(base, tbPrdVal);
|
||||
|
||||
//
|
||||
// Default Configurations.
|
||||
//
|
||||
EPWM_disablePhaseShiftLoad(base);
|
||||
EPWM_setPhaseShift(base, 0U);
|
||||
EPWM_setTimeBaseCounter(base, 0U);
|
||||
|
||||
//
|
||||
// Setup shadow register load on ZERO
|
||||
//
|
||||
EPWM_setCounterCompareShadowLoadMode(base,
|
||||
EPWM_COUNTER_COMPARE_A,
|
||||
EPWM_COMP_LOAD_ON_CNTR_ZERO);
|
||||
EPWM_setCounterCompareShadowLoadMode(base,
|
||||
EPWM_COUNTER_COMPARE_B,
|
||||
EPWM_COMP_LOAD_ON_CNTR_ZERO);
|
||||
//
|
||||
// Set Compare values
|
||||
//
|
||||
EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A,
|
||||
cmpAVal);
|
||||
EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B,
|
||||
cmpBVal);
|
||||
|
||||
//
|
||||
// Set actions for ePWMxA & ePWMxB
|
||||
//
|
||||
if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP)
|
||||
{
|
||||
//
|
||||
// Set PWMxA on Zero
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_A,
|
||||
EPWM_AQ_OUTPUT_HIGH,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
|
||||
|
||||
//
|
||||
// Clear PWMxA on event A, up count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_A,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
|
||||
|
||||
if(signalParams->invertSignalB == true)
|
||||
{
|
||||
//
|
||||
// Clear PWMxB on Zero
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
|
||||
//
|
||||
// Set PWMxB on event B, up count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_HIGH,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Set PWMxB on Zero
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_HIGH,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
|
||||
//
|
||||
// Clear PWMxB on event B, up count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
|
||||
|
||||
}
|
||||
}
|
||||
else if((signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN))
|
||||
{
|
||||
//
|
||||
// Set PWMxA on Zero
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_A,
|
||||
EPWM_AQ_OUTPUT_HIGH,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
|
||||
|
||||
//
|
||||
// Clear PWMxA on event A, down count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_A,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
|
||||
|
||||
if(signalParams->invertSignalB == true)
|
||||
{
|
||||
//
|
||||
// Clear PWMxB on Zero
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
|
||||
//
|
||||
// Set PWMxB on event B, down count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_HIGH,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Set PWMxB on Zero
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_HIGH,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
|
||||
//
|
||||
// Clear PWMxB on event B, down count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Clear PWMxA on Zero
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_A,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
|
||||
|
||||
//
|
||||
// Set PWMxA on event A, up count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_A,
|
||||
EPWM_AQ_OUTPUT_HIGH,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
|
||||
|
||||
//
|
||||
// Clear PWMxA on event A, down count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_A,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
|
||||
|
||||
if(signalParams->invertSignalB == true)
|
||||
{
|
||||
//
|
||||
// Set PWMxB on Zero
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_HIGH,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
|
||||
|
||||
//
|
||||
// Clear PWMxB on event B, up count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
|
||||
//
|
||||
// Set PWMxB on event B, down count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_HIGH,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Clear PWMxB on Zero
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
|
||||
|
||||
//
|
||||
// Set PWMxB on event B, up count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_HIGH,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
|
||||
//
|
||||
// Clear PWMxB on event B, down count
|
||||
//
|
||||
EPWM_setActionQualifierAction(base,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,147 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: eqep.c
|
||||
//
|
||||
// TITLE: C28x eQEP driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "eqep.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// EQEP_setCompareConfig
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue,
|
||||
uint16_t cycles)
|
||||
{
|
||||
uint16_t regValue;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(EQEP_isBaseValid(base));
|
||||
ASSERT(cycles <= (EQEP_QPOSCTL_PCSPW_M + 1U));
|
||||
|
||||
//
|
||||
// Set the compare match value
|
||||
//
|
||||
HWREG(base + EQEP_O_QPOSCMP) = compareValue;
|
||||
|
||||
//
|
||||
// Set the shadow register settings and pulse width.
|
||||
//
|
||||
regValue = (config & (uint16_t)(EQEP_QPOSCTL_PCSHDW |
|
||||
EQEP_QPOSCTL_PCLOAD)) | (cycles - 1U);
|
||||
|
||||
HWREGH(base + EQEP_O_QPOSCTL) = (HWREGH(base + EQEP_O_QPOSCTL) &
|
||||
~(EQEP_QPOSCTL_PCSPW_M |
|
||||
EQEP_QPOSCTL_PCLOAD |
|
||||
EQEP_QPOSCTL_PCSHDW)) | regValue;
|
||||
|
||||
//
|
||||
// Set position compare sync-output mode.
|
||||
//
|
||||
regValue = config & (uint16_t)(EQEP_QDECCTL_SOEN | EQEP_QDECCTL_SPSEL);
|
||||
|
||||
HWREGH(base + EQEP_O_QDECCTL) = (HWREGH(base + EQEP_O_QDECCTL) &
|
||||
~(EQEP_QDECCTL_SOEN |
|
||||
EQEP_QDECCTL_SPSEL)) | regValue;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// EQEP_setInputPolarity
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB,
|
||||
bool invertIndex, bool invertStrobe)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(EQEP_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Configure QEPA signal
|
||||
//
|
||||
if(invertQEPA)
|
||||
{
|
||||
HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QAP;
|
||||
}
|
||||
else
|
||||
{
|
||||
HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QAP;
|
||||
}
|
||||
|
||||
//
|
||||
// Configure QEPB signal
|
||||
//
|
||||
if(invertQEPB)
|
||||
{
|
||||
HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QBP;
|
||||
}
|
||||
else
|
||||
{
|
||||
HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QBP;
|
||||
}
|
||||
|
||||
//
|
||||
// Configure index signal
|
||||
//
|
||||
if(invertIndex)
|
||||
{
|
||||
HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QIP;
|
||||
}
|
||||
else
|
||||
{
|
||||
HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QIP;
|
||||
}
|
||||
|
||||
//
|
||||
// Configure strobe signal
|
||||
//
|
||||
if(invertStrobe)
|
||||
{
|
||||
HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QSP;
|
||||
}
|
||||
else
|
||||
{
|
||||
HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QSP;
|
||||
}
|
||||
}
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,173 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: flash.c
|
||||
//
|
||||
// TITLE: C28x Flash driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "flash.h"
|
||||
|
||||
#ifndef __cplusplus
|
||||
#pragma CODE_SECTION(Flash_initModule, ".TI.ramfunc");
|
||||
#pragma CODE_SECTION(Flash_powerDown, ".TI.ramfunc");
|
||||
#pragma CODE_SECTION(Flash_wakeFromLPM, ".TI.ramfunc");
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Flash_initModule
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
#pragma CODE_SECTION(".TI.ramfunc");
|
||||
#endif
|
||||
void
|
||||
Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(Flash_isCtrlBaseValid(ctrlBase));
|
||||
ASSERT(Flash_isECCBaseValid(eccBase));
|
||||
ASSERT(waitstates <= 0xFU);
|
||||
|
||||
//
|
||||
// Set the bank power up delay so that the bank will power up properly.
|
||||
//
|
||||
Flash_setBankPowerUpDelay(ctrlBase, 0x14);
|
||||
|
||||
//
|
||||
// Set the bank fallback power mode to active.
|
||||
//
|
||||
Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE);
|
||||
|
||||
//
|
||||
// Power up flash bank and pump and this also sets the fall back mode of
|
||||
// flash and pump as active
|
||||
//
|
||||
Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE);
|
||||
|
||||
//
|
||||
// Disable cache and prefetch mechanism before changing wait states
|
||||
//
|
||||
Flash_disableCache(ctrlBase);
|
||||
Flash_disablePrefetch(ctrlBase);
|
||||
|
||||
//
|
||||
// Set waitstates according to frequency.
|
||||
//
|
||||
Flash_setWaitstates(ctrlBase, waitstates);
|
||||
|
||||
|
||||
//
|
||||
// Enable cache and prefetch mechanism to improve performance of code
|
||||
// executed from flash.
|
||||
//
|
||||
Flash_enableCache(ctrlBase);
|
||||
Flash_enablePrefetch(ctrlBase);
|
||||
|
||||
//
|
||||
// At reset, ECC is enabled. If it is disabled by application software and
|
||||
// if application again wants to enable ECC.
|
||||
//
|
||||
Flash_enableECC(eccBase);
|
||||
|
||||
//
|
||||
// Force a pipeline flush to ensure that the write to the last register
|
||||
// configured occurs before returning.
|
||||
//
|
||||
|
||||
FLASH_DELAY_CONFIG;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Flash_powerDown
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
#pragma CODE_SECTION(".TI.ramfunc");
|
||||
#endif
|
||||
void
|
||||
Flash_powerDown(uint32_t ctrlBase)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(Flash_isCtrlBaseValid(ctrlBase));
|
||||
|
||||
//
|
||||
// Set the bank power up delay so that it will power up properly.
|
||||
//
|
||||
Flash_setBankPowerUpDelay(ctrlBase, 0x14);
|
||||
|
||||
//
|
||||
// Power down the flash bank.
|
||||
//
|
||||
Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_SLEEP);
|
||||
|
||||
//
|
||||
// Power down the flash pump.
|
||||
//
|
||||
Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_SLEEP);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Flash_wakeFromLPM
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
#pragma CODE_SECTION(".TI.ramfunc");
|
||||
#endif
|
||||
void
|
||||
Flash_wakeFromLPM(uint32_t ctrlBase)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(Flash_isCtrlBaseValid(ctrlBase));
|
||||
|
||||
//
|
||||
// Set the bank fallback power modes to active.
|
||||
//
|
||||
Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE);
|
||||
|
||||
//
|
||||
// Set the flash pump power mode to active.
|
||||
//
|
||||
Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE);
|
||||
}
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,487 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: gpio.c
|
||||
//
|
||||
// TITLE: C28x GPIO driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "gpio.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO_setDirectionMode
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO)
|
||||
{
|
||||
volatile uint32_t *gpioBaseAddr;
|
||||
uint32_t pinMask;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(GPIO_isPinValid(pin));
|
||||
|
||||
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
|
||||
((pin / 32U) * GPIO_CTRL_REGS_STEP);
|
||||
pinMask = (uint32_t)1U << (pin % 32U);
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Set the data direction
|
||||
//
|
||||
if(pinIO == GPIO_DIR_MODE_OUT)
|
||||
{
|
||||
//
|
||||
// Output
|
||||
//
|
||||
gpioBaseAddr[GPIO_GPxDIR_INDEX] |= pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Input
|
||||
//
|
||||
gpioBaseAddr[GPIO_GPxDIR_INDEX] &= ~pinMask;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO_getDirectionMode
|
||||
//
|
||||
//*****************************************************************************
|
||||
GPIO_Direction
|
||||
GPIO_getDirectionMode(uint32_t pin)
|
||||
{
|
||||
volatile uint32_t *gpioBaseAddr;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(GPIO_isPinValid(pin));
|
||||
|
||||
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
|
||||
((pin / 32U) * GPIO_CTRL_REGS_STEP);
|
||||
|
||||
return((GPIO_Direction)((uint32_t)((gpioBaseAddr[GPIO_GPxDIR_INDEX] >>
|
||||
(pin % 32U)) & 1U)));
|
||||
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO_setInterruptPin
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum)
|
||||
{
|
||||
XBAR_InputNum input;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(GPIO_isPinValid(pin));
|
||||
|
||||
//
|
||||
// Pick the X-BAR input that corresponds to the requested XINT.
|
||||
//
|
||||
switch(extIntNum)
|
||||
{
|
||||
case GPIO_INT_XINT1:
|
||||
input = XBAR_INPUT4;
|
||||
break;
|
||||
|
||||
case GPIO_INT_XINT2:
|
||||
input = XBAR_INPUT5;
|
||||
break;
|
||||
|
||||
case GPIO_INT_XINT3:
|
||||
input = XBAR_INPUT6;
|
||||
break;
|
||||
|
||||
case GPIO_INT_XINT4:
|
||||
input = XBAR_INPUT13;
|
||||
break;
|
||||
|
||||
case GPIO_INT_XINT5:
|
||||
input = XBAR_INPUT14;
|
||||
break;
|
||||
|
||||
default:
|
||||
//
|
||||
// Invalid interrupt. Shouldn't happen if enum value is used.
|
||||
// XBAR_INPUT1 isn't tied to an XINT, so we'll use it to check for
|
||||
// a bad value.
|
||||
//
|
||||
input = XBAR_INPUT1;
|
||||
break;
|
||||
}
|
||||
|
||||
if(input != XBAR_INPUT1)
|
||||
{
|
||||
XBAR_setInputPin(input, (uint16_t)pin);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO_setPadConfig
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
GPIO_setPadConfig(uint32_t pin, uint32_t pinType)
|
||||
{
|
||||
volatile uint32_t *gpioBaseAddr;
|
||||
uint32_t pinMask;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(GPIO_isPinValid(pin));
|
||||
|
||||
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
|
||||
((pin / 32U) * GPIO_CTRL_REGS_STEP);
|
||||
pinMask = (uint32_t)1U << (pin % 32U);
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable open drain if necessary
|
||||
//
|
||||
if((pinType & GPIO_PIN_TYPE_OD) != 0U)
|
||||
{
|
||||
gpioBaseAddr[GPIO_GPxODR_INDEX] |= pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
gpioBaseAddr[GPIO_GPxODR_INDEX] &= ~pinMask;
|
||||
}
|
||||
|
||||
//
|
||||
// Enable pull-up if necessary
|
||||
//
|
||||
if((pinType & GPIO_PIN_TYPE_PULLUP) != 0U)
|
||||
{
|
||||
gpioBaseAddr[GPIO_GPxPUD_INDEX] &= ~pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
gpioBaseAddr[GPIO_GPxPUD_INDEX] |= pinMask;
|
||||
}
|
||||
|
||||
//
|
||||
// Invert polarity if necessary
|
||||
//
|
||||
if((pinType & GPIO_PIN_TYPE_INVERT) != 0U)
|
||||
{
|
||||
gpioBaseAddr[GPIO_GPxINV_INDEX] |= pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
gpioBaseAddr[GPIO_GPxINV_INDEX] &= ~pinMask;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO_getPadConfig
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
GPIO_getPadConfig(uint32_t pin)
|
||||
{
|
||||
volatile uint32_t *gpioBaseAddr;
|
||||
uint32_t pinMask;
|
||||
uint32_t pinTypeRes;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(GPIO_isPinValid(pin));
|
||||
|
||||
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
|
||||
((pin / 32U) * GPIO_CTRL_REGS_STEP);
|
||||
pinMask = (uint32_t)1U << (pin % 32U);
|
||||
|
||||
pinTypeRes = GPIO_PIN_TYPE_STD;
|
||||
|
||||
//
|
||||
// Get open drain value
|
||||
//
|
||||
if((gpioBaseAddr[GPIO_GPxODR_INDEX] & pinMask) != 0U)
|
||||
{
|
||||
pinTypeRes |= GPIO_PIN_TYPE_OD;
|
||||
}
|
||||
|
||||
//
|
||||
// Get pull-up value
|
||||
//
|
||||
if((gpioBaseAddr[GPIO_GPxPUD_INDEX] & pinMask) == 0U)
|
||||
{
|
||||
pinTypeRes |= GPIO_PIN_TYPE_PULLUP;
|
||||
}
|
||||
|
||||
//
|
||||
// Get polarity value
|
||||
//
|
||||
if((gpioBaseAddr[GPIO_GPxINV_INDEX] & pinMask) != 0U)
|
||||
{
|
||||
pinTypeRes |= GPIO_PIN_TYPE_INVERT;
|
||||
}
|
||||
|
||||
return(pinTypeRes);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO_setQualificationMode
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification)
|
||||
{
|
||||
volatile uint32_t *gpioBaseAddr;
|
||||
uint32_t qSelIndex;
|
||||
uint32_t shiftAmt;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(GPIO_isPinValid(pin));
|
||||
|
||||
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
|
||||
((pin / 32U) * GPIO_CTRL_REGS_STEP);
|
||||
shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U);
|
||||
qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U);
|
||||
|
||||
//
|
||||
// Write the input qualification mode to the register.
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
gpioBaseAddr[qSelIndex] &= ~((uint32_t)GPIO_GPAQSEL1_GPIO0_M << shiftAmt);
|
||||
gpioBaseAddr[qSelIndex] |= (uint32_t)qualification << shiftAmt;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO_getQualificationMode
|
||||
//
|
||||
//*****************************************************************************
|
||||
GPIO_QualificationMode
|
||||
GPIO_getQualificationMode(uint32_t pin)
|
||||
{
|
||||
volatile uint32_t *gpioBaseAddr;
|
||||
uint32_t qSelIndex;
|
||||
uint32_t qualRes;
|
||||
uint32_t shiftAmt;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(GPIO_isPinValid(pin));
|
||||
|
||||
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
|
||||
((pin / 32U) * GPIO_CTRL_REGS_STEP);
|
||||
shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U);
|
||||
qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U);
|
||||
|
||||
//
|
||||
// Read the qualification mode register and shift and mask to get the
|
||||
// value for the specified pin.
|
||||
//
|
||||
qualRes = (gpioBaseAddr[qSelIndex] >> shiftAmt) &
|
||||
(uint32_t)GPIO_GPAQSEL1_GPIO0_M;
|
||||
return((GPIO_QualificationMode)qualRes);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO_setQualificationPeriod
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider)
|
||||
{
|
||||
volatile uint32_t *gpioBaseAddr;
|
||||
uint32_t pinMask, regVal, shiftAmt;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(GPIO_isPinValid(pin));
|
||||
ASSERT((divider >= 1U) && (divider <= 510U));
|
||||
|
||||
shiftAmt = (pin % 32U) & ~((uint32_t)0x7U);
|
||||
pinMask = (uint32_t)0xFFU << shiftAmt;
|
||||
|
||||
//
|
||||
// Divide divider by two to get the value that needs to go into the field.
|
||||
// Then shift it into the right place.
|
||||
//
|
||||
regVal = (divider / 2U) << shiftAmt;
|
||||
|
||||
//
|
||||
// Write the divider parameter into the register.
|
||||
//
|
||||
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
|
||||
((pin / 32U) * GPIO_CTRL_REGS_STEP);
|
||||
|
||||
EALLOW;
|
||||
gpioBaseAddr[GPIO_GPxCTRL_INDEX] &= ~pinMask;
|
||||
gpioBaseAddr[GPIO_GPxCTRL_INDEX] |= regVal;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO_setControllerCore
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core)
|
||||
{
|
||||
volatile uint32_t *gpioBaseAddr;
|
||||
uint32_t cSelIndex;
|
||||
uint32_t shiftAmt;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(GPIO_isPinValid(pin));
|
||||
|
||||
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
|
||||
((pin / 32U) * GPIO_CTRL_REGS_STEP);
|
||||
shiftAmt = (uint32_t)GPIO_GPACSEL1_GPIO1_S * (pin % 8U);
|
||||
cSelIndex = GPIO_GPxCSEL_INDEX + ((pin % 32U) / 8U);
|
||||
|
||||
//
|
||||
// Write the core parameter into the register.
|
||||
//
|
||||
EALLOW;
|
||||
gpioBaseAddr[cSelIndex] &= ~((uint32_t)GPIO_GPACSEL1_GPIO0_M << shiftAmt);
|
||||
gpioBaseAddr[cSelIndex] |= (uint32_t)core << shiftAmt;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO_setAnalogMode
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode)
|
||||
{
|
||||
volatile uint32_t *gpioBaseAddr;
|
||||
uint32_t pinMask;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((pin == 42U) || (pin == 43U));
|
||||
|
||||
pinMask = (uint32_t)1U << (pin % 32U);
|
||||
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
|
||||
((pin / 32U) * GPIO_CTRL_REGS_STEP);
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Set the analog mode selection.
|
||||
//
|
||||
if(mode == GPIO_ANALOG_ENABLED)
|
||||
{
|
||||
//
|
||||
// Enable analog mode
|
||||
//
|
||||
gpioBaseAddr[GPIO_GPxAMSEL_INDEX] |= pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Disable analog mode
|
||||
//
|
||||
gpioBaseAddr[GPIO_GPxAMSEL_INDEX] &= ~pinMask;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO_setPinConfig
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
GPIO_setPinConfig(uint32_t pinConfig)
|
||||
{
|
||||
uint32_t muxRegAddr;
|
||||
uint32_t pinMask, shiftAmt;
|
||||
|
||||
muxRegAddr = (uint32_t)GPIOCTRL_BASE + (pinConfig >> 16);
|
||||
shiftAmt = ((pinConfig >> 8) & (uint32_t)0xFFU);
|
||||
pinMask = (uint32_t)0x3U << shiftAmt;
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Clear fields in MUX register first to avoid glitches
|
||||
//
|
||||
HWREG(muxRegAddr) &= ~pinMask;
|
||||
|
||||
//
|
||||
// Write value into GMUX register
|
||||
//
|
||||
HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) =
|
||||
(HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) & ~pinMask) |
|
||||
(((pinConfig >> 2) & (uint32_t)0x3U) << shiftAmt);
|
||||
|
||||
//
|
||||
// Write value into MUX register
|
||||
//
|
||||
HWREG(muxRegAddr) |= ((pinConfig & (uint32_t)0x3U) << shiftAmt);
|
||||
EDIS;
|
||||
}
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,45 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hrpwm.c
|
||||
//
|
||||
// TITLE: C28x HRPWM driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "hrpwm.h"
|
||||
|
||||
//
|
||||
// All the API functions are in-lined in hrpwm.h
|
||||
//
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,29 @@
|
|||
#ifndef HW_REG_INCLUSIVE_TERMINOLOGY_H
|
||||
#define HW_REG_INCLUSIVE_TERMINOLOGY_H
|
||||
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// SPI
|
||||
//*****************************************************************************
|
||||
#define SPI_CTL_CONTROLLER_PERIPHERAL SPI_CTL_MASTER_SLAVE
|
||||
#define SPI_PRI_PTEINV SPI_PRI_STEINV
|
||||
|
||||
//*****************************************************************************
|
||||
// I2C
|
||||
//*****************************************************************************
|
||||
#define I2C_O_TAR I2C_O_SAR
|
||||
|
||||
#define I2C_TAR_TAR_S I2C_SAR_SAR_S
|
||||
#define I2C_TAR_TAR_M I2C_SAR_SAR_M
|
||||
|
||||
#define I2C_IER_AAT I2C_IER_AAS
|
||||
|
||||
#define I2C_STR_AAT I2C_STR_AAS
|
||||
#define I2C_STR_TDIR I2C_STR_SDIR
|
||||
|
||||
#define I2C_MDR_CNT I2C_MDR_MST
|
||||
|
||||
|
||||
|
||||
#endif // HW_REG_INCLUSIVE_TERMINOLOGY_H
|
|
@ -0,0 +1,271 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: i2c.c
|
||||
//
|
||||
// TITLE: C28x I2C driver.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "i2c.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C_initController
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
I2C_initController(uint32_t base, uint32_t sysclkHz, uint32_t bitRate,
|
||||
I2C_DutyCycle dutyCycle)
|
||||
{
|
||||
uint32_t modPrescale;
|
||||
uint32_t divider;
|
||||
uint32_t dValue;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(I2C_isBaseValid(base));
|
||||
ASSERT((10000000U / bitRate) > 10U);
|
||||
|
||||
//
|
||||
// Set the prescaler for the module clock.
|
||||
//
|
||||
modPrescale = (sysclkHz / 10000000U) - 1U;
|
||||
HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale;
|
||||
|
||||
switch(modPrescale)
|
||||
{
|
||||
case 0U:
|
||||
dValue = 7U;
|
||||
break;
|
||||
|
||||
case 1U:
|
||||
dValue = 6U;
|
||||
break;
|
||||
|
||||
default:
|
||||
dValue = 5U;
|
||||
break;
|
||||
}
|
||||
|
||||
//
|
||||
// Set the divider for the time low
|
||||
//
|
||||
divider = (10000000U / bitRate) - (2U * dValue);
|
||||
|
||||
if(dutyCycle == I2C_DUTYCYCLE_50)
|
||||
{
|
||||
HWREGH(base + I2C_O_CLKH) = divider / 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
HWREGH(base + I2C_O_CLKH) = divider / 3U;
|
||||
}
|
||||
|
||||
HWREGH(base + I2C_O_CLKL) = divider - HWREGH(base + I2C_O_CLKH);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C_enableInterrupt
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
I2C_enableInterrupt(uint32_t base, uint32_t intFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(I2C_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Enable the desired basic interrupts
|
||||
//
|
||||
HWREGH(base + I2C_O_IER) |= (intFlags & 0x00FFU);
|
||||
|
||||
//
|
||||
// Enabling addressed-as-target interrupt separately because its bit is
|
||||
// different between the IER and STR registers.
|
||||
//
|
||||
if((intFlags & I2C_INT_ADDR_TARGET) != 0U)
|
||||
{
|
||||
HWREGH(base + I2C_O_IER) |= I2C_IER_AAT;
|
||||
}
|
||||
|
||||
//
|
||||
// Enable desired FIFO interrupts.
|
||||
//
|
||||
if((intFlags & I2C_INT_TXFF) != 0U)
|
||||
{
|
||||
HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFIENA;
|
||||
}
|
||||
|
||||
if((intFlags & I2C_INT_RXFF) != 0U)
|
||||
{
|
||||
HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFIENA;
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C_disableInterrupt
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
I2C_disableInterrupt(uint32_t base, uint32_t intFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(I2C_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Disable the desired basic interrupts.
|
||||
//
|
||||
HWREGH(base + I2C_O_IER) &= ~(intFlags & 0x00FFU);
|
||||
|
||||
//
|
||||
// Disabling addressed-as-target interrupt separately because its bit is
|
||||
// different between the IER and STR registers.
|
||||
//
|
||||
if((intFlags & I2C_INT_ADDR_TARGET) != 0U)
|
||||
{
|
||||
HWREGH(base + I2C_O_IER) &= ~I2C_IER_AAT;
|
||||
}
|
||||
|
||||
//
|
||||
// Disable the desired FIFO interrupts.
|
||||
//
|
||||
if((intFlags & I2C_INT_TXFF) != 0U)
|
||||
{
|
||||
HWREGH(base + I2C_O_FFTX) &= ~(I2C_FFTX_TXFFIENA);
|
||||
}
|
||||
|
||||
if((intFlags & I2C_INT_RXFF) != 0U)
|
||||
{
|
||||
HWREGH(base + I2C_O_FFRX) &= ~(I2C_FFRX_RXFFIENA);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C_getInterruptStatus
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
I2C_getInterruptStatus(uint32_t base)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(I2C_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Return only the status bits associated with interrupts.
|
||||
//
|
||||
temp = (uint32_t)(HWREGH(base + I2C_O_STR) & I2C_STR_INTMASK);
|
||||
|
||||
//
|
||||
// Read FIFO interrupt flags.
|
||||
//
|
||||
if((HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFINT) != 0U)
|
||||
{
|
||||
temp |= I2C_INT_TXFF;
|
||||
}
|
||||
|
||||
if((HWREGH(base + I2C_O_FFRX) & I2C_FFRX_RXFFINT) != 0U)
|
||||
{
|
||||
temp |= I2C_INT_RXFF;
|
||||
}
|
||||
|
||||
return(temp);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C_clearInterruptStatus
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(I2C_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Clear the interrupt flags that are located in STR.
|
||||
//
|
||||
HWREGH(base + I2C_O_STR) = ((uint16_t)intFlags & I2C_STR_INTMASK);
|
||||
|
||||
//
|
||||
// Clear the FIFO interrupt flags if needed.
|
||||
//
|
||||
if((intFlags & I2C_INT_TXFF) != 0U)
|
||||
{
|
||||
HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFINTCLR;
|
||||
}
|
||||
|
||||
if((intFlags & I2C_INT_RXFF) != 0U)
|
||||
{
|
||||
HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFINTCLR;
|
||||
}
|
||||
}
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C_configureModuleFrequency
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz)
|
||||
{
|
||||
uint32_t modPrescale;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(I2C_isBaseValid(base));
|
||||
|
||||
//
|
||||
// Set the prescaler for the module clock.
|
||||
//
|
||||
modPrescale = (sysclkHz / 10000000U) - 1U;
|
||||
HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale;
|
||||
}
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,909 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_adc.h
|
||||
//
|
||||
// TITLE: Definitions for the ADC registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_ADC_H
|
||||
#define HW_ADC_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the ADC register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_O_CTL1 0x0U // ADC Control 1 Register
|
||||
#define ADC_O_CTL2 0x1U // ADC Control 2 Register
|
||||
#define ADC_O_BURSTCTL 0x2U // ADC Burst Control Register
|
||||
#define ADC_O_INTFLG 0x3U // ADC Interrupt Flag Register
|
||||
#define ADC_O_INTFLGCLR 0x4U // ADC Interrupt Flag Clear Register
|
||||
#define ADC_O_INTOVF 0x5U // ADC Interrupt Overflow Register
|
||||
#define ADC_O_INTOVFCLR 0x6U // ADC Interrupt Overflow Clear Register
|
||||
#define ADC_O_INTSEL1N2 0x7U // ADC Interrupt 1 and 2 Selection Register
|
||||
#define ADC_O_INTSEL3N4 0x8U // ADC Interrupt 3 and 4 Selection Register
|
||||
#define ADC_O_SOCPRICTL 0x9U // ADC SOC Priority Control Register
|
||||
#define ADC_O_INTSOCSEL1 0xAU // ADC Interrupt SOC Selection 1 Register
|
||||
#define ADC_O_INTSOCSEL2 0xBU // ADC Interrupt SOC Selection 2 Register
|
||||
#define ADC_O_SOCFLG1 0xCU // ADC SOC Flag 1 Register
|
||||
#define ADC_O_SOCFRC1 0xDU // ADC SOC Force 1 Register
|
||||
#define ADC_O_SOCOVF1 0xEU // ADC SOC Overflow 1 Register
|
||||
#define ADC_O_SOCOVFCLR1 0xFU // ADC SOC Overflow Clear 1 Register
|
||||
#define ADC_O_SOC0CTL 0x10U // ADC SOC0 Control Register
|
||||
#define ADC_O_SOC1CTL 0x12U // ADC SOC1 Control Register
|
||||
#define ADC_O_SOC2CTL 0x14U // ADC SOC2 Control Register
|
||||
#define ADC_O_SOC3CTL 0x16U // ADC SOC3 Control Register
|
||||
#define ADC_O_SOC4CTL 0x18U // ADC SOC4 Control Register
|
||||
#define ADC_O_SOC5CTL 0x1AU // ADC SOC5 Control Register
|
||||
#define ADC_O_SOC6CTL 0x1CU // ADC SOC6 Control Register
|
||||
#define ADC_O_SOC7CTL 0x1EU // ADC SOC7 Control Register
|
||||
#define ADC_O_SOC8CTL 0x20U // ADC SOC8 Control Register
|
||||
#define ADC_O_SOC9CTL 0x22U // ADC SOC9 Control Register
|
||||
#define ADC_O_SOC10CTL 0x24U // ADC SOC10 Control Register
|
||||
#define ADC_O_SOC11CTL 0x26U // ADC SOC11 Control Register
|
||||
#define ADC_O_SOC12CTL 0x28U // ADC SOC12 Control Register
|
||||
#define ADC_O_SOC13CTL 0x2AU // ADC SOC13 Control Register
|
||||
#define ADC_O_SOC14CTL 0x2CU // ADC SOC14 Control Register
|
||||
#define ADC_O_SOC15CTL 0x2EU // ADC SOC15 Control Register
|
||||
#define ADC_O_EVTSTAT 0x30U // ADC Event Status Register
|
||||
#define ADC_O_EVTCLR 0x32U // ADC Event Clear Register
|
||||
#define ADC_O_EVTSEL 0x34U // ADC Event Selection Register
|
||||
#define ADC_O_EVTINTSEL 0x36U // ADC Event Interrupt Selection Register
|
||||
#define ADC_O_OSDETECT 0x38U // ADC Open and Shorts Detect Register
|
||||
#define ADC_O_COUNTER 0x39U // ADC Counter Register
|
||||
#define ADC_O_REV 0x3AU // ADC Revision Register
|
||||
#define ADC_O_OFFTRIM 0x3BU // ADC Offset Trim Register
|
||||
#define ADC_O_PPB1CONFIG 0x40U // ADC PPB1 Config Register
|
||||
#define ADC_O_PPB1STAMP 0x41U // ADC PPB1 Sample Delay Time Stamp Register
|
||||
#define ADC_O_PPB1OFFCAL 0x42U // ADC PPB1 Offset Calibration Register
|
||||
#define ADC_O_PPB1OFFREF 0x43U // ADC PPB1 Offset Reference Register
|
||||
#define ADC_O_PPB1TRIPHI 0x44U // ADC PPB1 Trip High Register
|
||||
#define ADC_O_PPB1TRIPLO 0x46U // ADC PPB1 Trip Low/Trigger Time Stamp Register
|
||||
#define ADC_O_PPB2CONFIG 0x48U // ADC PPB2 Config Register
|
||||
#define ADC_O_PPB2STAMP 0x49U // ADC PPB2 Sample Delay Time Stamp Register
|
||||
#define ADC_O_PPB2OFFCAL 0x4AU // ADC PPB2 Offset Calibration Register
|
||||
#define ADC_O_PPB2OFFREF 0x4BU // ADC PPB2 Offset Reference Register
|
||||
#define ADC_O_PPB2TRIPHI 0x4CU // ADC PPB2 Trip High Register
|
||||
#define ADC_O_PPB2TRIPLO 0x4EU // ADC PPB2 Trip Low/Trigger Time Stamp Register
|
||||
#define ADC_O_PPB3CONFIG 0x50U // ADC PPB3 Config Register
|
||||
#define ADC_O_PPB3STAMP 0x51U // ADC PPB3 Sample Delay Time Stamp Register
|
||||
#define ADC_O_PPB3OFFCAL 0x52U // ADC PPB3 Offset Calibration Register
|
||||
#define ADC_O_PPB3OFFREF 0x53U // ADC PPB3 Offset Reference Register
|
||||
#define ADC_O_PPB3TRIPHI 0x54U // ADC PPB3 Trip High Register
|
||||
#define ADC_O_PPB3TRIPLO 0x56U // ADC PPB3 Trip Low/Trigger Time Stamp Register
|
||||
#define ADC_O_PPB4CONFIG 0x58U // ADC PPB4 Config Register
|
||||
#define ADC_O_PPB4STAMP 0x59U // ADC PPB4 Sample Delay Time Stamp Register
|
||||
#define ADC_O_PPB4OFFCAL 0x5AU // ADC PPB4 Offset Calibration Register
|
||||
#define ADC_O_PPB4OFFREF 0x5BU // ADC PPB4 Offset Reference Register
|
||||
#define ADC_O_PPB4TRIPHI 0x5CU // ADC PPB4 Trip High Register
|
||||
#define ADC_O_PPB4TRIPLO 0x5EU // ADC PPB4 Trip Low/Trigger Time Stamp Register
|
||||
#define ADC_O_INLTRIM1 0x70U // ADC Linearity Trim 1 Register
|
||||
#define ADC_O_INLTRIM2 0x72U // ADC Linearity Trim 2 Register
|
||||
#define ADC_O_INLTRIM3 0x74U // ADC Linearity Trim 3 Register
|
||||
#define ADC_O_INLTRIM4 0x76U // ADC Linearity Trim 4 Register
|
||||
#define ADC_O_INLTRIM5 0x78U // ADC Linearity Trim 5 Register
|
||||
#define ADC_O_INLTRIM6 0x7AU // ADC Linearity Trim 6 Register
|
||||
|
||||
#define ADC_O_RESULT0 0x0U // ADC Result 0 Register
|
||||
#define ADC_O_RESULT1 0x1U // ADC Result 1 Register
|
||||
#define ADC_O_RESULT2 0x2U // ADC Result 2 Register
|
||||
#define ADC_O_RESULT3 0x3U // ADC Result 3 Register
|
||||
#define ADC_O_RESULT4 0x4U // ADC Result 4 Register
|
||||
#define ADC_O_RESULT5 0x5U // ADC Result 5 Register
|
||||
#define ADC_O_RESULT6 0x6U // ADC Result 6 Register
|
||||
#define ADC_O_RESULT7 0x7U // ADC Result 7 Register
|
||||
#define ADC_O_RESULT8 0x8U // ADC Result 8 Register
|
||||
#define ADC_O_RESULT9 0x9U // ADC Result 9 Register
|
||||
#define ADC_O_RESULT10 0xAU // ADC Result 10 Register
|
||||
#define ADC_O_RESULT11 0xBU // ADC Result 11 Register
|
||||
#define ADC_O_RESULT12 0xCU // ADC Result 12 Register
|
||||
#define ADC_O_RESULT13 0xDU // ADC Result 13 Register
|
||||
#define ADC_O_RESULT14 0xEU // ADC Result 14 Register
|
||||
#define ADC_O_RESULT15 0xFU // ADC Result 15 Register
|
||||
#define ADC_O_PPB1RESULT 0x10U // ADC Post Processing Block 1 Result Register
|
||||
#define ADC_O_PPB2RESULT 0x12U // ADC Post Processing Block 2 Result Register
|
||||
#define ADC_O_PPB3RESULT 0x14U // ADC Post Processing Block 3 Result Register
|
||||
#define ADC_O_PPB4RESULT 0x16U // ADC Post Processing Block 4 Result Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCCTL1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_CTL1_INTPULSEPOS 0x4U // ADC Interrupt Pulse Position
|
||||
#define ADC_CTL1_ADCPWDNZ 0x80U // ADC Power Down
|
||||
#define ADC_CTL1_ADCBSYCHN_S 8U
|
||||
#define ADC_CTL1_ADCBSYCHN_M 0xF00U // ADC Busy Channel
|
||||
#define ADC_CTL1_ADCBSY 0x2000U // ADC Busy
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCCTL2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_CTL2_PRESCALE_S 0U
|
||||
#define ADC_CTL2_PRESCALE_M 0xFU // ADC Clock Prescaler
|
||||
#define ADC_CTL2_RESOLUTION 0x40U // SOC Conversion Resolution
|
||||
#define ADC_CTL2_SIGNALMODE 0x80U // SOC Signaling Mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCBURSTCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_BURSTCTL_BURSTTRIGSEL_S 0U
|
||||
#define ADC_BURSTCTL_BURSTTRIGSEL_M 0x3FU // SOC Burst Trigger Source Select
|
||||
#define ADC_BURSTCTL_BURSTSIZE_S 8U
|
||||
#define ADC_BURSTCTL_BURSTSIZE_M 0xF00U // SOC Burst Size Select
|
||||
#define ADC_BURSTCTL_BURSTEN 0x8000U // SOC Burst Mode Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCINTFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_INTFLG_ADCINT1 0x1U // ADC Interrupt 1 Flag
|
||||
#define ADC_INTFLG_ADCINT2 0x2U // ADC Interrupt 2 Flag
|
||||
#define ADC_INTFLG_ADCINT3 0x4U // ADC Interrupt 3 Flag
|
||||
#define ADC_INTFLG_ADCINT4 0x8U // ADC Interrupt 4 Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCINTFLGCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_INTFLGCLR_ADCINT1 0x1U // ADC Interrupt 1 Flag Clear
|
||||
#define ADC_INTFLGCLR_ADCINT2 0x2U // ADC Interrupt 2 Flag Clear
|
||||
#define ADC_INTFLGCLR_ADCINT3 0x4U // ADC Interrupt 3 Flag Clear
|
||||
#define ADC_INTFLGCLR_ADCINT4 0x8U // ADC Interrupt 4 Flag Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCINTOVF register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_INTOVF_ADCINT1 0x1U // ADC Interrupt 1 Overflow Flags
|
||||
#define ADC_INTOVF_ADCINT2 0x2U // ADC Interrupt 2 Overflow Flags
|
||||
#define ADC_INTOVF_ADCINT3 0x4U // ADC Interrupt 3 Overflow Flags
|
||||
#define ADC_INTOVF_ADCINT4 0x8U // ADC Interrupt 4 Overflow Flags
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCINTOVFCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_INTOVFCLR_ADCINT1 0x1U // ADC Interrupt 1 Overflow Clear Bits
|
||||
#define ADC_INTOVFCLR_ADCINT2 0x2U // ADC Interrupt 2 Overflow Clear Bits
|
||||
#define ADC_INTOVFCLR_ADCINT3 0x4U // ADC Interrupt 3 Overflow Clear Bits
|
||||
#define ADC_INTOVFCLR_ADCINT4 0x8U // ADC Interrupt 4 Overflow Clear Bits
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCINTSEL1N2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_INTSEL1N2_INT1SEL_S 0U
|
||||
#define ADC_INTSEL1N2_INT1SEL_M 0xFU // ADCINT1 EOC Source Select
|
||||
#define ADC_INTSEL1N2_INT1E 0x20U // ADCINT1 Interrupt Enable
|
||||
#define ADC_INTSEL1N2_INT1CONT 0x40U // ADCINT1 Continue to Interrupt Mode
|
||||
#define ADC_INTSEL1N2_INT2SEL_S 8U
|
||||
#define ADC_INTSEL1N2_INT2SEL_M 0xF00U // ADCINT2 EOC Source Select
|
||||
#define ADC_INTSEL1N2_INT2E 0x2000U // ADCINT2 Interrupt Enable
|
||||
#define ADC_INTSEL1N2_INT2CONT 0x4000U // ADCINT2 Continue to Interrupt Mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCINTSEL3N4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_INTSEL3N4_INT3SEL_S 0U
|
||||
#define ADC_INTSEL3N4_INT3SEL_M 0xFU // ADCINT3 EOC Source Select
|
||||
#define ADC_INTSEL3N4_INT3E 0x20U // ADCINT3 Interrupt Enable
|
||||
#define ADC_INTSEL3N4_INT3CONT 0x40U // ADCINT3 Continue to Interrupt Mode
|
||||
#define ADC_INTSEL3N4_INT4SEL_S 8U
|
||||
#define ADC_INTSEL3N4_INT4SEL_M 0xF00U // ADCINT4 EOC Source Select
|
||||
#define ADC_INTSEL3N4_INT4E 0x2000U // ADCINT4 Interrupt Enable
|
||||
#define ADC_INTSEL3N4_INT4CONT 0x4000U // ADCINT4 Continue to Interrupt Mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOCPRICTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOCPRICTL_SOCPRIORITY_S 0U
|
||||
#define ADC_SOCPRICTL_SOCPRIORITY_M 0x1FU // SOC Priority
|
||||
#define ADC_SOCPRICTL_RRPOINTER_S 5U
|
||||
#define ADC_SOCPRICTL_RRPOINTER_M 0x3E0U // Round Robin Pointer
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCINTSOCSEL1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_INTSOCSEL1_SOC0_S 0U
|
||||
#define ADC_INTSOCSEL1_SOC0_M 0x3U // SOC0 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL1_SOC1_S 2U
|
||||
#define ADC_INTSOCSEL1_SOC1_M 0xCU // SOC1 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL1_SOC2_S 4U
|
||||
#define ADC_INTSOCSEL1_SOC2_M 0x30U // SOC2 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL1_SOC3_S 6U
|
||||
#define ADC_INTSOCSEL1_SOC3_M 0xC0U // SOC3 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL1_SOC4_S 8U
|
||||
#define ADC_INTSOCSEL1_SOC4_M 0x300U // SOC4 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL1_SOC5_S 10U
|
||||
#define ADC_INTSOCSEL1_SOC5_M 0xC00U // SOC5 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL1_SOC6_S 12U
|
||||
#define ADC_INTSOCSEL1_SOC6_M 0x3000U // SOC6 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL1_SOC7_S 14U
|
||||
#define ADC_INTSOCSEL1_SOC7_M 0xC000U // SOC7 ADC Interrupt Trigger Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCINTSOCSEL2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_INTSOCSEL2_SOC8_S 0U
|
||||
#define ADC_INTSOCSEL2_SOC8_M 0x3U // SOC8 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL2_SOC9_S 2U
|
||||
#define ADC_INTSOCSEL2_SOC9_M 0xCU // SOC9 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL2_SOC10_S 4U
|
||||
#define ADC_INTSOCSEL2_SOC10_M 0x30U // SOC10 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL2_SOC11_S 6U
|
||||
#define ADC_INTSOCSEL2_SOC11_M 0xC0U // SOC11 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL2_SOC12_S 8U
|
||||
#define ADC_INTSOCSEL2_SOC12_M 0x300U // SOC12 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL2_SOC13_S 10U
|
||||
#define ADC_INTSOCSEL2_SOC13_M 0xC00U // SOC13 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL2_SOC14_S 12U
|
||||
#define ADC_INTSOCSEL2_SOC14_M 0x3000U // SOC14 ADC Interrupt Trigger Select
|
||||
#define ADC_INTSOCSEL2_SOC15_S 14U
|
||||
#define ADC_INTSOCSEL2_SOC15_M 0xC000U // SOC15 ADC Interrupt Trigger Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOCFLG1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOCFLG1_SOC0 0x1U // SOC0 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC1 0x2U // SOC1 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC2 0x4U // SOC2 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC3 0x8U // SOC3 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC4 0x10U // SOC4 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC5 0x20U // SOC5 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC6 0x40U // SOC6 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC7 0x80U // SOC7 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC8 0x100U // SOC8 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC9 0x200U // SOC9 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC10 0x400U // SOC10 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC11 0x800U // SOC11 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC12 0x1000U // SOC12 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC13 0x2000U // SOC13 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC14 0x4000U // SOC14 Start of Conversion Flag
|
||||
#define ADC_SOCFLG1_SOC15 0x8000U // SOC15 Start of Conversion Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOCFRC1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOCFRC1_SOC0 0x1U // SOC0 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC1 0x2U // SOC1 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC2 0x4U // SOC2 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC3 0x8U // SOC3 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC4 0x10U // SOC4 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC5 0x20U // SOC5 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC6 0x40U // SOC6 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC7 0x80U // SOC7 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC8 0x100U // SOC8 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC9 0x200U // SOC9 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC10 0x400U // SOC10 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC11 0x800U // SOC11 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC12 0x1000U // SOC12 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC13 0x2000U // SOC13 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC14 0x4000U // SOC14 Force Start of Conversion Bit
|
||||
#define ADC_SOCFRC1_SOC15 0x8000U // SOC15 Force Start of Conversion Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOCOVF1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOCOVF1_SOC0 0x1U // SOC0 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC1 0x2U // SOC1 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC2 0x4U // SOC2 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC3 0x8U // SOC3 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC4 0x10U // SOC4 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC5 0x20U // SOC5 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC6 0x40U // SOC6 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC7 0x80U // SOC7 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC8 0x100U // SOC8 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC9 0x200U // SOC9 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC10 0x400U // SOC10 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC11 0x800U // SOC11 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC12 0x1000U // SOC12 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC13 0x2000U // SOC13 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC14 0x4000U // SOC14 Start of Conversion Overflow Flag
|
||||
#define ADC_SOCOVF1_SOC15 0x8000U // SOC15 Start of Conversion Overflow Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOCOVFCLR1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOCOVFCLR1_SOC0 0x1U // SOC0 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC1 0x2U // SOC1 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC2 0x4U // SOC2 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC3 0x8U // SOC3 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC4 0x10U // SOC4 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC5 0x20U // SOC5 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC6 0x40U // SOC6 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC7 0x80U // SOC7 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC8 0x100U // SOC8 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC9 0x200U // SOC9 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC10 0x400U // SOC10 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC11 0x800U // SOC11 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC12 0x1000U // SOC12 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC13 0x2000U // SOC13 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC14 0x4000U // SOC14 Clear Start of Conversion Overflow Bit
|
||||
#define ADC_SOCOVFCLR1_SOC15 0x8000U // SOC15 Clear Start of Conversion Overflow Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC0CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC0CTL_ACQPS_S 0U
|
||||
#define ADC_SOC0CTL_ACQPS_M 0x1FFU // SOC0 Acquisition Prescale
|
||||
#define ADC_SOC0CTL_CHSEL_S 15U
|
||||
#define ADC_SOC0CTL_CHSEL_M 0x78000U // SOC0 Channel Select
|
||||
#define ADC_SOC0CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC0CTL_TRIGSEL_M 0x1F00000U // SOC0 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC1CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC1CTL_ACQPS_S 0U
|
||||
#define ADC_SOC1CTL_ACQPS_M 0x1FFU // SOC1 Acquisition Prescale
|
||||
#define ADC_SOC1CTL_CHSEL_S 15U
|
||||
#define ADC_SOC1CTL_CHSEL_M 0x78000U // SOC1 Channel Select
|
||||
#define ADC_SOC1CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC1CTL_TRIGSEL_M 0x1F00000U // SOC1 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC2CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC2CTL_ACQPS_S 0U
|
||||
#define ADC_SOC2CTL_ACQPS_M 0x1FFU // SOC2 Acquisition Prescale
|
||||
#define ADC_SOC2CTL_CHSEL_S 15U
|
||||
#define ADC_SOC2CTL_CHSEL_M 0x78000U // SOC2 Channel Select
|
||||
#define ADC_SOC2CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC2CTL_TRIGSEL_M 0x1F00000U // SOC2 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC3CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC3CTL_ACQPS_S 0U
|
||||
#define ADC_SOC3CTL_ACQPS_M 0x1FFU // SOC3 Acquisition Prescale
|
||||
#define ADC_SOC3CTL_CHSEL_S 15U
|
||||
#define ADC_SOC3CTL_CHSEL_M 0x78000U // SOC3 Channel Select
|
||||
#define ADC_SOC3CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC3CTL_TRIGSEL_M 0x1F00000U // SOC3 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC4CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC4CTL_ACQPS_S 0U
|
||||
#define ADC_SOC4CTL_ACQPS_M 0x1FFU // SOC4 Acquisition Prescale
|
||||
#define ADC_SOC4CTL_CHSEL_S 15U
|
||||
#define ADC_SOC4CTL_CHSEL_M 0x78000U // SOC4 Channel Select
|
||||
#define ADC_SOC4CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC4CTL_TRIGSEL_M 0x1F00000U // SOC4 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC5CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC5CTL_ACQPS_S 0U
|
||||
#define ADC_SOC5CTL_ACQPS_M 0x1FFU // SOC5 Acquisition Prescale
|
||||
#define ADC_SOC5CTL_CHSEL_S 15U
|
||||
#define ADC_SOC5CTL_CHSEL_M 0x78000U // SOC5 Channel Select
|
||||
#define ADC_SOC5CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC5CTL_TRIGSEL_M 0x1F00000U // SOC5 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC6CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC6CTL_ACQPS_S 0U
|
||||
#define ADC_SOC6CTL_ACQPS_M 0x1FFU // SOC6 Acquisition Prescale
|
||||
#define ADC_SOC6CTL_CHSEL_S 15U
|
||||
#define ADC_SOC6CTL_CHSEL_M 0x78000U // SOC6 Channel Select
|
||||
#define ADC_SOC6CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC6CTL_TRIGSEL_M 0x1F00000U // SOC6 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC7CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC7CTL_ACQPS_S 0U
|
||||
#define ADC_SOC7CTL_ACQPS_M 0x1FFU // SOC7 Acquisition Prescale
|
||||
#define ADC_SOC7CTL_CHSEL_S 15U
|
||||
#define ADC_SOC7CTL_CHSEL_M 0x78000U // SOC7 Channel Select
|
||||
#define ADC_SOC7CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC7CTL_TRIGSEL_M 0x1F00000U // SOC7 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC8CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC8CTL_ACQPS_S 0U
|
||||
#define ADC_SOC8CTL_ACQPS_M 0x1FFU // SOC8 Acquisition Prescale
|
||||
#define ADC_SOC8CTL_CHSEL_S 15U
|
||||
#define ADC_SOC8CTL_CHSEL_M 0x78000U // SOC8 Channel Select
|
||||
#define ADC_SOC8CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC8CTL_TRIGSEL_M 0x1F00000U // SOC8 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC9CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC9CTL_ACQPS_S 0U
|
||||
#define ADC_SOC9CTL_ACQPS_M 0x1FFU // SOC9 Acquisition Prescale
|
||||
#define ADC_SOC9CTL_CHSEL_S 15U
|
||||
#define ADC_SOC9CTL_CHSEL_M 0x78000U // SOC9 Channel Select
|
||||
#define ADC_SOC9CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC9CTL_TRIGSEL_M 0x1F00000U // SOC9 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC10CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC10CTL_ACQPS_S 0U
|
||||
#define ADC_SOC10CTL_ACQPS_M 0x1FFU // SOC10 Acquisition Prescale
|
||||
#define ADC_SOC10CTL_CHSEL_S 15U
|
||||
#define ADC_SOC10CTL_CHSEL_M 0x78000U // SOC10 Channel Select
|
||||
#define ADC_SOC10CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC10CTL_TRIGSEL_M 0x1F00000U // SOC10 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC11CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC11CTL_ACQPS_S 0U
|
||||
#define ADC_SOC11CTL_ACQPS_M 0x1FFU // SOC11 Acquisition Prescale
|
||||
#define ADC_SOC11CTL_CHSEL_S 15U
|
||||
#define ADC_SOC11CTL_CHSEL_M 0x78000U // SOC11 Channel Select
|
||||
#define ADC_SOC11CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC11CTL_TRIGSEL_M 0x1F00000U // SOC11 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC12CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC12CTL_ACQPS_S 0U
|
||||
#define ADC_SOC12CTL_ACQPS_M 0x1FFU // SOC12 Acquisition Prescale
|
||||
#define ADC_SOC12CTL_CHSEL_S 15U
|
||||
#define ADC_SOC12CTL_CHSEL_M 0x78000U // SOC12 Channel Select
|
||||
#define ADC_SOC12CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC12CTL_TRIGSEL_M 0x1F00000U // SOC12 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC13CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC13CTL_ACQPS_S 0U
|
||||
#define ADC_SOC13CTL_ACQPS_M 0x1FFU // SOC13 Acquisition Prescale
|
||||
#define ADC_SOC13CTL_CHSEL_S 15U
|
||||
#define ADC_SOC13CTL_CHSEL_M 0x78000U // SOC13 Channel Select
|
||||
#define ADC_SOC13CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC13CTL_TRIGSEL_M 0x1F00000U // SOC13 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC14CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC14CTL_ACQPS_S 0U
|
||||
#define ADC_SOC14CTL_ACQPS_M 0x1FFU // SOC14 Acquisition Prescale
|
||||
#define ADC_SOC14CTL_CHSEL_S 15U
|
||||
#define ADC_SOC14CTL_CHSEL_M 0x78000U // SOC14 Channel Select
|
||||
#define ADC_SOC14CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC14CTL_TRIGSEL_M 0x1F00000U // SOC14 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCSOC15CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_SOC15CTL_ACQPS_S 0U
|
||||
#define ADC_SOC15CTL_ACQPS_M 0x1FFU // SOC15 Acquisition Prescale
|
||||
#define ADC_SOC15CTL_CHSEL_S 15U
|
||||
#define ADC_SOC15CTL_CHSEL_M 0x78000U // SOC15 Channel Select
|
||||
#define ADC_SOC15CTL_TRIGSEL_S 20U
|
||||
#define ADC_SOC15CTL_TRIGSEL_M 0x1F00000U // SOC15 Trigger Source Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCEVTSTAT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_EVTSTAT_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Flag
|
||||
#define ADC_EVTSTAT_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Flag
|
||||
#define ADC_EVTSTAT_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Flag
|
||||
#define ADC_EVTSTAT_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Flag
|
||||
#define ADC_EVTSTAT_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Flag
|
||||
#define ADC_EVTSTAT_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Flag
|
||||
#define ADC_EVTSTAT_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Flag
|
||||
#define ADC_EVTSTAT_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Flag
|
||||
#define ADC_EVTSTAT_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Flag
|
||||
#define ADC_EVTSTAT_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Flag
|
||||
#define ADC_EVTSTAT_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Flag
|
||||
#define ADC_EVTSTAT_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCEVTCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_EVTCLR_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Clear
|
||||
#define ADC_EVTCLR_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Clear
|
||||
#define ADC_EVTCLR_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Clear
|
||||
#define ADC_EVTCLR_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Clear
|
||||
#define ADC_EVTCLR_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Clear
|
||||
#define ADC_EVTCLR_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Clear
|
||||
#define ADC_EVTCLR_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Clear
|
||||
#define ADC_EVTCLR_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Clear
|
||||
#define ADC_EVTCLR_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Clear
|
||||
#define ADC_EVTCLR_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Clear
|
||||
#define ADC_EVTCLR_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Clear
|
||||
#define ADC_EVTCLR_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCEVTSEL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_EVTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Event Enable
|
||||
#define ADC_EVTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Event Enable
|
||||
#define ADC_EVTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Event Enable
|
||||
#define ADC_EVTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Event Enable
|
||||
#define ADC_EVTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Event Enable
|
||||
#define ADC_EVTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Event Enable
|
||||
#define ADC_EVTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Event Enable
|
||||
#define ADC_EVTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Event Enable
|
||||
#define ADC_EVTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Event Enable
|
||||
#define ADC_EVTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Event Enable
|
||||
#define ADC_EVTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Event Enable
|
||||
#define ADC_EVTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Event Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCEVTINTSEL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_EVTINTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Interrupt Enable
|
||||
#define ADC_EVTINTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Interrupt Enable
|
||||
#define ADC_EVTINTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Interrupt
|
||||
// Enable
|
||||
#define ADC_EVTINTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Interrupt Enable
|
||||
#define ADC_EVTINTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Interrupt Enable
|
||||
#define ADC_EVTINTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Interrupt
|
||||
// Enable
|
||||
#define ADC_EVTINTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Interrupt Enable
|
||||
#define ADC_EVTINTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Interrupt Enable
|
||||
#define ADC_EVTINTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Interrupt
|
||||
// Enable
|
||||
#define ADC_EVTINTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Interrupt Enable
|
||||
#define ADC_EVTINTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Interrupt Enable
|
||||
#define ADC_EVTINTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Interrupt
|
||||
// Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCOSDETECT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_OSDETECT_DETECTCFG_S 0U
|
||||
#define ADC_OSDETECT_DETECTCFG_M 0x7U // ADC Opens and Shorts Detect Configuration
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCCOUNTER register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_COUNTER_FREECOUNT_S 0U
|
||||
#define ADC_COUNTER_FREECOUNT_M 0xFFFU // ADC Free Running Counter Value
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCREV register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_REV_TYPE_S 0U
|
||||
#define ADC_REV_TYPE_M 0xFFU // ADC Type
|
||||
#define ADC_REV_REV_S 8U
|
||||
#define ADC_REV_REV_M 0xFF00U // ADC Revision
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCOFFTRIM register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_OFFTRIM_OFFTRIM_S 0U
|
||||
#define ADC_OFFTRIM_OFFTRIM_M 0xFFU // ADC Offset Trim
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB1CONFIG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB1CONFIG_CONFIG_S 0U
|
||||
#define ADC_PPB1CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 1 Configuration
|
||||
#define ADC_PPB1CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 1 Two's Complement Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB1STAMP register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB1STAMP_DLYSTAMP_S 0U
|
||||
#define ADC_PPB1STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 1 Delay Time Stamp
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB1OFFCAL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB1OFFCAL_OFFCAL_S 0U
|
||||
#define ADC_PPB1OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB1TRIPHI register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB1TRIPHI_LIMITHI_S 0U
|
||||
#define ADC_PPB1TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 1 Trip High Limit
|
||||
#define ADC_PPB1TRIPHI_HSIGN 0x10000U // High Limit Sign Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB1TRIPLO register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB1TRIPLO_LIMITLO_S 0U
|
||||
#define ADC_PPB1TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 1 Trip Low Limit
|
||||
#define ADC_PPB1TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit
|
||||
#define ADC_PPB1TRIPLO_REQSTAMP_S 20U
|
||||
#define ADC_PPB1TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 1 Request Time Stamp
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB2CONFIG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB2CONFIG_CONFIG_S 0U
|
||||
#define ADC_PPB2CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 2 Configuration
|
||||
#define ADC_PPB2CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 2 Two's Complement Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB2STAMP register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB2STAMP_DLYSTAMP_S 0U
|
||||
#define ADC_PPB2STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 2 Delay Time Stamp
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB2OFFCAL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB2OFFCAL_OFFCAL_S 0U
|
||||
#define ADC_PPB2OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB2TRIPHI register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB2TRIPHI_LIMITHI_S 0U
|
||||
#define ADC_PPB2TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 2 Trip High Limit
|
||||
#define ADC_PPB2TRIPHI_HSIGN 0x10000U // High Limit Sign Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB2TRIPLO register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB2TRIPLO_LIMITLO_S 0U
|
||||
#define ADC_PPB2TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 2 Trip Low Limit
|
||||
#define ADC_PPB2TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit
|
||||
#define ADC_PPB2TRIPLO_REQSTAMP_S 20U
|
||||
#define ADC_PPB2TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 2 Request Time Stamp
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB3CONFIG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB3CONFIG_CONFIG_S 0U
|
||||
#define ADC_PPB3CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 3 Configuration
|
||||
#define ADC_PPB3CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 3 Two's Complement Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB3STAMP register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB3STAMP_DLYSTAMP_S 0U
|
||||
#define ADC_PPB3STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 3 Delay Time Stamp
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB3OFFCAL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB3OFFCAL_OFFCAL_S 0U
|
||||
#define ADC_PPB3OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB3TRIPHI register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB3TRIPHI_LIMITHI_S 0U
|
||||
#define ADC_PPB3TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 3 Trip High Limit
|
||||
#define ADC_PPB3TRIPHI_HSIGN 0x10000U // High Limit Sign Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB3TRIPLO register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB3TRIPLO_LIMITLO_S 0U
|
||||
#define ADC_PPB3TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 3 Trip Low Limit
|
||||
#define ADC_PPB3TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit
|
||||
#define ADC_PPB3TRIPLO_REQSTAMP_S 20U
|
||||
#define ADC_PPB3TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 3 Request Time Stamp
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB4CONFIG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB4CONFIG_CONFIG_S 0U
|
||||
#define ADC_PPB4CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 4 Configuration
|
||||
#define ADC_PPB4CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 4 Two's Complement Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB4STAMP register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB4STAMP_DLYSTAMP_S 0U
|
||||
#define ADC_PPB4STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 4 Delay Time Stamp
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB4OFFCAL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB4OFFCAL_OFFCAL_S 0U
|
||||
#define ADC_PPB4OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB4TRIPHI register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB4TRIPHI_LIMITHI_S 0U
|
||||
#define ADC_PPB4TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 4 Trip High Limit
|
||||
#define ADC_PPB4TRIPHI_HSIGN 0x10000U // High Limit Sign Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB4TRIPLO register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB4TRIPLO_LIMITLO_S 0U
|
||||
#define ADC_PPB4TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 4 Trip Low Limit
|
||||
#define ADC_PPB4TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit
|
||||
#define ADC_PPB4TRIPLO_REQSTAMP_S 20U
|
||||
#define ADC_PPB4TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 4 Request Time Stamp
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB1RESULT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB1RESULT_PPBRESULT_S 0U
|
||||
#define ADC_PPB1RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result
|
||||
#define ADC_PPB1RESULT_SIGN_S 16U
|
||||
#define ADC_PPB1RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB2RESULT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB2RESULT_PPBRESULT_S 0U
|
||||
#define ADC_PPB2RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result
|
||||
#define ADC_PPB2RESULT_SIGN_S 16U
|
||||
#define ADC_PPB2RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB3RESULT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB3RESULT_PPBRESULT_S 0U
|
||||
#define ADC_PPB3RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result
|
||||
#define ADC_PPB3RESULT_SIGN_S 16U
|
||||
#define ADC_PPB3RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ADCPPB4RESULT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ADC_PPB4RESULT_PPBRESULT_S 0U
|
||||
#define ADC_PPB4RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result
|
||||
#define ADC_PPB4RESULT_SIGN_S 16U
|
||||
#define ADC_PPB4RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,143 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_asysctl.h
|
||||
//
|
||||
// TITLE: Definitions for the ASYSCTL registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_ASYSCTL_H
|
||||
#define HW_ASYSCTL_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the ASYSCTL register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ASYSCTL_O_INTOSC1TRIM 0x20U // Internal Oscillator 1 Trim Register
|
||||
#define ASYSCTL_O_INTOSC2TRIM 0x22U // Internal Oscillator 2 Trim Register
|
||||
#define ASYSCTL_O_TSNSCTL 0x26U // Temperature Sensor Control Register
|
||||
#define ASYSCTL_O_LOCK 0x2EU // Lock Register
|
||||
#define ASYSCTL_O_ANAREFTRIMA 0x36U // Analog Reference Trim A Register
|
||||
#define ASYSCTL_O_ANAREFTRIMB 0x38U // Analog Reference Trim B Register
|
||||
#define ASYSCTL_O_ANAREFTRIMC 0x3AU // Analog Reference Trim C Register
|
||||
#define ASYSCTL_O_ANAREFTRIMD 0x3CU // Analog Reference Trim D Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the INTOSC1TRIM register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_S 0U
|
||||
#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the INTOSC2TRIM register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_S 0U
|
||||
#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TSNSCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ASYSCTL_TSNSCTL_ENABLE 0x1U // Temperature Sensor Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ASYSCTL_LOCK_TSNSCTL 0x8U // Temperature Sensor Control Register Lock
|
||||
#define ASYSCTL_LOCK_ANAREFTRIMA 0x800000U // Analog Reference A Trim Register Lock
|
||||
#define ASYSCTL_LOCK_ANAREFTRIMB 0x1000000U // Analog Reference B Trim Register Lock
|
||||
#define ASYSCTL_LOCK_ANAREFTRIMC 0x2000000U // Analog Reference C Trim Register Lock
|
||||
#define ASYSCTL_LOCK_ANAREFTRIMD 0x4000000U // Analog Reference D Trim Register Lock
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ANAREFTRIMA register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_S 0U
|
||||
#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_M 0x3FU // Bandgap Value Trim
|
||||
#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_S 6U
|
||||
#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim
|
||||
#define ASYSCTL_ANAREFTRIMA_IREFTRIM_S 11U
|
||||
#define ASYSCTL_ANAREFTRIMA_IREFTRIM_M 0xF800U // Reference Current Trim
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ANAREFTRIMB register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_S 0U
|
||||
#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_M 0x3FU // Bandgap Value Trim
|
||||
#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_S 6U
|
||||
#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim
|
||||
#define ASYSCTL_ANAREFTRIMB_IREFTRIM_S 11U
|
||||
#define ASYSCTL_ANAREFTRIMB_IREFTRIM_M 0xF800U // Reference Current Trim
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ANAREFTRIMC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_S 0U
|
||||
#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_M 0x3FU // Bandgap Value Trim
|
||||
#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_S 6U
|
||||
#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim
|
||||
#define ASYSCTL_ANAREFTRIMC_IREFTRIM_S 11U
|
||||
#define ASYSCTL_ANAREFTRIMC_IREFTRIM_M 0xF800U // Reference Current Trim
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ANAREFTRIMD register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_S 0U
|
||||
#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_M 0x3FU // Bandgap Value Trim
|
||||
#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_S 6U
|
||||
#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim
|
||||
#define ASYSCTL_ANAREFTRIMD_IREFTRIM_S 11U
|
||||
#define ASYSCTL_ANAREFTRIMD_IREFTRIM_M 0xF800U // Reference Current Trim
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,512 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_can.h
|
||||
//
|
||||
// TITLE: Definitions for the CAN registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_CAN_H
|
||||
#define HW_CAN_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the CAN register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_O_CTL 0x0U // CAN Control Register
|
||||
#define CAN_O_ES 0x4U // Error and Status Register
|
||||
#define CAN_O_ERRC 0x8U // Error Counter Register
|
||||
#define CAN_O_BTR 0xCU // Bit Timing Register
|
||||
#define CAN_O_INT 0x10U // Interrupt Register
|
||||
#define CAN_O_TEST 0x14U // Test Register
|
||||
#define CAN_O_PERR 0x1CU // CAN Parity Error Code Register
|
||||
#define CAN_O_RAM_INIT 0x40U // CAN RAM Initialization Register
|
||||
#define CAN_O_GLB_INT_EN 0x50U // CAN Global Interrupt Enable Register
|
||||
#define CAN_O_GLB_INT_FLG 0x54U // CAN Global Interrupt Flag Register
|
||||
#define CAN_O_GLB_INT_CLR 0x58U // CAN Global Interrupt Clear Register
|
||||
#define CAN_O_ABOTR 0x80U // Auto-Bus-On Time Register
|
||||
#define CAN_O_TXRQ_X 0x84U // CAN Transmission Request Register
|
||||
#define CAN_O_TXRQ_21 0x88U // CAN Transmission Request 2_1 Register
|
||||
#define CAN_O_NDAT_X 0x98U // CAN New Data Register
|
||||
#define CAN_O_NDAT_21 0x9CU // CAN New Data 2_1 Register
|
||||
#define CAN_O_IPEN_X 0xACU // CAN Interrupt Pending Register
|
||||
#define CAN_O_IPEN_21 0xB0U // CAN Interrupt Pending 2_1 Register
|
||||
#define CAN_O_MVAL_X 0xC0U // CAN Message Valid Register
|
||||
#define CAN_O_MVAL_21 0xC4U // CAN Message Valid 2_1 Register
|
||||
#define CAN_O_IP_MUX21 0xD8U // CAN Interrupt Multiplexer 2_1 Register
|
||||
#define CAN_O_IF1CMD 0x100U // IF1 Command Register
|
||||
#define CAN_O_IF1MSK 0x104U // IF1 Mask Register
|
||||
#define CAN_O_IF1ARB 0x108U // IF1 Arbitration Register
|
||||
#define CAN_O_IF1MCTL 0x10CU // IF1 Message Control Register
|
||||
#define CAN_O_IF1DATA 0x110U // IF1 Data A Register
|
||||
#define CAN_O_IF1DATB 0x114U // IF1 Data B Register
|
||||
#define CAN_O_IF2CMD 0x120U // IF2 Command Register
|
||||
#define CAN_O_IF2MSK 0x124U // IF2 Mask Register
|
||||
#define CAN_O_IF2ARB 0x128U // IF2 Arbitration Register
|
||||
#define CAN_O_IF2MCTL 0x12CU // IF2 Message Control Register
|
||||
#define CAN_O_IF2DATA 0x130U // IF2 Data A Register
|
||||
#define CAN_O_IF2DATB 0x134U // IF2 Data B Register
|
||||
#define CAN_O_IF3OBS 0x140U // IF3 Observation Register
|
||||
#define CAN_O_IF3MSK 0x144U // IF3 Mask Register
|
||||
#define CAN_O_IF3ARB 0x148U // IF3 Arbitration Register
|
||||
#define CAN_O_IF3MCTL 0x14CU // IF3 Message Control Register
|
||||
#define CAN_O_IF3DATA 0x150U // IF3 Data A Register
|
||||
#define CAN_O_IF3DATB 0x154U // IF3 Data B Register
|
||||
#define CAN_O_IF3UPD 0x160U // IF3 Update Enable Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_CTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_CTL_INIT 0x1U // Initialization
|
||||
#define CAN_CTL_IE0 0x2U // Interrupt line 0 Enable
|
||||
#define CAN_CTL_SIE 0x4U // Status Change Interrupt Enable
|
||||
#define CAN_CTL_EIE 0x8U // Error Interrupt Enable
|
||||
#define CAN_CTL_DAR 0x20U // Disable Automatic Retransmission
|
||||
#define CAN_CTL_CCE 0x40U // Configuration Change Enable
|
||||
#define CAN_CTL_TEST 0x80U // Test Mode Enable
|
||||
#define CAN_CTL_IDS 0x100U // Interruption Debug Support Enable
|
||||
#define CAN_CTL_ABO 0x200U // Auto-Bus-On Enable
|
||||
#define CAN_CTL_PMD_S 10U
|
||||
#define CAN_CTL_PMD_M 0x3C00U // Parity on/off
|
||||
#define CAN_CTL_SWR 0x8000U // SW Reset Enable
|
||||
#define CAN_CTL_INITDBG 0x10000U // Debug Mode Status
|
||||
#define CAN_CTL_IE1 0x20000U // Interrupt line 1 Enable Disabled
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_ES register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_ES_LEC_S 0U
|
||||
#define CAN_ES_LEC_M 0x7U // Last Error Code
|
||||
#define CAN_ES_TXOK 0x8U // Transmission status
|
||||
#define CAN_ES_RXOK 0x10U // Reception status
|
||||
#define CAN_ES_EPASS 0x20U // Error Passive State
|
||||
#define CAN_ES_EWARN 0x40U // Warning State
|
||||
#define CAN_ES_BOFF 0x80U // Bus-Off State
|
||||
#define CAN_ES_PER 0x100U // Parity Error Detected
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_ERRC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_ERRC_TEC_S 0U
|
||||
#define CAN_ERRC_TEC_M 0xFFU // Transmit Error Counter
|
||||
#define CAN_ERRC_REC_S 8U
|
||||
#define CAN_ERRC_REC_M 0x7F00U // Receive Error Counter
|
||||
#define CAN_ERRC_RP 0x8000U // Receive Error Passive
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_BTR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_BTR_BRP_S 0U
|
||||
#define CAN_BTR_BRP_M 0x3FU // Baud Rate Prescaler
|
||||
#define CAN_BTR_SJW_S 6U
|
||||
#define CAN_BTR_SJW_M 0xC0U // Synchronization Jump Width
|
||||
#define CAN_BTR_TSEG1_S 8U
|
||||
#define CAN_BTR_TSEG1_M 0xF00U // Time segment
|
||||
#define CAN_BTR_TSEG2_S 12U
|
||||
#define CAN_BTR_TSEG2_M 0x7000U // Time segment
|
||||
#define CAN_BTR_BRPE_S 16U
|
||||
#define CAN_BTR_BRPE_M 0xF0000U // Baud Rate Prescaler Extension
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_INT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_INT_INT0ID_S 0U
|
||||
#define CAN_INT_INT0ID_M 0xFFFFU // Interrupt Identifier
|
||||
#define CAN_INT_INT1ID_S 16U
|
||||
#define CAN_INT_INT1ID_M 0xFF0000U // Interrupt 1 Identifier
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_TEST register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_TEST_SILENT 0x8U // Silent Mode
|
||||
#define CAN_TEST_LBACK 0x10U // Loopback Mode
|
||||
#define CAN_TEST_TX_S 5U
|
||||
#define CAN_TEST_TX_M 0x60U // CANTX Pin Control
|
||||
#define CAN_TEST_RX 0x80U // CANRX Pin Status
|
||||
#define CAN_TEST_EXL 0x100U // External Loopback Mode
|
||||
#define CAN_TEST_RDA 0x200U // RAM Direct Access Enable:
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_PERR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_PERR_MSG_NUM_S 0U
|
||||
#define CAN_PERR_MSG_NUM_M 0xFFU // Message Number
|
||||
#define CAN_PERR_WORD_NUM_S 8U
|
||||
#define CAN_PERR_WORD_NUM_M 0x700U // Word Number
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_RAM_INIT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_RAM_INIT_KEY0 0x1U // KEY0
|
||||
#define CAN_RAM_INIT_KEY1 0x2U // KEY1
|
||||
#define CAN_RAM_INIT_KEY2 0x4U // KEY2
|
||||
#define CAN_RAM_INIT_KEY3 0x8U // KEY3
|
||||
#define CAN_RAM_INIT_CAN_RAM_INIT 0x10U // Initialize CAN Mailbox RAM
|
||||
#define CAN_RAM_INIT_RAM_INIT_DONE 0x20U // CAN RAM initialization complete
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_GLB_INT_EN register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_GLB_INT_EN_GLBINT0_EN 0x1U // Global Interrupt Enable for CANINT0
|
||||
#define CAN_GLB_INT_EN_GLBINT1_EN 0x2U // Global Interrupt Enable for CANINT1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_GLB_INT_FLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_GLB_INT_FLG_INT0_FLG 0x1U // Global Interrupt Flag for CANINT0
|
||||
#define CAN_GLB_INT_FLG_INT1_FLG 0x2U // Global Interrupt Flag for CANINT1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_GLB_INT_CLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_GLB_INT_CLR_INT0_FLG_CLR 0x1U // Global Interrupt flag clear for CANINT0
|
||||
#define CAN_GLB_INT_CLR_INT1_FLG_CLR 0x2U // Global Interrupt flag clear for CANINT1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_TXRQ_X register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_TXRQ_X_TXRQSTREG1_S 0U
|
||||
#define CAN_TXRQ_X_TXRQSTREG1_M 0x3U // Transmit Request Register 1
|
||||
#define CAN_TXRQ_X_TXRQSTREG2_S 2U
|
||||
#define CAN_TXRQ_X_TXRQSTREG2_M 0xCU // Transmit Request Register 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_NDAT_X register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_NDAT_X_NEWDATREG1_S 0U
|
||||
#define CAN_NDAT_X_NEWDATREG1_M 0x3U // New Data Register 1
|
||||
#define CAN_NDAT_X_NEWDATREG2_S 2U
|
||||
#define CAN_NDAT_X_NEWDATREG2_M 0xCU // New Data Register 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IPEN_X register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IPEN_X_INTPNDREG1_S 0U
|
||||
#define CAN_IPEN_X_INTPNDREG1_M 0x3U // Interrupt Pending Register 1
|
||||
#define CAN_IPEN_X_INTPNDREG2_S 2U
|
||||
#define CAN_IPEN_X_INTPNDREG2_M 0xCU // Interrupt Pending Register 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_MVAL_X register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_MVAL_X_MSGVALREG1_S 0U
|
||||
#define CAN_MVAL_X_MSGVALREG1_M 0x3U // Message Valid Register 1
|
||||
#define CAN_MVAL_X_MSGVALREG2_S 2U
|
||||
#define CAN_MVAL_X_MSGVALREG2_M 0xCU // Message Valid Register 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF1CMD register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF1CMD_MSG_NUM_S 0U
|
||||
#define CAN_IF1CMD_MSG_NUM_M 0xFFU // Message Number
|
||||
#define CAN_IF1CMD_BUSY 0x8000U // Busy Flag
|
||||
#define CAN_IF1CMD_DATA_B 0x10000U // Access Data Bytes 4-7
|
||||
#define CAN_IF1CMD_DATA_A 0x20000U // Access Data Bytes 0-3
|
||||
#define CAN_IF1CMD_TXRQST 0x40000U // Access Transmission Request Bit
|
||||
#define CAN_IF1CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit
|
||||
#define CAN_IF1CMD_CONTROL 0x100000U // Access Control Bits
|
||||
#define CAN_IF1CMD_ARB 0x200000U // Access Arbitration Bits
|
||||
#define CAN_IF1CMD_MASK 0x400000U // Access Mask Bits
|
||||
#define CAN_IF1CMD_DIR 0x800000U // Write/Read Direction
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF1MSK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF1MSK_MSK_S 0U
|
||||
#define CAN_IF1MSK_MSK_M 0x1FFFFFFFU // Identifier Mask
|
||||
#define CAN_IF1MSK_MDIR 0x40000000U // Mask Message Direction
|
||||
#define CAN_IF1MSK_MXTD 0x80000000U // Mask Extended Identifier
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF1ARB register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF1ARB_ID_S 0U
|
||||
#define CAN_IF1ARB_ID_M 0x1FFFFFFFU // `
|
||||
#define CAN_IF1ARB_DIR 0x20000000U // Message Direction
|
||||
#define CAN_IF1ARB_XTD 0x40000000U // Extended Identifier
|
||||
#define CAN_IF1ARB_MSGVAL 0x80000000U // Message Valid
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF1MCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF1MCTL_DLC_S 0U
|
||||
#define CAN_IF1MCTL_DLC_M 0xFU // Data length code
|
||||
#define CAN_IF1MCTL_EOB 0x80U // End of Block
|
||||
#define CAN_IF1MCTL_TXRQST 0x100U // Transmit Request
|
||||
#define CAN_IF1MCTL_RMTEN 0x200U // Remote Enable
|
||||
#define CAN_IF1MCTL_RXIE 0x400U // Receive Interrupt Enable
|
||||
#define CAN_IF1MCTL_TXIE 0x800U // Transmit Interrupt Enable
|
||||
#define CAN_IF1MCTL_UMASK 0x1000U // Use Acceptance Mask
|
||||
#define CAN_IF1MCTL_INTPND 0x2000U // Interrupt Pending
|
||||
#define CAN_IF1MCTL_MSGLST 0x4000U // Message Lost
|
||||
#define CAN_IF1MCTL_NEWDAT 0x8000U // New Data
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF1DATA register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF1DATA_DATA_0_S 0U
|
||||
#define CAN_IF1DATA_DATA_0_M 0xFFU // Data Byte 0
|
||||
#define CAN_IF1DATA_DATA_1_S 8U
|
||||
#define CAN_IF1DATA_DATA_1_M 0xFF00U // Data Byte 1
|
||||
#define CAN_IF1DATA_DATA_2_S 16U
|
||||
#define CAN_IF1DATA_DATA_2_M 0xFF0000U // Data Byte 2
|
||||
#define CAN_IF1DATA_DATA_3_S 24U
|
||||
#define CAN_IF1DATA_DATA_3_M 0xFF000000U // Data Byte 3
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF1DATB register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF1DATB_DATA_4_S 0U
|
||||
#define CAN_IF1DATB_DATA_4_M 0xFFU // Data Byte 4
|
||||
#define CAN_IF1DATB_DATA_5_S 8U
|
||||
#define CAN_IF1DATB_DATA_5_M 0xFF00U // Data Byte 5
|
||||
#define CAN_IF1DATB_DATA_6_S 16U
|
||||
#define CAN_IF1DATB_DATA_6_M 0xFF0000U // Data Byte 6
|
||||
#define CAN_IF1DATB_DATA_7_S 24U
|
||||
#define CAN_IF1DATB_DATA_7_M 0xFF000000U // Data Byte 7
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF2CMD register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF2CMD_MSG_NUM_S 0U
|
||||
#define CAN_IF2CMD_MSG_NUM_M 0xFFU // Message Number
|
||||
#define CAN_IF2CMD_BUSY 0x8000U // Busy Flag
|
||||
#define CAN_IF2CMD_DATA_B 0x10000U // Access Data Bytes 4-7
|
||||
#define CAN_IF2CMD_DATA_A 0x20000U // Access Data Bytes 0-3
|
||||
#define CAN_IF2CMD_TXRQST 0x40000U // Access Transmission Request Bit
|
||||
#define CAN_IF2CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit
|
||||
#define CAN_IF2CMD_CONTROL 0x100000U // Access Control Bits
|
||||
#define CAN_IF2CMD_ARB 0x200000U // Access Arbitration Bits
|
||||
#define CAN_IF2CMD_MASK 0x400000U // Access Mask Bits
|
||||
#define CAN_IF2CMD_DIR 0x800000U // Write/Read Direction
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF2MSK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF2MSK_MSK_S 0U
|
||||
#define CAN_IF2MSK_MSK_M 0x1FFFFFFFU // Identifier Mask
|
||||
#define CAN_IF2MSK_MDIR 0x40000000U // Mask Message Direction
|
||||
#define CAN_IF2MSK_MXTD 0x80000000U // Mask Extended Identifier
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF2ARB register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF2ARB_ID_S 0U
|
||||
#define CAN_IF2ARB_ID_M 0x1FFFFFFFU // Message Identifier
|
||||
#define CAN_IF2ARB_DIR 0x20000000U // Message Direction
|
||||
#define CAN_IF2ARB_XTD 0x40000000U // Extended Identifier
|
||||
#define CAN_IF2ARB_MSGVAL 0x80000000U // Message Valid
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF2MCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF2MCTL_DLC_S 0U
|
||||
#define CAN_IF2MCTL_DLC_M 0xFU // Data length code
|
||||
#define CAN_IF2MCTL_EOB 0x80U // End of Block
|
||||
#define CAN_IF2MCTL_TXRQST 0x100U // Transmit Request
|
||||
#define CAN_IF2MCTL_RMTEN 0x200U // Remote Enable
|
||||
#define CAN_IF2MCTL_RXIE 0x400U // Receive Interrupt Enable
|
||||
#define CAN_IF2MCTL_TXIE 0x800U // Transmit Interrupt Enable
|
||||
#define CAN_IF2MCTL_UMASK 0x1000U // Use Acceptance Mask
|
||||
#define CAN_IF2MCTL_INTPND 0x2000U // Interrupt Pending
|
||||
#define CAN_IF2MCTL_MSGLST 0x4000U // Message Lost
|
||||
#define CAN_IF2MCTL_NEWDAT 0x8000U // New Data
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF2DATA register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF2DATA_DATA_0_S 0U
|
||||
#define CAN_IF2DATA_DATA_0_M 0xFFU // Data Byte 0
|
||||
#define CAN_IF2DATA_DATA_1_S 8U
|
||||
#define CAN_IF2DATA_DATA_1_M 0xFF00U // Data Byte 1
|
||||
#define CAN_IF2DATA_DATA_2_S 16U
|
||||
#define CAN_IF2DATA_DATA_2_M 0xFF0000U // Data Byte 2
|
||||
#define CAN_IF2DATA_DATA_3_S 24U
|
||||
#define CAN_IF2DATA_DATA_3_M 0xFF000000U // Data Byte 3
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF2DATB register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF2DATB_DATA_4_S 0U
|
||||
#define CAN_IF2DATB_DATA_4_M 0xFFU // Data Byte 4
|
||||
#define CAN_IF2DATB_DATA_5_S 8U
|
||||
#define CAN_IF2DATB_DATA_5_M 0xFF00U // Data Byte 5
|
||||
#define CAN_IF2DATB_DATA_6_S 16U
|
||||
#define CAN_IF2DATB_DATA_6_M 0xFF0000U // Data Byte 6
|
||||
#define CAN_IF2DATB_DATA_7_S 24U
|
||||
#define CAN_IF2DATB_DATA_7_M 0xFF000000U // Data Byte 7
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF3OBS register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF3OBS_MASK 0x1U // Mask data read observation
|
||||
#define CAN_IF3OBS_ARB 0x2U // Arbitration data read observation
|
||||
#define CAN_IF3OBS_CTRL 0x4U // Ctrl read observation
|
||||
#define CAN_IF3OBS_DATA_A 0x8U // Data A read observation
|
||||
#define CAN_IF3OBS_DATA_B 0x10U // Data B read observation
|
||||
#define CAN_IF3OBS_IF3SM 0x100U // IF3 Status of Mask data read access
|
||||
#define CAN_IF3OBS_IF3SA 0x200U // IF3 Status of Arbitration data read access
|
||||
#define CAN_IF3OBS_IF3SC 0x400U // IF3 Status of Control bits read access
|
||||
#define CAN_IF3OBS_IF3SDA 0x800U // IF3 Status of Data A read access
|
||||
#define CAN_IF3OBS_IF3SDB 0x1000U // IF3 Status of Data B read access
|
||||
#define CAN_IF3OBS_IF3UPD 0x8000U // IF3 Update Data
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF3MSK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF3MSK_MSK_S 0U
|
||||
#define CAN_IF3MSK_MSK_M 0x1FFFFFFFU // Mask
|
||||
#define CAN_IF3MSK_MDIR 0x40000000U // Mask Message Direction
|
||||
#define CAN_IF3MSK_MXTD 0x80000000U // Mask Extended Identifier
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF3ARB register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF3ARB_ID_S 0U
|
||||
#define CAN_IF3ARB_ID_M 0x1FFFFFFFU // Message Identifier
|
||||
#define CAN_IF3ARB_DIR 0x20000000U // Message Direction
|
||||
#define CAN_IF3ARB_XTD 0x40000000U // Extended Identifier
|
||||
#define CAN_IF3ARB_MSGVAL 0x80000000U // Message Valid
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF3MCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF3MCTL_DLC_S 0U
|
||||
#define CAN_IF3MCTL_DLC_M 0xFU // Data length code
|
||||
#define CAN_IF3MCTL_EOB 0x80U // End of Block
|
||||
#define CAN_IF3MCTL_TXRQST 0x100U // Transmit Request
|
||||
#define CAN_IF3MCTL_RMTEN 0x200U // Remote Enable
|
||||
#define CAN_IF3MCTL_RXIE 0x400U // Receive Interrupt Enable
|
||||
#define CAN_IF3MCTL_TXIE 0x800U // Transmit Interrupt Enable
|
||||
#define CAN_IF3MCTL_UMASK 0x1000U // Use Acceptance Mask
|
||||
#define CAN_IF3MCTL_INTPND 0x2000U // Interrupt Pending
|
||||
#define CAN_IF3MCTL_MSGLST 0x4000U // Message Lost
|
||||
#define CAN_IF3MCTL_NEWDAT 0x8000U // New Data
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF3DATA register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF3DATA_DATA_0_S 0U
|
||||
#define CAN_IF3DATA_DATA_0_M 0xFFU // Data Byte 0
|
||||
#define CAN_IF3DATA_DATA_1_S 8U
|
||||
#define CAN_IF3DATA_DATA_1_M 0xFF00U // Data Byte 1
|
||||
#define CAN_IF3DATA_DATA_2_S 16U
|
||||
#define CAN_IF3DATA_DATA_2_M 0xFF0000U // Data Byte 2
|
||||
#define CAN_IF3DATA_DATA_3_S 24U
|
||||
#define CAN_IF3DATA_DATA_3_M 0xFF000000U // Data Byte 3
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_IF3DATB register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CAN_IF3DATB_DATA_4_S 0U
|
||||
#define CAN_IF3DATB_DATA_4_M 0xFFU // Data Byte 4
|
||||
#define CAN_IF3DATB_DATA_5_S 8U
|
||||
#define CAN_IF3DATB_DATA_5_M 0xFF00U // Data Byte 5
|
||||
#define CAN_IF3DATB_DATA_6_S 16U
|
||||
#define CAN_IF3DATB_DATA_6_M 0xFF0000U // Data Byte 6
|
||||
#define CAN_IF3DATB_DATA_7_S 24U
|
||||
#define CAN_IF3DATB_DATA_7_M 0xFF000000U // Data Byte 7
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,239 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_cla.h
|
||||
//
|
||||
// TITLE: Definitions for the CLA registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_CLA_H
|
||||
#define HW_CLA_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the CLA register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#ifndef __TMS320C28XX_CLA__
|
||||
#define CLA_O_MVECT1 0x0U // Task Interrupt Vector
|
||||
#define CLA_O_MVECT2 0x1U // Task Interrupt Vector
|
||||
#define CLA_O_MVECT3 0x2U // Task Interrupt Vector
|
||||
#define CLA_O_MVECT4 0x3U // Task Interrupt Vector
|
||||
#define CLA_O_MVECT5 0x4U // Task Interrupt Vector
|
||||
#define CLA_O_MVECT6 0x5U // Task Interrupt Vector
|
||||
#define CLA_O_MVECT7 0x6U // Task Interrupt Vector
|
||||
#define CLA_O_MVECT8 0x7U // Task Interrupt Vector
|
||||
#define CLA_O_MCTL 0x10U // Control Register
|
||||
#define CLA_O_MIFR 0x20U // Interrupt Flag Register
|
||||
#define CLA_O_MIOVF 0x21U // Interrupt Overflow Flag Register
|
||||
#define CLA_O_MIFRC 0x22U // Interrupt Force Register
|
||||
#define CLA_O_MICLR 0x23U // Interrupt Flag Clear Register
|
||||
#define CLA_O_MICLROVF 0x24U // Interrupt Overflow Flag Clear Register
|
||||
#define CLA_O_MIER 0x25U // Interrupt Enable Register
|
||||
#define CLA_O_MIRUN 0x26U // Interrupt Run Status Register
|
||||
#define CLA_O_MPC 0x28U // CLA Program Counter
|
||||
#define CLA_O_MAR0 0x2AU // CLA Auxiliary Register 0
|
||||
#define CLA_O_MAR1 0x2BU // CLA Auxiliary Register 1
|
||||
#define CLA_O_MSTF 0x2EU // CLA Floating-Point Status Register
|
||||
#define CLA_O_MR0 0x30U // CLA Floating-Point Result Register 0
|
||||
#define CLA_O_MR1 0x34U // CLA Floating-Point Result Register 1
|
||||
#define CLA_O_MR2 0x38U // CLA Floating-Point Result Register 2
|
||||
#define CLA_O_MR3 0x3CU // CLA Floating-Point Result Register 3
|
||||
#endif
|
||||
|
||||
#ifdef __TMS320C28XX_CLA__
|
||||
#define CLA_O_SOFTINTEN 0x0U // CLA Software Interrupt Enable Register
|
||||
#define CLA_O_SOFTINTFRC 0x2U // CLA Software Interrupt Force Register
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __TMS320C28XX_CLA__
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLA_MCTL_HARDRESET 0x1U // Hard Reset
|
||||
#define CLA_MCTL_SOFTRESET 0x2U // Soft Reset
|
||||
#define CLA_MCTL_IACKE 0x4U // IACK enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MIFR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLA_MIFR_INT1 0x1U // Task 1 Interrupt Flag
|
||||
#define CLA_MIFR_INT2 0x2U // Task 2 Interrupt Flag
|
||||
#define CLA_MIFR_INT3 0x4U // Task 3 Interrupt Flag
|
||||
#define CLA_MIFR_INT4 0x8U // Task 4 Interrupt Flag
|
||||
#define CLA_MIFR_INT5 0x10U // Task 5 Interrupt Flag
|
||||
#define CLA_MIFR_INT6 0x20U // Task 6 Interrupt Flag
|
||||
#define CLA_MIFR_INT7 0x40U // Task 7 Interrupt Flag
|
||||
#define CLA_MIFR_INT8 0x80U // Task 8 Interrupt Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MIOVF register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLA_MIOVF_INT1 0x1U // Task 1 Interrupt Overflow Flag
|
||||
#define CLA_MIOVF_INT2 0x2U // Task 2 Interrupt Overflow Flag
|
||||
#define CLA_MIOVF_INT3 0x4U // Task 3 Interrupt Overflow Flag
|
||||
#define CLA_MIOVF_INT4 0x8U // Task 4 Interrupt Overflow Flag
|
||||
#define CLA_MIOVF_INT5 0x10U // Task 5 Interrupt Overflow Flag
|
||||
#define CLA_MIOVF_INT6 0x20U // Task 6 Interrupt Overflow Flag
|
||||
#define CLA_MIOVF_INT7 0x40U // Task 7 Interrupt Overflow Flag
|
||||
#define CLA_MIOVF_INT8 0x80U // Task 8 Interrupt Overflow Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MIFRC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLA_MIFRC_INT1 0x1U // Task 1 Interrupt Force
|
||||
#define CLA_MIFRC_INT2 0x2U // Task 2 Interrupt Force
|
||||
#define CLA_MIFRC_INT3 0x4U // Task 3 Interrupt Force
|
||||
#define CLA_MIFRC_INT4 0x8U // Task 4 Interrupt Force
|
||||
#define CLA_MIFRC_INT5 0x10U // Task 5 Interrupt Force
|
||||
#define CLA_MIFRC_INT6 0x20U // Task 6 Interrupt Force
|
||||
#define CLA_MIFRC_INT7 0x40U // Task 7 Interrupt Force
|
||||
#define CLA_MIFRC_INT8 0x80U // Task 8 Interrupt Force
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MICLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLA_MICLR_INT1 0x1U // Task 1 Interrupt Flag Clear
|
||||
#define CLA_MICLR_INT2 0x2U // Task 2 Interrupt Flag Clear
|
||||
#define CLA_MICLR_INT3 0x4U // Task 3 Interrupt Flag Clear
|
||||
#define CLA_MICLR_INT4 0x8U // Task 4 Interrupt Flag Clear
|
||||
#define CLA_MICLR_INT5 0x10U // Task 5 Interrupt Flag Clear
|
||||
#define CLA_MICLR_INT6 0x20U // Task 6 Interrupt Flag Clear
|
||||
#define CLA_MICLR_INT7 0x40U // Task 7 Interrupt Flag Clear
|
||||
#define CLA_MICLR_INT8 0x80U // Task 8 Interrupt Flag Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MICLROVF register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLA_MICLROVF_INT1 0x1U // Task 1 Interrupt Overflow Flag Clear
|
||||
#define CLA_MICLROVF_INT2 0x2U // Task 2 Interrupt Overflow Flag Clear
|
||||
#define CLA_MICLROVF_INT3 0x4U // Task 3 Interrupt Overflow Flag Clear
|
||||
#define CLA_MICLROVF_INT4 0x8U // Task 4 Interrupt Overflow Flag Clear
|
||||
#define CLA_MICLROVF_INT5 0x10U // Task 5 Interrupt Overflow Flag Clear
|
||||
#define CLA_MICLROVF_INT6 0x20U // Task 6 Interrupt Overflow Flag Clear
|
||||
#define CLA_MICLROVF_INT7 0x40U // Task 7 Interrupt Overflow Flag Clear
|
||||
#define CLA_MICLROVF_INT8 0x80U // Task 8 Interrupt Overflow Flag Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MIER register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLA_MIER_INT1 0x1U // Task 1 Interrupt Enable
|
||||
#define CLA_MIER_INT2 0x2U // Task 2 Interrupt Enable
|
||||
#define CLA_MIER_INT3 0x4U // Task 3 Interrupt Enable
|
||||
#define CLA_MIER_INT4 0x8U // Task 4 Interrupt Enable
|
||||
#define CLA_MIER_INT5 0x10U // Task 5 Interrupt Enable
|
||||
#define CLA_MIER_INT6 0x20U // Task 6 Interrupt Enable
|
||||
#define CLA_MIER_INT7 0x40U // Task 7 Interrupt Enable
|
||||
#define CLA_MIER_INT8 0x80U // Task 8 Interrupt Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MIRUN register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLA_MIRUN_INT1 0x1U // Task 1 Run Status
|
||||
#define CLA_MIRUN_INT2 0x2U // Task 2 Run Status
|
||||
#define CLA_MIRUN_INT3 0x4U // Task 3 Run Status
|
||||
#define CLA_MIRUN_INT4 0x8U // Task 4 Run Status
|
||||
#define CLA_MIRUN_INT5 0x10U // Task 5 Run Status
|
||||
#define CLA_MIRUN_INT6 0x20U // Task 6 Run Status
|
||||
#define CLA_MIRUN_INT7 0x40U // Task 7 Run Status
|
||||
#define CLA_MIRUN_INT8 0x80U // Task 8 Run Status
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the _MSTF register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLA_MSTF_LVF 0x1U // Latched Overflow Flag
|
||||
#define CLA_MSTF_LUF 0x2U // Latched Underflow Flag
|
||||
#define CLA_MSTF_NF 0x4U // Negative Float Flag
|
||||
#define CLA_MSTF_ZF 0x8U // Zero Float Flag
|
||||
#define CLA_MSTF_TF 0x40U // Test Flag
|
||||
#define CLA_MSTF_RNDF32 0x200U // Round 32-bit Floating-Point Mode
|
||||
#define CLA_MSTF_MEALLOW 0x800U // MEALLOW Status
|
||||
#define CLA_MSTF_RPC_S 12U
|
||||
#define CLA_MSTF_RPC_M 0xFFFF000U // Return PC
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __TMS320C28XX_CLA__
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SOFTINTEN register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLA_SOFTINTEN_TASK1 0x1U // Configure Software Interrupt or End of Task interrupt.
|
||||
#define CLA_SOFTINTEN_TASK2 0x2U // Configure Software Interrupt or End of Task interrupt.
|
||||
#define CLA_SOFTINTEN_TASK3 0x4U // Configure Software Interrupt or End of Task interrupt.
|
||||
#define CLA_SOFTINTEN_TASK4 0x8U // Configure Software Interrupt or End of Task interrupt.
|
||||
#define CLA_SOFTINTEN_TASK5 0x10U // Configure Software Interrupt or End of Task interrupt.
|
||||
#define CLA_SOFTINTEN_TASK6 0x20U // Configure Software Interrupt or End of Task interrupt.
|
||||
#define CLA_SOFTINTEN_TASK7 0x40U // Configure Software Interrupt or End of Task interrupt.
|
||||
#define CLA_SOFTINTEN_TASK8 0x80U // Configure Software Interrupt or End of Task interrupt.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SOFTINTFRC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLA_SOFTINTFRC_TASK1 0x1U // Force CLA software interrupt for the corresponding task.
|
||||
#define CLA_SOFTINTFRC_TASK2 0x2U // Force CLA software interrupt for the corresponding task.
|
||||
#define CLA_SOFTINTFRC_TASK3 0x4U // Force CLA software interrupt for the corresponding task.
|
||||
#define CLA_SOFTINTFRC_TASK4 0x8U // Force CLA software interrupt for the corresponding task.
|
||||
#define CLA_SOFTINTFRC_TASK5 0x10U // Force CLA software interrupt for the corresponding task.
|
||||
#define CLA_SOFTINTFRC_TASK6 0x20U // Force CLA software interrupt for the corresponding task.
|
||||
#define CLA_SOFTINTFRC_TASK7 0x40U // Force CLA software interrupt for the corresponding task.
|
||||
#define CLA_SOFTINTFRC_TASK8 0x80U // Force CLA software interrupt for the corresponding task.
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,659 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_clb.h
|
||||
//
|
||||
// TITLE: Definitions for the CLB registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_CLB_H
|
||||
#define HW_CLB_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the CLB register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_O_COUNT_RESET 0x2U // Counter Block RESET
|
||||
#define CLB_O_COUNT_MODE_1 0x4U // Counter Block MODE_1
|
||||
#define CLB_O_COUNT_MODE_0 0x6U // Counter Block MODE_0
|
||||
#define CLB_O_COUNT_EVENT 0x8U // Counter Block EVENT
|
||||
#define CLB_O_FSM_EXTRA_IN0 0xAU // FSM Extra EXT_IN0
|
||||
#define CLB_O_FSM_EXTERNAL_IN0 0xCU // FSM EXT_IN0
|
||||
#define CLB_O_FSM_EXTERNAL_IN1 0xEU // FSM_EXT_IN1
|
||||
#define CLB_O_FSM_EXTRA_IN1 0x10U // FSM Extra_EXT_IN1
|
||||
#define CLB_O_LUT4_IN0 0x12U // LUT4_0/1/2 IN0 input source
|
||||
#define CLB_O_LUT4_IN1 0x14U // LUT4_0/1/2 IN1 input source
|
||||
#define CLB_O_LUT4_IN2 0x16U // LUT4_0/1/2 IN2 input source
|
||||
#define CLB_O_LUT4_IN3 0x18U // LUT4_0/1/2 IN3 input source
|
||||
#define CLB_O_FSM_LUT_FN1_0 0x1CU // LUT function for FSM Unit 1 and Unit 0
|
||||
#define CLB_O_FSM_LUT_FN2 0x1EU // LUT function for FSM Unit 2
|
||||
#define CLB_O_LUT4_FN1_0 0x20U // LUT function for LUT4 block of Unit 1 and 0
|
||||
#define CLB_O_LUT4_FN2 0x22U // LUT function for LUT4 block of Unit 2
|
||||
#define CLB_O_FSM_NEXT_STATE_0 0x24U // FSM Next state equations for Unit 0
|
||||
#define CLB_O_FSM_NEXT_STATE_1 0x26U // FSM Next state equations for Unit 1
|
||||
#define CLB_O_FSM_NEXT_STATE_2 0x28U // FSM Next state equations for Unit 2
|
||||
#define CLB_O_MISC_CONTROL 0x2AU // Static controls for Ctr,FSM
|
||||
#define CLB_O_OUTPUT_LUT_0 0x2CU // Inp Sel, LUT fns for Out0
|
||||
#define CLB_O_OUTPUT_LUT_1 0x2EU // Inp Sel, LUT fns for Out1
|
||||
#define CLB_O_OUTPUT_LUT_2 0x30U // Inp Sel, LUT fns for Out2
|
||||
#define CLB_O_OUTPUT_LUT_3 0x32U // Inp Sel, LUT fns for Out3
|
||||
#define CLB_O_OUTPUT_LUT_4 0x34U // Inp Sel, LUT fns for Out4
|
||||
#define CLB_O_OUTPUT_LUT_5 0x36U // Inp Sel, LUT fns for Out5
|
||||
#define CLB_O_OUTPUT_LUT_6 0x38U // Inp Sel, LUT fns for Out6
|
||||
#define CLB_O_OUTPUT_LUT_7 0x3AU // Inp Sel, LUT fns for Out7
|
||||
#define CLB_O_HLC_EVENT_SEL 0x3CU // Event Selector register for the High Level controller
|
||||
|
||||
#define CLB_O_LOAD_EN 0x0U // Global enable & indirect load enable control
|
||||
#define CLB_O_LOAD_ADDR 0x2U // Indirect address
|
||||
#define CLB_O_LOAD_DATA 0x4U // Data for indirect loads
|
||||
#define CLB_O_INPUT_FILTER 0x6U // Input filter selection for both edge detection and
|
||||
// synchronizers
|
||||
#define CLB_O_IN_MUX_SEL_0 0x8U // Input selection to decide between Signals and GP register
|
||||
#define CLB_O_LCL_MUX_SEL_1 0xAU // Input Mux selection for local mux
|
||||
#define CLB_O_LCL_MUX_SEL_2 0xCU // Input Mux selection for local mux
|
||||
#define CLB_O_BUF_PTR 0xEU // PUSH and PULL pointers
|
||||
#define CLB_O_GP_REG 0x10U // General purpose register for CELL inputs
|
||||
#define CLB_O_OUT_EN 0x12U // CELL output enable register
|
||||
#define CLB_O_GLBL_MUX_SEL_1 0x14U // Global Mux select for CELL inputs
|
||||
#define CLB_O_GLBL_MUX_SEL_2 0x16U // Global Mux select for CELL inputs
|
||||
#define CLB_O_INTR_TAG_REG 0x20U // Interrupt Tag register
|
||||
#define CLB_O_LOCK 0x22U // Lock control register
|
||||
#define CLB_O_DBG_R0 0x30U // R0 of High level Controller
|
||||
#define CLB_O_DBG_R1 0x32U // R1 of High level Controller
|
||||
#define CLB_O_DBG_R2 0x34U // R2 of High level Controller
|
||||
#define CLB_O_DBG_R3 0x36U // R3 of High level Controller
|
||||
#define CLB_O_DBG_C0 0x38U // Count of Unit 0
|
||||
#define CLB_O_DBG_C1 0x3AU // Count of Unit 1
|
||||
#define CLB_O_DBG_C2 0x3CU // Count of Unit 2
|
||||
#define CLB_O_DBG_OUT 0x3EU // Outputs of various units in the Cell
|
||||
|
||||
#define CLB_O_PUSH(i) (0x0U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PUSH FIFO Registers (from
|
||||
// HLC)
|
||||
#define CLB_O_PULL(i) (0x100U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PULL FIFO Registers (TO HLC)
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_COUNT_RESET register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_COUNT_RESET_SEL_0_S 0U
|
||||
#define CLB_COUNT_RESET_SEL_0_M 0x1FU // Count Reset Select 0
|
||||
#define CLB_COUNT_RESET_SEL_1_S 5U
|
||||
#define CLB_COUNT_RESET_SEL_1_M 0x3E0U // Count Reset Select 1
|
||||
#define CLB_COUNT_RESET_SEL_2_S 10U
|
||||
#define CLB_COUNT_RESET_SEL_2_M 0x7C00U // Count Reset Select 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_COUNT_MODE_1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_COUNT_MODE_1_SEL_0_S 0U
|
||||
#define CLB_COUNT_MODE_1_SEL_0_M 0x1FU // Counter mode 1 select 0
|
||||
#define CLB_COUNT_MODE_1_SEL_1_S 5U
|
||||
#define CLB_COUNT_MODE_1_SEL_1_M 0x3E0U // Counter mode 1 select 1
|
||||
#define CLB_COUNT_MODE_1_SEL_2_S 10U
|
||||
#define CLB_COUNT_MODE_1_SEL_2_M 0x7C00U // Counter mode 1 select 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_COUNT_MODE_0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_COUNT_MODE_0_SEL_0_S 0U
|
||||
#define CLB_COUNT_MODE_0_SEL_0_M 0x1FU // Counter mode 0 select 0
|
||||
#define CLB_COUNT_MODE_0_SEL_1_S 5U
|
||||
#define CLB_COUNT_MODE_0_SEL_1_M 0x3E0U // Counter mode 0 select 1
|
||||
#define CLB_COUNT_MODE_0_SEL_2_S 10U
|
||||
#define CLB_COUNT_MODE_0_SEL_2_M 0x7C00U // Counter mode 0 select 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_COUNT_EVENT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_COUNT_EVENT_SEL_0_S 0U
|
||||
#define CLB_COUNT_EVENT_SEL_0_M 0x1FU // Counter event select 0
|
||||
#define CLB_COUNT_EVENT_SEL_1_S 5U
|
||||
#define CLB_COUNT_EVENT_SEL_1_M 0x3E0U // Counter event select 1
|
||||
#define CLB_COUNT_EVENT_SEL_2_S 10U
|
||||
#define CLB_COUNT_EVENT_SEL_2_M 0x7C00U // Counter event select 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_FSM_EXTRA_IN0_SEL_0_S 0U
|
||||
#define CLB_FSM_EXTRA_IN0_SEL_0_M 0x1FU // FSM extra ext input select 0
|
||||
#define CLB_FSM_EXTRA_IN0_SEL_1_S 5U
|
||||
#define CLB_FSM_EXTRA_IN0_SEL_1_M 0x3E0U // FSM extra ext input select 1
|
||||
#define CLB_FSM_EXTRA_IN0_SEL_2_S 10U
|
||||
#define CLB_FSM_EXTRA_IN0_SEL_2_M 0x7C00U // FSM extra ext input select 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_FSM_EXTERNAL_IN0_SEL_0_S 0U
|
||||
#define CLB_FSM_EXTERNAL_IN0_SEL_0_M 0x1FU // FSM EXT_IN0 select input for unit 0
|
||||
#define CLB_FSM_EXTERNAL_IN0_SEL_1_S 5U
|
||||
#define CLB_FSM_EXTERNAL_IN0_SEL_1_M 0x3E0U // FSM EXT_IN0 select input for unit 1
|
||||
#define CLB_FSM_EXTERNAL_IN0_SEL_2_S 10U
|
||||
#define CLB_FSM_EXTERNAL_IN0_SEL_2_M 0x7C00U // FSM EXT_IN0 select input for unit 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_FSM_EXTERNAL_IN1_SEL_0_S 0U
|
||||
#define CLB_FSM_EXTERNAL_IN1_SEL_0_M 0x1FU // FSM EXT_IN1 select input for unit 0
|
||||
#define CLB_FSM_EXTERNAL_IN1_SEL_1_S 5U
|
||||
#define CLB_FSM_EXTERNAL_IN1_SEL_1_M 0x3E0U // FSM EXT_IN1 select input for unit 1
|
||||
#define CLB_FSM_EXTERNAL_IN1_SEL_2_S 10U
|
||||
#define CLB_FSM_EXTERNAL_IN1_SEL_2_M 0x7C00U // FSM EXT_IN1 select input for unit 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_FSM_EXTRA_IN1_SEL_0_S 0U
|
||||
#define CLB_FSM_EXTRA_IN1_SEL_0_M 0x1FU // FSM extra ext input select 0
|
||||
#define CLB_FSM_EXTRA_IN1_SEL_1_S 5U
|
||||
#define CLB_FSM_EXTRA_IN1_SEL_1_M 0x3E0U // FSM extra ext input select 1
|
||||
#define CLB_FSM_EXTRA_IN1_SEL_2_S 10U
|
||||
#define CLB_FSM_EXTRA_IN1_SEL_2_M 0x7C00U // FSM extra ext input select 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_LUT4_IN0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_LUT4_IN0_SEL_0_S 0U
|
||||
#define CLB_LUT4_IN0_SEL_0_M 0x1FU // Select inputs for unit 0
|
||||
#define CLB_LUT4_IN0_SEL_1_S 5U
|
||||
#define CLB_LUT4_IN0_SEL_1_M 0x3E0U // Select inputs for unit 1
|
||||
#define CLB_LUT4_IN0_SEL_2_S 10U
|
||||
#define CLB_LUT4_IN0_SEL_2_M 0x7C00U // Select inputs for unit 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_LUT4_IN1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_LUT4_IN1_SEL_0_S 0U
|
||||
#define CLB_LUT4_IN1_SEL_0_M 0x1FU // Select inputs for unit 0
|
||||
#define CLB_LUT4_IN1_SEL_1_S 5U
|
||||
#define CLB_LUT4_IN1_SEL_1_M 0x3E0U // Select inputs for unit 1
|
||||
#define CLB_LUT4_IN1_SEL_2_S 10U
|
||||
#define CLB_LUT4_IN1_SEL_2_M 0x7C00U // Select inputs for unit 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_LUT4_IN2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_LUT4_IN2_SEL_0_S 0U
|
||||
#define CLB_LUT4_IN2_SEL_0_M 0x1FU // Select inputs for unit 0
|
||||
#define CLB_LUT4_IN2_SEL_1_S 5U
|
||||
#define CLB_LUT4_IN2_SEL_1_M 0x3E0U // Select inputs for unit 1
|
||||
#define CLB_LUT4_IN2_SEL_2_S 10U
|
||||
#define CLB_LUT4_IN2_SEL_2_M 0x7C00U // Select inputs for unit 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_LUT4_IN3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_LUT4_IN3_SEL_0_S 0U
|
||||
#define CLB_LUT4_IN3_SEL_0_M 0x1FU // Select inputs for unit 0
|
||||
#define CLB_LUT4_IN3_SEL_1_S 5U
|
||||
#define CLB_LUT4_IN3_SEL_1_M 0x3E0U // Select inputs for unit 1
|
||||
#define CLB_LUT4_IN3_SEL_2_S 10U
|
||||
#define CLB_LUT4_IN3_SEL_2_M 0x7C00U // Select inputs for unit 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_FSM_LUT_FN1_0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_FSM_LUT_FN1_0_FN0_S 0U
|
||||
#define CLB_FSM_LUT_FN1_0_FN0_M 0xFFFFU // FSM LUT output function for unit 0
|
||||
#define CLB_FSM_LUT_FN1_0_FN1_S 16U
|
||||
#define CLB_FSM_LUT_FN1_0_FN1_M 0xFFFF0000U // FSM LUT output function for unit 1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_FSM_LUT_FN2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_FSM_LUT_FN2_FN1_S 0U
|
||||
#define CLB_FSM_LUT_FN2_FN1_M 0xFFFFU // FSM LUT output function for unit 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_LUT4_FN1_0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_LUT4_FN1_0_FN0_S 0U
|
||||
#define CLB_LUT4_FN1_0_FN0_M 0xFFFFU // LUT4 output function for unit 0
|
||||
#define CLB_LUT4_FN1_0_FN1_S 16U
|
||||
#define CLB_LUT4_FN1_0_FN1_M 0xFFFF0000U // LUT4 output function for unit 1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_LUT4_FN2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_LUT4_FN2_FN1_S 0U
|
||||
#define CLB_LUT4_FN2_FN1_M 0xFFFFU // LUT4 output function for unit 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_FSM_NEXT_STATE_0_S0_S 0U
|
||||
#define CLB_FSM_NEXT_STATE_0_S0_M 0xFFFFU // FSM next state function for S0
|
||||
#define CLB_FSM_NEXT_STATE_0_S1_S 16U
|
||||
#define CLB_FSM_NEXT_STATE_0_S1_M 0xFFFF0000U // FSM next state function for S1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_FSM_NEXT_STATE_1_S0_S 0U
|
||||
#define CLB_FSM_NEXT_STATE_1_S0_M 0xFFFFU // FSM next state function for S0
|
||||
#define CLB_FSM_NEXT_STATE_1_S1_S 16U
|
||||
#define CLB_FSM_NEXT_STATE_1_S1_M 0xFFFF0000U // FSM next state function for S1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_FSM_NEXT_STATE_2_S0_S 0U
|
||||
#define CLB_FSM_NEXT_STATE_2_S0_M 0xFFFFU // FSM next state function for S0
|
||||
#define CLB_FSM_NEXT_STATE_2_S1_S 16U
|
||||
#define CLB_FSM_NEXT_STATE_2_S1_M 0xFFFF0000U // FSM next state function for S1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_MISC_CONTROL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_0 0x1U // Add/Shift for counter 0
|
||||
#define CLB_MISC_CONTROL_COUNT_DIR_0 0x2U // Direction for counter 0
|
||||
#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_0 0x4U // Event control for counter 0
|
||||
#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_1 0x8U // Add/Shift for counter 1
|
||||
#define CLB_MISC_CONTROL_COUNT_DIR_1 0x10U // Direction for counter 1
|
||||
#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_1 0x20U // Event control for counter 1
|
||||
#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_2 0x40U // Add/Shift for counter 2
|
||||
#define CLB_MISC_CONTROL_COUNT_DIR_2 0x80U // Direction for counter 2
|
||||
#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_2 0x100U // Event control for counter 2
|
||||
#define CLB_MISC_CONTROL_COUNT_SERIALIZER_0 0x200U // Serializer enable 0
|
||||
#define CLB_MISC_CONTROL_COUNT_SERIALIZER_1 0x400U // Serializer enable 1
|
||||
#define CLB_MISC_CONTROL_COUNT_SERIALIZER_2 0x800U // Serializer enable 2
|
||||
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_0 0x1000U // FSM extra_sel0 for 0
|
||||
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_0 0x2000U // FSM extra_sel1 for 0
|
||||
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_1 0x4000U // FSM extra_sel0 for 1
|
||||
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_1 0x8000U // FSM extra_sel1 for 1
|
||||
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_2 0x10000U // FSM extra_sel0 for 2
|
||||
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_2 0x20000U // FSM extra_sel1 for 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_OUTPUT_LUT_0_IN0_S 0U
|
||||
#define CLB_OUTPUT_LUT_0_IN0_M 0x1FU // Select value for IN0 of output LUT
|
||||
#define CLB_OUTPUT_LUT_0_IN1_S 5U
|
||||
#define CLB_OUTPUT_LUT_0_IN1_M 0x3E0U // Select value for IN1 of output LUT
|
||||
#define CLB_OUTPUT_LUT_0_IN2_S 10U
|
||||
#define CLB_OUTPUT_LUT_0_IN2_M 0x7C00U // Select value for IN2 of output LUT
|
||||
#define CLB_OUTPUT_LUT_0_FN_S 15U
|
||||
#define CLB_OUTPUT_LUT_0_FN_M 0x7F8000U // Output function for output LUT
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_OUTPUT_LUT_1_IN0_S 0U
|
||||
#define CLB_OUTPUT_LUT_1_IN0_M 0x1FU // Select value for IN0 of output LUT
|
||||
#define CLB_OUTPUT_LUT_1_IN1_S 5U
|
||||
#define CLB_OUTPUT_LUT_1_IN1_M 0x3E0U // Select value for IN1 of output LUT
|
||||
#define CLB_OUTPUT_LUT_1_IN2_S 10U
|
||||
#define CLB_OUTPUT_LUT_1_IN2_M 0x7C00U // Select value for IN2 of output LUT
|
||||
#define CLB_OUTPUT_LUT_1_FN_S 15U
|
||||
#define CLB_OUTPUT_LUT_1_FN_M 0x7F8000U // Output function for output LUT
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_OUTPUT_LUT_2_IN0_S 0U
|
||||
#define CLB_OUTPUT_LUT_2_IN0_M 0x1FU // Select value for IN0 of output LUT
|
||||
#define CLB_OUTPUT_LUT_2_IN1_S 5U
|
||||
#define CLB_OUTPUT_LUT_2_IN1_M 0x3E0U // Select value for IN1 of output LUT
|
||||
#define CLB_OUTPUT_LUT_2_IN2_S 10U
|
||||
#define CLB_OUTPUT_LUT_2_IN2_M 0x7C00U // Select value for IN2 of output LUT
|
||||
#define CLB_OUTPUT_LUT_2_FN_S 15U
|
||||
#define CLB_OUTPUT_LUT_2_FN_M 0x7F8000U // Output function for output LUT
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_OUTPUT_LUT_3_IN0_S 0U
|
||||
#define CLB_OUTPUT_LUT_3_IN0_M 0x1FU // Select value for IN0 of output LUT
|
||||
#define CLB_OUTPUT_LUT_3_IN1_S 5U
|
||||
#define CLB_OUTPUT_LUT_3_IN1_M 0x3E0U // Select value for IN1 of output LUT
|
||||
#define CLB_OUTPUT_LUT_3_IN2_S 10U
|
||||
#define CLB_OUTPUT_LUT_3_IN2_M 0x7C00U // Select value for IN2 of output LUT
|
||||
#define CLB_OUTPUT_LUT_3_FN_S 15U
|
||||
#define CLB_OUTPUT_LUT_3_FN_M 0x7F8000U // Output function for output LUT
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_OUTPUT_LUT_4_IN0_S 0U
|
||||
#define CLB_OUTPUT_LUT_4_IN0_M 0x1FU // Select value for IN0 of output LUT
|
||||
#define CLB_OUTPUT_LUT_4_IN1_S 5U
|
||||
#define CLB_OUTPUT_LUT_4_IN1_M 0x3E0U // Select value for IN1 of output LUT
|
||||
#define CLB_OUTPUT_LUT_4_IN2_S 10U
|
||||
#define CLB_OUTPUT_LUT_4_IN2_M 0x7C00U // Select value for IN2 of output LUT
|
||||
#define CLB_OUTPUT_LUT_4_FN_S 15U
|
||||
#define CLB_OUTPUT_LUT_4_FN_M 0x7F8000U // Output function for output LUT
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_5 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_OUTPUT_LUT_5_IN0_S 0U
|
||||
#define CLB_OUTPUT_LUT_5_IN0_M 0x1FU // Select value for IN0 of output LUT
|
||||
#define CLB_OUTPUT_LUT_5_IN1_S 5U
|
||||
#define CLB_OUTPUT_LUT_5_IN1_M 0x3E0U // Select value for IN1 of output LUT
|
||||
#define CLB_OUTPUT_LUT_5_IN2_S 10U
|
||||
#define CLB_OUTPUT_LUT_5_IN2_M 0x7C00U // Select value for IN2 of output LUT
|
||||
#define CLB_OUTPUT_LUT_5_FN_S 15U
|
||||
#define CLB_OUTPUT_LUT_5_FN_M 0x7F8000U // Output function for output LUT
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_6 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_OUTPUT_LUT_6_IN0_S 0U
|
||||
#define CLB_OUTPUT_LUT_6_IN0_M 0x1FU // Select value for IN0 of output LUT
|
||||
#define CLB_OUTPUT_LUT_6_IN1_S 5U
|
||||
#define CLB_OUTPUT_LUT_6_IN1_M 0x3E0U // Select value for IN1 of output LUT
|
||||
#define CLB_OUTPUT_LUT_6_IN2_S 10U
|
||||
#define CLB_OUTPUT_LUT_6_IN2_M 0x7C00U // Select value for IN2 of output LUT
|
||||
#define CLB_OUTPUT_LUT_6_FN_S 15U
|
||||
#define CLB_OUTPUT_LUT_6_FN_M 0x7F8000U // Output function for output LUT
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_7 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_OUTPUT_LUT_7_IN0_S 0U
|
||||
#define CLB_OUTPUT_LUT_7_IN0_M 0x1FU // Select value for IN0 of output LUT
|
||||
#define CLB_OUTPUT_LUT_7_IN1_S 5U
|
||||
#define CLB_OUTPUT_LUT_7_IN1_M 0x3E0U // Select value for IN1 of output LUT
|
||||
#define CLB_OUTPUT_LUT_7_IN2_S 10U
|
||||
#define CLB_OUTPUT_LUT_7_IN2_M 0x7C00U // Select value for IN2 of output LUT
|
||||
#define CLB_OUTPUT_LUT_7_FN_S 15U
|
||||
#define CLB_OUTPUT_LUT_7_FN_M 0x7F8000U // Output function for output LUT
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_HLC_EVENT_SEL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_HLC_EVENT_SEL_EVENT0_SEL_S 0U
|
||||
#define CLB_HLC_EVENT_SEL_EVENT0_SEL_M 0x1FU // Event Select 0
|
||||
#define CLB_HLC_EVENT_SEL_EVENT1_SEL_S 5U
|
||||
#define CLB_HLC_EVENT_SEL_EVENT1_SEL_M 0x3E0U // Event Select 1
|
||||
#define CLB_HLC_EVENT_SEL_EVENT2_SEL_S 10U
|
||||
#define CLB_HLC_EVENT_SEL_EVENT2_SEL_M 0x7C00U // Event Select 2
|
||||
#define CLB_HLC_EVENT_SEL_EVENT3_SEL_S 15U
|
||||
#define CLB_HLC_EVENT_SEL_EVENT3_SEL_M 0xF8000U // Event Select 3
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_LOAD_EN register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_LOAD_EN_LOAD_EN 0x1U // Load Enable
|
||||
#define CLB_LOAD_EN_GLOBAL_EN 0x2U // Global Enable
|
||||
#define CLB_LOAD_EN_STOP 0x4U // Debug stop control
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_LOAD_ADDR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_LOAD_ADDR_ADDR_S 0U
|
||||
#define CLB_LOAD_ADDR_ADDR_M 0x3FU // Indirect Address
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_INPUT_FILTER register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_INPUT_FILTER_FIN0_S 0U
|
||||
#define CLB_INPUT_FILTER_FIN0_M 0x3U // Input filter control 0
|
||||
#define CLB_INPUT_FILTER_FIN1_S 2U
|
||||
#define CLB_INPUT_FILTER_FIN1_M 0xCU // Input filter control 1
|
||||
#define CLB_INPUT_FILTER_FIN2_S 4U
|
||||
#define CLB_INPUT_FILTER_FIN2_M 0x30U // Input filter control 2
|
||||
#define CLB_INPUT_FILTER_FIN3_S 6U
|
||||
#define CLB_INPUT_FILTER_FIN3_M 0xC0U // Input filter control 3
|
||||
#define CLB_INPUT_FILTER_FIN4_S 8U
|
||||
#define CLB_INPUT_FILTER_FIN4_M 0x300U // Input filter control 4
|
||||
#define CLB_INPUT_FILTER_FIN5_S 10U
|
||||
#define CLB_INPUT_FILTER_FIN5_M 0xC00U // Input filter control 5
|
||||
#define CLB_INPUT_FILTER_FIN6_S 12U
|
||||
#define CLB_INPUT_FILTER_FIN6_M 0x3000U // Input filter control 6
|
||||
#define CLB_INPUT_FILTER_FIN7_S 14U
|
||||
#define CLB_INPUT_FILTER_FIN7_M 0xC000U // Input filter control 7
|
||||
#define CLB_INPUT_FILTER_SYNC0 0x10000U // Synchronizer control 0
|
||||
#define CLB_INPUT_FILTER_SYNC1 0x20000U // Synchronizer control 1
|
||||
#define CLB_INPUT_FILTER_SYNC2 0x40000U // Synchronizer control 2
|
||||
#define CLB_INPUT_FILTER_SYNC3 0x80000U // Synchronizer control 3
|
||||
#define CLB_INPUT_FILTER_SYNC4 0x100000U // Synchronizer control 4
|
||||
#define CLB_INPUT_FILTER_SYNC5 0x200000U // Synchronizer control 5
|
||||
#define CLB_INPUT_FILTER_SYNC6 0x400000U // Synchronizer control 6
|
||||
#define CLB_INPUT_FILTER_SYNC7 0x800000U // Synchronizer control 7
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_IN_MUX_SEL_0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_0 0x1U // Select GP register 0
|
||||
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_1 0x2U // Select GP register 1
|
||||
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_2 0x4U // Select GP register 2
|
||||
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_3 0x8U // Select GP register 3
|
||||
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_4 0x10U // Select GP register 4
|
||||
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_5 0x20U // Select GP register 5
|
||||
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_6 0x40U // Select GP register 6
|
||||
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_7 0x80U // Select GP register 7
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_S 0U
|
||||
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M 0x1FU // Local Mux select 0
|
||||
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S 5U
|
||||
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_M 0x3E0U // Local Mux select 1
|
||||
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_S 10U
|
||||
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_M 0x7C00U // Local Mux select 2
|
||||
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_S 15U
|
||||
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_M 0xF8000U // Local Mux select 3
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_S 0U
|
||||
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_M 0x1FU // Local Mux select 4
|
||||
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_S 5U
|
||||
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_M 0x3E0U // Local Mux select 5
|
||||
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_S 10U
|
||||
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_M 0x7C00U // Local Mux select 6
|
||||
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_S 15U
|
||||
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_M 0xF8000U // Local Mux select 7
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_BUF_PTR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_BUF_PTR_PULL_S 0U
|
||||
#define CLB_BUF_PTR_PULL_M 0xFFU // Data pointer for pull
|
||||
#define CLB_BUF_PTR_PUSH_S 16U
|
||||
#define CLB_BUF_PTR_PUSH_M 0xFF0000U // Data pointer for pull
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_GP_REG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_GP_REG_REG_S 0U
|
||||
#define CLB_GP_REG_REG_M 0xFFU // General Purpose bit register
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_S 0U
|
||||
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M 0x7FU // Global Mux select 0
|
||||
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S 7U
|
||||
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_M 0x3F80U // Global Mux select 1
|
||||
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_S 14U
|
||||
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_M 0x1FC000U // Global Mux select 2
|
||||
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_S 21U
|
||||
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_M 0xFE00000U // Global Mux select 3
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_S 0U
|
||||
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_M 0x7FU // Global Mux select 4
|
||||
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_S 7U
|
||||
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_M 0x3F80U // Global Mux select 5
|
||||
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_S 14U
|
||||
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_M 0x1FC000U // Global Mux select 6
|
||||
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_S 21U
|
||||
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_M 0xFE00000U // Global Mux select 7
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_INTR_TAG_REG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_INTR_TAG_REG_TAG_S 0U
|
||||
#define CLB_INTR_TAG_REG_TAG_M 0x3FU // Interrupt tag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_LOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_LOCK_LOCK 0x1U // LOCK enable
|
||||
#define CLB_LOCK_KEY_S 16U
|
||||
#define CLB_LOCK_KEY_M 0xFFFF0000U // Key for enabling write
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CLB_DBG_OUT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CLB_DBG_OUT_COUNT0_MATCH2 0x2U // COUNT_MATCH2 UNIT 0
|
||||
#define CLB_DBG_OUT_COUNT0_ZERO 0x4U // COUNT_ZERO UNIT 0
|
||||
#define CLB_DBG_OUT_COUNT0_MATCH1 0x8U // COUNT_MATCH1 UNIT 0
|
||||
#define CLB_DBG_OUT_FSM0_S0 0x10U // FSM_S0 UNIT 0
|
||||
#define CLB_DBG_OUT_FSM0_S1 0x20U // FSM_S1 UNIT 0
|
||||
#define CLB_DBG_OUT_FSM0_LUTOUT 0x40U // FSM_LUT_OUT UNIT 0
|
||||
#define CLB_DBG_OUT_LUT40_OUT 0x80U // LUT4_OUT UNIT 0
|
||||
#define CLB_DBG_OUT_COUNT1_MATCH2 0x200U // COUNT_MATCH2 UNIT 1
|
||||
#define CLB_DBG_OUT_COUNT1_ZERO 0x400U // COUNT_ZERO UNIT 1
|
||||
#define CLB_DBG_OUT_COUNT1_MATCH1 0x800U // COUNT_MATCH1 UNIT 1
|
||||
#define CLB_DBG_OUT_FSM1_S0 0x1000U // FSM_S0 UNIT 1
|
||||
#define CLB_DBG_OUT_FSM1_S1 0x2000U // FSM_S1 UNIT 1
|
||||
#define CLB_DBG_OUT_FSM1_LUTOUT 0x4000U // FSM_LUT_OUT UNIT 1
|
||||
#define CLB_DBG_OUT_LUT41_OUT 0x8000U // LUT4_OUT UNIT 1
|
||||
#define CLB_DBG_OUT_COUNT2_MATCH2 0x20000U // COUNT_MATCH2 UNIT 2
|
||||
#define CLB_DBG_OUT_COUNT2_ZERO 0x40000U // COUNT_ZERO UNIT 2
|
||||
#define CLB_DBG_OUT_COUNT2_MATCH1 0x80000U // COUNT_MATCH1 UNIT 2
|
||||
#define CLB_DBG_OUT_FSM2_S0 0x100000U // FSM_S0 UNIT 2
|
||||
#define CLB_DBG_OUT_FSM2_S1 0x200000U // FSM_S1 UNIT 2
|
||||
#define CLB_DBG_OUT_FSM2_LUTOUT 0x400000U // FSM_LUT_OUT UNIT 2
|
||||
#define CLB_DBG_OUT_LUT42_OUT 0x800000U // LUT4_OUT UNIT 2
|
||||
#define CLB_DBG_OUT_OUT0 0x1000000U // CELL Output 0
|
||||
#define CLB_DBG_OUT_OUT1 0x2000000U // CELL Output 1
|
||||
#define CLB_DBG_OUT_OUT2 0x4000000U // CELL Output 2
|
||||
#define CLB_DBG_OUT_OUT3 0x8000000U // CELL Output 3
|
||||
#define CLB_DBG_OUT_OUT4 0x10000000U // CELL Output 4
|
||||
#define CLB_DBG_OUT_OUT5 0x20000000U // CELL Output 5
|
||||
#define CLB_DBG_OUT_OUT6 0x40000000U // CELL Output 6
|
||||
#define CLB_DBG_OUT_OUT7 0x80000000U // CELL Output 7
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,233 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_cmpss.h
|
||||
//
|
||||
// TITLE: Definitions for the CMPSS registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_CMPSS_H
|
||||
#define HW_CMPSS_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the CMPSS register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_O_COMPCTL 0x0U // CMPSS Comparator Control Register
|
||||
#define CMPSS_O_COMPHYSCTL 0x1U // CMPSS Comparator Hysteresis Control Register
|
||||
#define CMPSS_O_COMPSTS 0x2U // CMPSS Comparator Status Register
|
||||
#define CMPSS_O_COMPSTSCLR 0x3U // CMPSS Comparator Status Clear Register
|
||||
#define CMPSS_O_COMPDACCTL 0x4U // CMPSS DAC Control Register
|
||||
#define CMPSS_O_DACHVALS 0x6U // CMPSS High DAC Value Shadow Register
|
||||
#define CMPSS_O_DACHVALA 0x7U // CMPSS High DAC Value Active Register
|
||||
#define CMPSS_O_RAMPMAXREFA 0x8U // CMPSS Ramp Max Reference Active Register
|
||||
#define CMPSS_O_RAMPMAXREFS 0xAU // CMPSS Ramp Max Reference Shadow Register
|
||||
#define CMPSS_O_RAMPDECVALA 0xCU // CMPSS Ramp Decrement Value Active Register
|
||||
#define CMPSS_O_RAMPDECVALS 0xEU // CMPSS Ramp Decrement Value Shadow Register
|
||||
#define CMPSS_O_RAMPSTS 0x10U // CMPSS Ramp Status Register
|
||||
#define CMPSS_O_DACLVALS 0x12U // CMPSS Low DAC Value Shadow Register
|
||||
#define CMPSS_O_DACLVALA 0x13U // CMPSS Low DAC Value Active Register
|
||||
#define CMPSS_O_RAMPDLYA 0x14U // CMPSS Ramp Delay Active Register
|
||||
#define CMPSS_O_RAMPDLYS 0x15U // CMPSS Ramp Delay Shadow Register
|
||||
#define CMPSS_O_CTRIPLFILCTL 0x16U // CTRIPL Filter Control Register
|
||||
#define CMPSS_O_CTRIPLFILCLKCTL 0x17U // CTRIPL Filter Clock Control Register
|
||||
#define CMPSS_O_CTRIPHFILCTL 0x18U // CTRIPH Filter Control Register
|
||||
#define CMPSS_O_CTRIPHFILCLKCTL 0x19U // CTRIPH Filter Clock Control Register
|
||||
#define CMPSS_O_COMPLOCK 0x1AU // CMPSS Lock Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMPCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_COMPCTL_COMPHSOURCE 0x1U // High Comparator Source Select
|
||||
#define CMPSS_COMPCTL_COMPHINV 0x2U // High Comparator Invert Select
|
||||
#define CMPSS_COMPCTL_CTRIPHSEL_S 2U
|
||||
#define CMPSS_COMPCTL_CTRIPHSEL_M 0xCU // High Comparator Trip Select
|
||||
#define CMPSS_COMPCTL_CTRIPOUTHSEL_S 4U
|
||||
#define CMPSS_COMPCTL_CTRIPOUTHSEL_M 0x30U // High Comparator Trip Output Select
|
||||
#define CMPSS_COMPCTL_ASYNCHEN 0x40U // High Comparator Asynchronous Path Enable
|
||||
#define CMPSS_COMPCTL_COMPLSOURCE 0x100U // Low Comparator Source Select
|
||||
#define CMPSS_COMPCTL_COMPLINV 0x200U // Low Comparator Invert Select
|
||||
#define CMPSS_COMPCTL_CTRIPLSEL_S 10U
|
||||
#define CMPSS_COMPCTL_CTRIPLSEL_M 0xC00U // Low Comparator Trip Select
|
||||
#define CMPSS_COMPCTL_CTRIPOUTLSEL_S 12U
|
||||
#define CMPSS_COMPCTL_CTRIPOUTLSEL_M 0x3000U // Low Comparator Trip Output Select
|
||||
#define CMPSS_COMPCTL_ASYNCLEN 0x4000U // Low Comparator Asynchronous Path Enable
|
||||
#define CMPSS_COMPCTL_COMPDACE 0x8000U // Comparator/DAC Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMPHYSCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_COMPHYSCTL_COMPHYS_S 0U
|
||||
#define CMPSS_COMPHYSCTL_COMPHYS_M 0x7U // Comparator Hysteresis Trim
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMPSTS register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_COMPSTS_COMPHSTS 0x1U // High Comparator Status
|
||||
#define CMPSS_COMPSTS_COMPHLATCH 0x2U // High Comparator Latched Status
|
||||
#define CMPSS_COMPSTS_COMPLSTS 0x100U // Low Comparator Status
|
||||
#define CMPSS_COMPSTS_COMPLLATCH 0x200U // Low Comparator Latched Status
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMPSTSCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_COMPSTSCLR_HLATCHCLR 0x2U // High Comparator Latched Status Clear
|
||||
#define CMPSS_COMPSTSCLR_HSYNCCLREN 0x4U // High Comparator EPWMSYNCPER Clear Enable
|
||||
#define CMPSS_COMPSTSCLR_LLATCHCLR 0x200U // Low Comparator Latched Status Clear
|
||||
#define CMPSS_COMPSTSCLR_LSYNCCLREN 0x400U // Low Comparator EPWMSYNCPER Clear Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMPDACCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_COMPDACCTL_DACSOURCE 0x1U // DAC Source Control
|
||||
#define CMPSS_COMPDACCTL_RAMPSOURCE_S 1U
|
||||
#define CMPSS_COMPDACCTL_RAMPSOURCE_M 0x1EU // Ramp Generator Source Control
|
||||
#define CMPSS_COMPDACCTL_SELREF 0x20U // DAC Reference Select
|
||||
#define CMPSS_COMPDACCTL_RAMPLOADSEL 0x40U // Ramp Load Select
|
||||
#define CMPSS_COMPDACCTL_SWLOADSEL 0x80U // Software Load Select
|
||||
#define CMPSS_COMPDACCTL_FREESOFT_S 14U
|
||||
#define CMPSS_COMPDACCTL_FREESOFT_M 0xC000U // Free/Soft Emulation Bits
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DACHVALS register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_DACHVALS_DACVAL_S 0U
|
||||
#define CMPSS_DACHVALS_DACVAL_M 0xFFFU // DAC Value Control
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DACHVALA register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_DACHVALA_DACVAL_S 0U
|
||||
#define CMPSS_DACHVALA_DACVAL_M 0xFFFU // DAC Value Control
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DACLVALS register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_DACLVALS_DACVAL_S 0U
|
||||
#define CMPSS_DACLVALS_DACVAL_M 0xFFFU // DAC Value Control
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DACLVALA register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_DACLVALA_DACVAL_S 0U
|
||||
#define CMPSS_DACLVALA_DACVAL_M 0xFFFU // DAC Value Control
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the RAMPDLYA register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_RAMPDLYA_DELAY_S 0U
|
||||
#define CMPSS_RAMPDLYA_DELAY_M 0x1FFFU // Ramp Delay Value
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the RAMPDLYS register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_RAMPDLYS_DELAY_S 0U
|
||||
#define CMPSS_RAMPDLYS_DELAY_M 0x1FFFU // Ramp Delay Value
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CTRIPLFILCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_CTRIPLFILCTL_SAMPWIN_S 4U
|
||||
#define CMPSS_CTRIPLFILCTL_SAMPWIN_M 0x1F0U // Sample Window
|
||||
#define CMPSS_CTRIPLFILCTL_THRESH_S 9U
|
||||
#define CMPSS_CTRIPLFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold
|
||||
#define CMPSS_CTRIPLFILCTL_FILINIT 0x8000U // Filter Initialization Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CTRIPLFILCLKCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_S 0U
|
||||
#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CTRIPHFILCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_CTRIPHFILCTL_SAMPWIN_S 4U
|
||||
#define CMPSS_CTRIPHFILCTL_SAMPWIN_M 0x1F0U // Sample Window
|
||||
#define CMPSS_CTRIPHFILCTL_THRESH_S 9U
|
||||
#define CMPSS_CTRIPHFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold
|
||||
#define CMPSS_CTRIPHFILCTL_FILINIT 0x8000U // Filter Initialization Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CTRIPHFILCLKCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_S 0U
|
||||
#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMPLOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CMPSS_COMPLOCK_COMPCTL 0x1U // COMPCTL Lock
|
||||
#define CMPSS_COMPLOCK_COMPHYSCTL 0x2U // COMPHYSCTL Lock
|
||||
#define CMPSS_COMPLOCK_DACCTL 0x4U // DACCTL Lock
|
||||
#define CMPSS_COMPLOCK_CTRIP 0x8U // CTRIP Lock
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,110 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_cputimer.h
|
||||
//
|
||||
// TITLE: Definitions for the CPUTIMER registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_CPUTIMER_H
|
||||
#define HW_CPUTIMER_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the CPUTIMER register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CPUTIMER_O_TIM 0x0U // CPU-Timer, Counter Register
|
||||
#define CPUTIMER_O_PRD 0x2U // CPU-Timer, Period Register
|
||||
#define CPUTIMER_O_TCR 0x4U // CPU-Timer, Control Register
|
||||
#define CPUTIMER_O_TPR 0x6U // CPU-Timer, Prescale Register
|
||||
#define CPUTIMER_O_TPRH 0x7U // CPU-Timer, Prescale Register High
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIM register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CPUTIMER_TIM_LSW_S 0U
|
||||
#define CPUTIMER_TIM_LSW_M 0xFFFFU // CPU-Timer Counter Registers
|
||||
#define CPUTIMER_TIM_MSW_S 16U
|
||||
#define CPUTIMER_TIM_MSW_M 0xFFFF0000U // CPU-Timer Counter Registers High
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PRD register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CPUTIMER_PRD_LSW_S 0U
|
||||
#define CPUTIMER_PRD_LSW_M 0xFFFFU // CPU-Timer Period Registers
|
||||
#define CPUTIMER_PRD_MSW_S 16U
|
||||
#define CPUTIMER_PRD_MSW_M 0xFFFF0000U // CPU-Timer Period Registers High
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TCR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CPUTIMER_TCR_TSS 0x10U // CPU-Timer stop status bit.
|
||||
#define CPUTIMER_TCR_TRB 0x20U // Timer reload
|
||||
#define CPUTIMER_TCR_SOFT 0x400U // Emulation modes
|
||||
#define CPUTIMER_TCR_FREE 0x800U // Emulation modes
|
||||
#define CPUTIMER_TCR_TIE 0x4000U // CPU-Timer Interrupt Enable.
|
||||
#define CPUTIMER_TCR_TIF 0x8000U // CPU-Timer Interrupt Flag.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TPR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CPUTIMER_TPR_TDDR_S 0U
|
||||
#define CPUTIMER_TPR_TDDR_M 0xFFU // CPU-Timer Divide-Down.
|
||||
#define CPUTIMER_TPR_PSC_S 8U
|
||||
#define CPUTIMER_TPR_PSC_M 0xFF00U // CPU-Timer Prescale Counter.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TPRH register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define CPUTIMER_TPRH_TDDRH_S 0U
|
||||
#define CPUTIMER_TPRH_TDDRH_M 0xFFU // CPU-Timer Divide-Down.
|
||||
#define CPUTIMER_TPRH_PSCH_S 8U
|
||||
#define CPUTIMER_TPRH_PSCH_M 0xFF00U // CPU-Timer Prescale Counter.
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,120 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_dac.h
|
||||
//
|
||||
// TITLE: Definitions for the DAC registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_DAC_H
|
||||
#define HW_DAC_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the DAC register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DAC_O_REV 0x0U // DAC Revision Register
|
||||
#define DAC_O_CTL 0x1U // DAC Control Register
|
||||
#define DAC_O_VALA 0x2U // DAC Value Register - Active
|
||||
#define DAC_O_VALS 0x3U // DAC Value Register - Shadow
|
||||
#define DAC_O_OUTEN 0x4U // DAC Output Enable Register
|
||||
#define DAC_O_LOCK 0x5U // DAC Lock Register
|
||||
#define DAC_O_TRIM 0x6U // DAC Trim Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DACREV register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DAC_REV_REV_S 0U
|
||||
#define DAC_REV_REV_M 0xFFU // DAC Revision Register
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DACCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DAC_CTL_DACREFSEL 0x1U // DAC Reference Select
|
||||
#define DAC_CTL_LOADMODE 0x4U // DACVALA Load Mode
|
||||
#define DAC_CTL_SYNCSEL_S 4U
|
||||
#define DAC_CTL_SYNCSEL_M 0xF0U // DAC EPWMSYNCPER Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DACVALA register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DAC_VALA_DACVALA_S 0U
|
||||
#define DAC_VALA_DACVALA_M 0xFFFU // DAC Active Output Code
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DACVALS register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DAC_VALS_DACVALS_S 0U
|
||||
#define DAC_VALS_DACVALS_M 0xFFFU // DAC Shadow Output Code
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DACOUTEN register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DAC_OUTEN_DACOUTEN 0x1U // DAC Output Code
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DACLOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DAC_LOCK_DACCTL 0x1U // DAC Control Register Lock
|
||||
#define DAC_LOCK_DACVAL 0x2U // DAC Value Register Lock
|
||||
#define DAC_LOCK_DACOUTEN 0x4U // DAC Output Enable Register Lock
|
||||
#define DAC_LOCK_KEY_S 12U
|
||||
#define DAC_LOCK_KEY_M 0xF000U // DAC Register Lock Key
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DACTRIM register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DAC_TRIM_OFFSET_TRIM_S 0U
|
||||
#define DAC_TRIM_OFFSET_TRIM_M 0xFFU // DAC Offset Trim
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,440 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_dcsm.h
|
||||
//
|
||||
// TITLE: Definitions for the DCSM registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_DCSM_H
|
||||
#define HW_DCSM_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the DCSM register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_O_Z1OTP_LINKPOINTER1 0x0U // Zone 1 Link Pointer1 in Z1 OTP
|
||||
#define DCSM_O_Z1OTP_LINKPOINTER2 0x4U // Zone 1 Link Pointer2 in Z1 OTP
|
||||
#define DCSM_O_Z1OTP_LINKPOINTER3 0x8U // Zone 1 Link Pointer3 in Z1 OTP
|
||||
#define DCSM_O_Z1OTP_PSWDLOCK 0x10U // Secure Password Lock in Z1 OTP
|
||||
#define DCSM_O_Z1OTP_CRCLOCK 0x14U // Secure CRC Lock in Z1 OTP
|
||||
#define DCSM_O_Z1OTP_BOOTCTRL 0x1EU // Boot Mode in Z1 OTP
|
||||
|
||||
#define DCSM_O_Z2OTP_LINKPOINTER1 0x0U // Zone 2 Link Pointer1 in Z2 OTP
|
||||
#define DCSM_O_Z2OTP_LINKPOINTER2 0x4U // Zone 2 Link Pointer2 in Z2 OTP
|
||||
#define DCSM_O_Z2OTP_LINKPOINTER3 0x8U // Zone 2 Link Pointer3 in Z2 OTP
|
||||
#define DCSM_O_Z2OTP_PSWDLOCK 0x10U // Secure Password Lock in Z2 OTP
|
||||
#define DCSM_O_Z2OTP_CRCLOCK 0x14U // Secure CRC Lock in Z2 OTP
|
||||
#define DCSM_O_Z2OTP_BOOTCTRL 0x1EU // Boot Mode in Z2 OTP
|
||||
|
||||
#define DCSM_O_Z1_LINKPOINTER 0x0U // Zone 1 Link Pointer
|
||||
#define DCSM_O_Z1_OTPSECLOCK 0x2U // Zone 1 OTP Secure JTAG lock
|
||||
#define DCSM_O_Z1_BOOTCTRL 0x4U // Boot Mode
|
||||
#define DCSM_O_Z1_LINKPOINTERERR 0x6U // Link Pointer Error
|
||||
#define DCSM_O_Z1_CSMKEY0 0x10U // Zone 1 CSM Key 0
|
||||
#define DCSM_O_Z1_CSMKEY1 0x12U // Zone 1 CSM Key 1
|
||||
#define DCSM_O_Z1_CSMKEY2 0x14U // Zone 1 CSM Key 2
|
||||
#define DCSM_O_Z1_CSMKEY3 0x16U // Zone 1 CSM Key 3
|
||||
#define DCSM_O_Z1_CR 0x19U // Zone 1 CSM Control Register
|
||||
#define DCSM_O_Z1_GRABSECTR 0x1AU // Zone 1 Grab Flash Sectors Register
|
||||
#define DCSM_O_Z1_GRABRAMR 0x1CU // Zone 1 Grab RAM Blocks Register
|
||||
#define DCSM_O_Z1_EXEONLYSECTR 0x1EU // Zone 1 Flash Execute_Only Sector Register
|
||||
#define DCSM_O_Z1_EXEONLYRAMR 0x20U // Zone 1 RAM Execute_Only Block Register
|
||||
|
||||
#define DCSM_O_Z2_LINKPOINTER 0x0U // Zone 2 Link Pointer
|
||||
#define DCSM_O_Z2_OTPSECLOCK 0x2U // Zone 2 OTP Secure JTAG lock
|
||||
#define DCSM_O_Z2_BOOTCTRL 0x4U // Boot Mode
|
||||
#define DCSM_O_Z2_LINKPOINTERERR 0x6U // Link Pointer Error
|
||||
#define DCSM_O_Z2_CSMKEY0 0x10U // Zone 2 CSM Key 0
|
||||
#define DCSM_O_Z2_CSMKEY1 0x12U // Zone 2 CSM Key 1
|
||||
#define DCSM_O_Z2_CSMKEY2 0x14U // Zone 2 CSM Key 2
|
||||
#define DCSM_O_Z2_CSMKEY3 0x16U // Zone 2 CSM Key 3
|
||||
#define DCSM_O_Z2_CR 0x19U // Zone 2 CSM Control Register
|
||||
#define DCSM_O_Z2_GRABSECTR 0x1AU // Zone 2 Grab Flash Sectors Register
|
||||
#define DCSM_O_Z2_GRABRAMR 0x1CU // Zone 2 Grab RAM Blocks Register
|
||||
#define DCSM_O_Z2_EXEONLYSECTR 0x1EU // Zone 2 Flash Execute_Only Sector Register
|
||||
#define DCSM_O_Z2_EXEONLYRAMR 0x20U // Zone 2 RAM Execute_Only Block Register
|
||||
|
||||
#define DCSM_O_FLSEM 0x0U // Flash Wrapper Semaphore Register
|
||||
#define DCSM_O_SECTSTAT 0x2U // Sectors Status Register
|
||||
#define DCSM_O_RAMSTAT 0x4U // RAM Status Register
|
||||
|
||||
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z1_LINKPOINTER register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z1_LINKPOINTER_LINKPOINTER_S 0U
|
||||
#define DCSM_Z1_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone1 LINK Pointer.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z1_OTPSECLOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_S 4U
|
||||
#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone1 Password Lock.
|
||||
#define DCSM_Z1_OTPSECLOCK_CRCLOCK_S 8U
|
||||
#define DCSM_Z1_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone1 CRC Lock.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z1_BOOTCTRL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z1_BOOTCTRL_KEY_S 0U
|
||||
#define DCSM_Z1_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key
|
||||
#define DCSM_Z1_BOOTCTRL_BMODE_S 8U
|
||||
#define DCSM_Z1_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode
|
||||
#define DCSM_Z1_BOOTCTRL_BOOTPIN0_S 16U
|
||||
#define DCSM_Z1_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping
|
||||
#define DCSM_Z1_BOOTCTRL_BOOTPIN1_S 24U
|
||||
#define DCSM_Z1_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z1_CR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z1_CR_ALLZERO 0x8U // CSMPSWD All Zeros
|
||||
#define DCSM_Z1_CR_ALLONE 0x10U // CSMPSWD All Ones
|
||||
#define DCSM_Z1_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY
|
||||
#define DCSM_Z1_CR_ARMED 0x40U // CSM Armed
|
||||
#define DCSM_Z1_CR_FORCESEC 0x8000U // Force Secure
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z1_GRABSECTR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTA_S 0U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTB_S 2U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTC_S 4U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTD_S 6U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTE_S 8U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTF_S 10U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTG_S 12U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTH_S 14U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTI_S 16U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_S 18U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTK_S 20U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTL_S 22U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTM_S 24U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTN_S 26U
|
||||
#define DCSM_Z1_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z1_GRABRAMR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM0_S 0U
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM1_S 2U
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM2_S 4U
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM3_S 6U
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM4_S 8U
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM5_S 10U
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM6_S 12U
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM7_S 14U
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_CLA1_S 28U
|
||||
#define DCSM_Z1_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z1_EXEONLYSECTR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M
|
||||
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z1_EXEONLYRAMR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0
|
||||
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1
|
||||
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2
|
||||
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3
|
||||
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4
|
||||
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5
|
||||
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0
|
||||
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z2_LINKPOINTER register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z2_LINKPOINTER_LINKPOINTER_S 0U
|
||||
#define DCSM_Z2_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone2 LINK Pointer.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z2_OTPSECLOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_S 4U
|
||||
#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone2 Password Lock.
|
||||
#define DCSM_Z2_OTPSECLOCK_CRCLOCK_S 8U
|
||||
#define DCSM_Z2_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone2 CRC Lock.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z2_BOOTCTRL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z2_BOOTCTRL_KEY_S 0U
|
||||
#define DCSM_Z2_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key
|
||||
#define DCSM_Z2_BOOTCTRL_BMODE_S 8U
|
||||
#define DCSM_Z2_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode
|
||||
#define DCSM_Z2_BOOTCTRL_BOOTPIN0_S 16U
|
||||
#define DCSM_Z2_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping
|
||||
#define DCSM_Z2_BOOTCTRL_BOOTPIN1_S 24U
|
||||
#define DCSM_Z2_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z2_CR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z2_CR_ALLZERO 0x8U // CSMPSWD All Zeros
|
||||
#define DCSM_Z2_CR_ALLONE 0x10U // CSMPSWD All Ones
|
||||
#define DCSM_Z2_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY
|
||||
#define DCSM_Z2_CR_ARMED 0x40U // CSM Armed
|
||||
#define DCSM_Z2_CR_FORCESEC 0x8000U // Force Secure
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z2_GRABSECTR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTA_S 0U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTB_S 2U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTC_S 4U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTD_S 6U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTE_S 8U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTF_S 10U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTG_S 12U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTH_S 14U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTI_S 16U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_S 18U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTK_S 20U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTL_S 22U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTM_S 24U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTN_S 26U
|
||||
#define DCSM_Z2_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z2_GRABRAMR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM0_S 0U
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM1_S 2U
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM2_S 4U
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM3_S 6U
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM4_S 8U
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM5_S 10U
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM6_S 12U
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM7_S 14U
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_CLA1_S 28U
|
||||
#define DCSM_Z2_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z2_EXEONLYSECTR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M
|
||||
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the Z2_EXEONLYRAMR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0
|
||||
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1
|
||||
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2
|
||||
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3
|
||||
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4
|
||||
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5
|
||||
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0
|
||||
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLSEM register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_FLSEM_SEM_S 0U
|
||||
#define DCSM_FLSEM_SEM_M 0x3U // Flash Semaphore Bit
|
||||
#define DCSM_FLSEM_KEY_S 8U
|
||||
#define DCSM_FLSEM_KEY_M 0xFF00U // Semaphore Key
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SECTSTAT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_SECTSTAT_STATUS_SECTA_S 0U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTA_M 0x3U // Zone Status Flash Sector A
|
||||
#define DCSM_SECTSTAT_STATUS_SECTB_S 2U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTB_M 0xCU // Zone Status Flash Sector B
|
||||
#define DCSM_SECTSTAT_STATUS_SECTC_S 4U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTC_M 0x30U // Zone Status Flash Sector C
|
||||
#define DCSM_SECTSTAT_STATUS_SECTD_S 6U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTD_M 0xC0U // Zone Status Flash Sector D
|
||||
#define DCSM_SECTSTAT_STATUS_SECTE_S 8U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTE_M 0x300U // Zone Status Flash Sector E
|
||||
#define DCSM_SECTSTAT_STATUS_SECTF_S 10U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTF_M 0xC00U // Zone Status Flash Sector F
|
||||
#define DCSM_SECTSTAT_STATUS_SECTG_S 12U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTG_M 0x3000U // Zone Status Flash Sector G
|
||||
#define DCSM_SECTSTAT_STATUS_SECTH_S 14U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTH_M 0xC000U // Zone Status Flash Sector H
|
||||
#define DCSM_SECTSTAT_STATUS_SECTI_S 16U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTI_M 0x30000U // Zone Status Flash Sector I
|
||||
#define DCSM_SECTSTAT_STATUS_SECTJ_S 18U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTJ_M 0xC0000U // Zone Status Flash Sector J
|
||||
#define DCSM_SECTSTAT_STATUS_SECTK_S 20U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTK_M 0x300000U // Zone Status Flash Sector K
|
||||
#define DCSM_SECTSTAT_STATUS_SECTL_S 22U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTL_M 0xC00000U // Zone Status Flash Sector L
|
||||
#define DCSM_SECTSTAT_STATUS_SECTM_S 24U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTM_M 0x3000000U // Zone Status Flash Sector M
|
||||
#define DCSM_SECTSTAT_STATUS_SECTN_S 26U
|
||||
#define DCSM_SECTSTAT_STATUS_SECTN_M 0xC000000U // Zone Status Flash Sector N
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the RAMSTAT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DCSM_RAMSTAT_STATUS_RAM0_S 0U
|
||||
#define DCSM_RAMSTAT_STATUS_RAM0_M 0x3U // Zone Status RAM LS0
|
||||
#define DCSM_RAMSTAT_STATUS_RAM1_S 2U
|
||||
#define DCSM_RAMSTAT_STATUS_RAM1_M 0xCU // Zone Status RAM LS1
|
||||
#define DCSM_RAMSTAT_STATUS_RAM2_S 4U
|
||||
#define DCSM_RAMSTAT_STATUS_RAM2_M 0x30U // Zone Status RAM LS2
|
||||
#define DCSM_RAMSTAT_STATUS_RAM3_S 6U
|
||||
#define DCSM_RAMSTAT_STATUS_RAM3_M 0xC0U // Zone Status RAM LS3
|
||||
#define DCSM_RAMSTAT_STATUS_RAM4_S 8U
|
||||
#define DCSM_RAMSTAT_STATUS_RAM4_M 0x300U // Zone Status RAM LS4
|
||||
#define DCSM_RAMSTAT_STATUS_RAM5_S 10U
|
||||
#define DCSM_RAMSTAT_STATUS_RAM5_M 0xC00U // Zone Status RAM LS5
|
||||
#define DCSM_RAMSTAT_STATUS_RAM6_S 12U
|
||||
#define DCSM_RAMSTAT_STATUS_RAM6_M 0x3000U // Zone Status RAM D0
|
||||
#define DCSM_RAMSTAT_STATUS_RAM7_S 14U
|
||||
#define DCSM_RAMSTAT_STATUS_RAM7_M 0xC000U // Zone Status RAM D1
|
||||
#define DCSM_RAMSTAT_STATUS_CLA1_S 28U
|
||||
#define DCSM_RAMSTAT_STATUS_CLA1_M 0x30000000U // Zone Status CLA1
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,163 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_dma.h
|
||||
//
|
||||
// TITLE: Definitions for the DMA registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_DMA_H
|
||||
#define HW_DMA_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the DMA register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DMA_O_CTRL 0x0U // DMA Control Register
|
||||
#define DMA_O_DEBUGCTRL 0x1U // Debug Control Register
|
||||
#define DMA_O_PRIORITYCTRL1 0x4U // Priority Control 1 Register
|
||||
#define DMA_O_PRIORITYSTAT 0x6U // Priority Status Register
|
||||
|
||||
#define DMA_O_MODE 0x0U // Mode Register
|
||||
#define DMA_O_CONTROL 0x1U // Control Register
|
||||
#define DMA_O_BURST_SIZE 0x2U // Burst Size Register
|
||||
#define DMA_O_BURST_COUNT 0x3U // Burst Count Register
|
||||
#define DMA_O_SRC_BURST_STEP 0x4U // Source Burst Step Register
|
||||
#define DMA_O_DST_BURST_STEP 0x5U // Destination Burst Step Register
|
||||
#define DMA_O_TRANSFER_SIZE 0x6U // Transfer Size Register
|
||||
#define DMA_O_TRANSFER_COUNT 0x7U // Transfer Count Register
|
||||
#define DMA_O_SRC_TRANSFER_STEP 0x8U // Source Transfer Step Register
|
||||
#define DMA_O_DST_TRANSFER_STEP 0x9U // Destination Transfer Step Register
|
||||
#define DMA_O_SRC_WRAP_SIZE 0xAU // Source Wrap Size Register
|
||||
#define DMA_O_SRC_WRAP_COUNT 0xBU // Source Wrap Count Register
|
||||
#define DMA_O_SRC_WRAP_STEP 0xCU // Source Wrap Step Register
|
||||
#define DMA_O_DST_WRAP_SIZE 0xDU // Destination Wrap Size Register
|
||||
#define DMA_O_DST_WRAP_COUNT 0xEU // Destination Wrap Count Register
|
||||
#define DMA_O_DST_WRAP_STEP 0xFU // Destination Wrap Step Register
|
||||
#define DMA_O_SRC_BEG_ADDR_SHADOW 0x10U // Source Begin Address Shadow Register
|
||||
#define DMA_O_SRC_ADDR_SHADOW 0x12U // Source Address Shadow Register
|
||||
#define DMA_O_SRC_BEG_ADDR_ACTIVE 0x14U // Source Begin Address Active Register
|
||||
#define DMA_O_SRC_ADDR_ACTIVE 0x16U // Source Address Active Register
|
||||
#define DMA_O_DST_BEG_ADDR_SHADOW 0x18U // Destination Begin Address Shadow Register
|
||||
#define DMA_O_DST_ADDR_SHADOW 0x1AU // Destination Address Shadow Register
|
||||
#define DMA_O_DST_BEG_ADDR_ACTIVE 0x1CU // Destination Begin Address Active Register
|
||||
#define DMA_O_DST_ADDR_ACTIVE 0x1EU // Destination Address Active Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DMACTRL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DMA_CTRL_HARDRESET 0x1U // Hard Reset Bit
|
||||
#define DMA_CTRL_PRIORITYRESET 0x2U // Priority Reset Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DEBUGCTRL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DMA_DEBUGCTRL_FREE 0x8000U // Debug Mode Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PRIORITYCTRL1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DMA_PRIORITYCTRL1_CH1PRIORITY 0x1U // Ch1 Priority Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PRIORITYSTAT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DMA_PRIORITYSTAT_ACTIVESTS_S 0U
|
||||
#define DMA_PRIORITYSTAT_ACTIVESTS_M 0x7U // Active Channel Status Bits
|
||||
#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_S 4U
|
||||
#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_M 0x70U // Active Channel Status Shadow Bits
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MODE register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DMA_MODE_PERINTSEL_S 0U
|
||||
#define DMA_MODE_PERINTSEL_M 0x1FU // Peripheral Interrupt and Sync Select
|
||||
#define DMA_MODE_OVRINTE 0x80U // Overflow Interrupt Enable
|
||||
#define DMA_MODE_PERINTE 0x100U // Peripheral Interrupt Enable
|
||||
#define DMA_MODE_CHINTMODE 0x200U // Channel Interrupt Mode
|
||||
#define DMA_MODE_ONESHOT 0x400U // One Shot Mode Bit
|
||||
#define DMA_MODE_CONTINUOUS 0x800U // Continuous Mode Bit
|
||||
#define DMA_MODE_DATASIZE 0x4000U // Data Size Mode Bit
|
||||
#define DMA_MODE_CHINTE 0x8000U // Channel Interrupt Enable Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CONTROL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DMA_CONTROL_RUN 0x1U // Run Bit
|
||||
#define DMA_CONTROL_HALT 0x2U // Halt Bit
|
||||
#define DMA_CONTROL_SOFTRESET 0x4U // Soft Reset Bit
|
||||
#define DMA_CONTROL_PERINTFRC 0x8U // Interrupt Force Bit
|
||||
#define DMA_CONTROL_PERINTCLR 0x10U // Interrupt Clear Bit
|
||||
#define DMA_CONTROL_ERRCLR 0x80U // Error Clear Bit
|
||||
#define DMA_CONTROL_PERINTFLG 0x100U // Interrupt Flag Bit
|
||||
#define DMA_CONTROL_TRANSFERSTS 0x800U // Transfer Status Bit
|
||||
#define DMA_CONTROL_BURSTSTS 0x1000U // Burst Status Bit
|
||||
#define DMA_CONTROL_RUNSTS 0x2000U // Run Status Bit
|
||||
#define DMA_CONTROL_OVRFLG 0x4000U // Overflow Flag Bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the BURST_SIZE register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DMA_BURST_SIZE_BURSTSIZE_S 0U
|
||||
#define DMA_BURST_SIZE_BURSTSIZE_M 0x1FU // Burst Transfer Size
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the BURST_COUNT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define DMA_BURST_COUNT_BURSTCOUNT_S 0U
|
||||
#define DMA_BURST_COUNT_BURSTCOUNT_M 0x1FU // Burst Transfer Size
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,155 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_ecap.h
|
||||
//
|
||||
// TITLE: Definitions for the ECAP registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_ECAP_H
|
||||
#define HW_ECAP_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the ECAP register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ECAP_O_TSCTR 0x0U // Time-Stamp Counter
|
||||
#define ECAP_O_CTRPHS 0x2U // Counter Phase Offset Value Register
|
||||
#define ECAP_O_CAP1 0x4U // Capture 1 Register
|
||||
#define ECAP_O_CAP2 0x6U // Capture 2 Register
|
||||
#define ECAP_O_CAP3 0x8U // Capture 3 Register
|
||||
#define ECAP_O_CAP4 0xAU // Capture 4 Register
|
||||
#define ECAP_O_ECCTL1 0x14U // Capture Control Register 1
|
||||
#define ECAP_O_ECCTL2 0x15U // Capture Control Register 2
|
||||
#define ECAP_O_ECEINT 0x16U // Capture Interrupt Enable Register
|
||||
#define ECAP_O_ECFLG 0x17U // Capture Interrupt Flag Register
|
||||
#define ECAP_O_ECCLR 0x18U // Capture Interrupt Clear Register
|
||||
#define ECAP_O_ECFRC 0x19U // Capture Interrupt Force Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ECCTL1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ECAP_ECCTL1_CAP1POL 0x1U // Capture Event 1 Polarity select
|
||||
#define ECAP_ECCTL1_CTRRST1 0x2U // Counter Reset on Capture Event 1
|
||||
#define ECAP_ECCTL1_CAP2POL 0x4U // Capture Event 2 Polarity select
|
||||
#define ECAP_ECCTL1_CTRRST2 0x8U // Counter Reset on Capture Event 2
|
||||
#define ECAP_ECCTL1_CAP3POL 0x10U // Capture Event 3 Polarity select
|
||||
#define ECAP_ECCTL1_CTRRST3 0x20U // Counter Reset on Capture Event 3
|
||||
#define ECAP_ECCTL1_CAP4POL 0x40U // Capture Event 4 Polarity select
|
||||
#define ECAP_ECCTL1_CTRRST4 0x80U // Counter Reset on Capture Event 4
|
||||
#define ECAP_ECCTL1_CAPLDEN 0x100U // Enable Loading CAP1-4 regs on a Cap Event
|
||||
#define ECAP_ECCTL1_PRESCALE_S 9U
|
||||
#define ECAP_ECCTL1_PRESCALE_M 0x3E00U // Event Filter prescale select
|
||||
#define ECAP_ECCTL1_FREE_SOFT_S 14U
|
||||
#define ECAP_ECCTL1_FREE_SOFT_M 0xC000U // Emulation mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ECCTL2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ECAP_ECCTL2_CONT_ONESHT 0x1U // Continuous or one-shot
|
||||
#define ECAP_ECCTL2_STOP_WRAP_S 1U
|
||||
#define ECAP_ECCTL2_STOP_WRAP_M 0x6U // Stop value for one-shot, Wrap for continuous
|
||||
#define ECAP_ECCTL2_REARM 0x8U // One-shot re-arm
|
||||
#define ECAP_ECCTL2_TSCTRSTOP 0x10U // TSCNT counter stop
|
||||
#define ECAP_ECCTL2_SYNCI_EN 0x20U // Counter sync-in select
|
||||
#define ECAP_ECCTL2_SYNCO_SEL_S 6U
|
||||
#define ECAP_ECCTL2_SYNCO_SEL_M 0xC0U // Sync-out mode
|
||||
#define ECAP_ECCTL2_SWSYNC 0x100U // SW forced counter sync
|
||||
#define ECAP_ECCTL2_CAP_APWM 0x200U // CAP/APWM operating mode select
|
||||
#define ECAP_ECCTL2_APWMPOL 0x400U // APWM output polarity select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ECEINT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ECAP_ECEINT_CEVT1 0x2U // Capture Event 1 Interrupt Enable
|
||||
#define ECAP_ECEINT_CEVT2 0x4U // Capture Event 2 Interrupt Enable
|
||||
#define ECAP_ECEINT_CEVT3 0x8U // Capture Event 3 Interrupt Enable
|
||||
#define ECAP_ECEINT_CEVT4 0x10U // Capture Event 4 Interrupt Enable
|
||||
#define ECAP_ECEINT_CTROVF 0x20U // Counter Overflow Interrupt Enable
|
||||
#define ECAP_ECEINT_CTR_EQ_PRD 0x40U // Period Equal Interrupt Enable
|
||||
#define ECAP_ECEINT_CTR_EQ_CMP 0x80U // Compare Equal Interrupt Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ECFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ECAP_ECFLG_INT 0x1U // Global Flag
|
||||
#define ECAP_ECFLG_CEVT1 0x2U // Capture Event 1 Interrupt Flag
|
||||
#define ECAP_ECFLG_CEVT2 0x4U // Capture Event 2 Interrupt Flag
|
||||
#define ECAP_ECFLG_CEVT3 0x8U // Capture Event 3 Interrupt Flag
|
||||
#define ECAP_ECFLG_CEVT4 0x10U // Capture Event 4 Interrupt Flag
|
||||
#define ECAP_ECFLG_CTROVF 0x20U // Counter Overflow Interrupt Flag
|
||||
#define ECAP_ECFLG_CTR_PRD 0x40U // Period Equal Interrupt Flag
|
||||
#define ECAP_ECFLG_CTR_CMP 0x80U // Compare Equal Interrupt Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ECCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ECAP_ECCLR_INT 0x1U // ECAP Global Interrupt Status Clear
|
||||
#define ECAP_ECCLR_CEVT1 0x2U // Capture Event 1 Status Clear
|
||||
#define ECAP_ECCLR_CEVT2 0x4U // Capture Event 2 Status Clear
|
||||
#define ECAP_ECCLR_CEVT3 0x8U // Capture Event 3 Status Clear
|
||||
#define ECAP_ECCLR_CEVT4 0x10U // Capture Event 4 Status Clear
|
||||
#define ECAP_ECCLR_CTROVF 0x20U // Counter Overflow Status Clear
|
||||
#define ECAP_ECCLR_CTR_PRD 0x40U // Period Equal Status Clear
|
||||
#define ECAP_ECCLR_CTR_CMP 0x80U // Compare Equal Status Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ECFRC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define ECAP_ECFRC_CEVT1 0x2U // Capture Event 1 Force Interrupt
|
||||
#define ECAP_ECFRC_CEVT2 0x4U // Capture Event 2 Force Interrupt
|
||||
#define ECAP_ECFRC_CEVT3 0x8U // Capture Event 3 Force Interrupt
|
||||
#define ECAP_ECFRC_CEVT4 0x10U // Capture Event 4 Force Interrupt
|
||||
#define ECAP_ECFRC_CTROVF 0x20U // Counter Overflow Force Interrupt
|
||||
#define ECAP_ECFRC_CTR_PRD 0x40U // Period Equal Force Interrupt
|
||||
#define ECAP_ECFRC_CTR_CMP 0x80U // Compare Equal Force Interrupt
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,257 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_emif.h
|
||||
//
|
||||
// TITLE: Definitions for the EMIF registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_EMIF_H
|
||||
#define HW_EMIF_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the EMIF register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_O_RCSR 0x0U // Revision Code and Status Register
|
||||
#define EMIF_O_ASYNC_WCCR 0x2U // Async Wait Cycle Config Register
|
||||
#define EMIF_O_SDRAM_CR 0x4U // SDRAM (EMxCS0n) Config Register
|
||||
#define EMIF_O_SDRAM_RCR 0x6U // SDRAM Refresh Control Register
|
||||
#define EMIF_O_ASYNC_CS2_CR 0x8U // Async 1 (EMxCS2n) Config Register
|
||||
#define EMIF_O_ASYNC_CS3_CR 0xAU // Async 2 (EMxCS3n) Config Register
|
||||
#define EMIF_O_ASYNC_CS4_CR 0xCU // Async 3 (EMxCS4n) Config Register
|
||||
#define EMIF_O_SDRAM_TR 0x10U // SDRAM Timing Register
|
||||
#define EMIF_O_TOTAL_SDRAM_AR 0x18U // Total SDRAM Accesses Register
|
||||
#define EMIF_O_TOTAL_SDRAM_ACTR 0x1AU // Total SDRAM Activate Register
|
||||
#define EMIF_O_SDR_EXT_TMNG 0x1EU // SDRAM SR/PD Exit Timing Register
|
||||
#define EMIF_O_INT_RAW 0x20U // Interrupt Raw Register
|
||||
#define EMIF_O_INT_MSK 0x22U // Interrupt Masked Register
|
||||
#define EMIF_O_INT_MSK_SET 0x24U // Interrupt Mask Set Register
|
||||
#define EMIF_O_INT_MSK_CLR 0x26U // Interrupt Mask Clear Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the RCSR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_RCSR_MINOR_REVISION_S 0U
|
||||
#define EMIF_RCSR_MINOR_REVISION_M 0xFFU // Minor Revision.
|
||||
#define EMIF_RCSR_MAJOR_REVISION_S 8U
|
||||
#define EMIF_RCSR_MAJOR_REVISION_M 0xFF00U // Major Revision.
|
||||
#define EMIF_RCSR_MODULE_ID_S 16U
|
||||
#define EMIF_RCSR_MODULE_ID_M 0x3FFF0000U // EMIF module ID.
|
||||
#define EMIF_RCSR_FR 0x40000000U // EMIF is running in full rate or half rate.
|
||||
#define EMIF_RCSR_BE 0x80000000U // EMIF endian mode.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ASYNC_WCCR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_S 0U
|
||||
#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M 0xFFU // Maximum Extended Wait cycles.
|
||||
#define EMIF_ASYNC_WCCR_WP0 0x10000000U // Polarity for EMxWAIT.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDRAM_CR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_SDRAM_CR_PAGESIGE_S 0U
|
||||
#define EMIF_SDRAM_CR_PAGESIGE_M 0x7U // Page Size.
|
||||
#define EMIF_SDRAM_CR_IBANK_S 4U
|
||||
#define EMIF_SDRAM_CR_IBANK_M 0x70U // Internal Bank setup of SDRAM devices.
|
||||
#define EMIF_SDRAM_CR_BIT_11_9_LOCK 0x100U // Bits 11 to 9 are writable only if this bit
|
||||
// is set.
|
||||
#define EMIF_SDRAM_CR_CL_S 9U
|
||||
#define EMIF_SDRAM_CR_CL_M 0xE00U // CAS Latency.
|
||||
#define EMIF_SDRAM_CR_NM 0x4000U // Narrow Mode.
|
||||
#define EMIF_SDRAM_CR_PDWR 0x20000000U // Perform refreshes during Power Down.
|
||||
#define EMIF_SDRAM_CR_PD 0x40000000U // Power Down.
|
||||
#define EMIF_SDRAM_CR_SR 0x80000000U // Self Refresh.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDRAM_RCR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_SDRAM_RCR_REFRESH_RATE_S 0U
|
||||
#define EMIF_SDRAM_RCR_REFRESH_RATE_M 0x1FFFU // Refresh Rate.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ASYNC_CS2_CR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_ASYNC_CS2_CR_ASIZE_S 0U
|
||||
#define EMIF_ASYNC_CS2_CR_ASIZE_M 0x3U // Asynchronous Memory Size.
|
||||
#define EMIF_ASYNC_CS2_CR_TA_S 2U
|
||||
#define EMIF_ASYNC_CS2_CR_TA_M 0xCU // Turn Around cycles.
|
||||
#define EMIF_ASYNC_CS2_CR_R_HOLD_S 4U
|
||||
#define EMIF_ASYNC_CS2_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles.
|
||||
#define EMIF_ASYNC_CS2_CR_R_STROBE_S 7U
|
||||
#define EMIF_ASYNC_CS2_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles.
|
||||
#define EMIF_ASYNC_CS2_CR_R_SETUP_S 13U
|
||||
#define EMIF_ASYNC_CS2_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles.
|
||||
#define EMIF_ASYNC_CS2_CR_W_HOLD_S 17U
|
||||
#define EMIF_ASYNC_CS2_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles.
|
||||
#define EMIF_ASYNC_CS2_CR_W_STROBE_S 20U
|
||||
#define EMIF_ASYNC_CS2_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles.
|
||||
#define EMIF_ASYNC_CS2_CR_W_SETUP_S 26U
|
||||
#define EMIF_ASYNC_CS2_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles.
|
||||
#define EMIF_ASYNC_CS2_CR_EW 0x40000000U // Extend Wait mode.
|
||||
#define EMIF_ASYNC_CS2_CR_SS 0x80000000U // Select Strobe mode.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ASYNC_CS3_CR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_ASYNC_CS3_CR_ASIZE_S 0U
|
||||
#define EMIF_ASYNC_CS3_CR_ASIZE_M 0x3U // Asynchronous Memory Size.
|
||||
#define EMIF_ASYNC_CS3_CR_TA_S 2U
|
||||
#define EMIF_ASYNC_CS3_CR_TA_M 0xCU // Turn Around cycles.
|
||||
#define EMIF_ASYNC_CS3_CR_R_HOLD_S 4U
|
||||
#define EMIF_ASYNC_CS3_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles.
|
||||
#define EMIF_ASYNC_CS3_CR_R_STROBE_S 7U
|
||||
#define EMIF_ASYNC_CS3_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles.
|
||||
#define EMIF_ASYNC_CS3_CR_R_SETUP_S 13U
|
||||
#define EMIF_ASYNC_CS3_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles.
|
||||
#define EMIF_ASYNC_CS3_CR_W_HOLD_S 17U
|
||||
#define EMIF_ASYNC_CS3_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles.
|
||||
#define EMIF_ASYNC_CS3_CR_W_STROBE_S 20U
|
||||
#define EMIF_ASYNC_CS3_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles.
|
||||
#define EMIF_ASYNC_CS3_CR_W_SETUP_S 26U
|
||||
#define EMIF_ASYNC_CS3_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles.
|
||||
#define EMIF_ASYNC_CS3_CR_EW 0x40000000U // Extend Wait mode.
|
||||
#define EMIF_ASYNC_CS3_CR_SS 0x80000000U // Select Strobe mode.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ASYNC_CS4_CR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_ASYNC_CS4_CR_ASIZE_S 0U
|
||||
#define EMIF_ASYNC_CS4_CR_ASIZE_M 0x3U // Asynchronous Memory Size.
|
||||
#define EMIF_ASYNC_CS4_CR_TA_S 2U
|
||||
#define EMIF_ASYNC_CS4_CR_TA_M 0xCU // Turn Around cycles.
|
||||
#define EMIF_ASYNC_CS4_CR_R_HOLD_S 4U
|
||||
#define EMIF_ASYNC_CS4_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles.
|
||||
#define EMIF_ASYNC_CS4_CR_R_STROBE_S 7U
|
||||
#define EMIF_ASYNC_CS4_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles.
|
||||
#define EMIF_ASYNC_CS4_CR_R_SETUP_S 13U
|
||||
#define EMIF_ASYNC_CS4_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles.
|
||||
#define EMIF_ASYNC_CS4_CR_W_HOLD_S 17U
|
||||
#define EMIF_ASYNC_CS4_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles.
|
||||
#define EMIF_ASYNC_CS4_CR_W_STROBE_S 20U
|
||||
#define EMIF_ASYNC_CS4_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles.
|
||||
#define EMIF_ASYNC_CS4_CR_W_SETUP_S 26U
|
||||
#define EMIF_ASYNC_CS4_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles.
|
||||
#define EMIF_ASYNC_CS4_CR_EW 0x40000000U // Extend Wait mode.
|
||||
#define EMIF_ASYNC_CS4_CR_SS 0x80000000U // Select Strobe mode.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDRAM_TR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_SDRAM_TR_T_RRD_S 4U
|
||||
#define EMIF_SDRAM_TR_T_RRD_M 0x70U // Activate to Activate timing for different bank.
|
||||
#define EMIF_SDRAM_TR_T_RC_S 8U
|
||||
#define EMIF_SDRAM_TR_T_RC_M 0xF00U // Activate to Activate timing .
|
||||
#define EMIF_SDRAM_TR_T_RAS_S 12U
|
||||
#define EMIF_SDRAM_TR_T_RAS_M 0xF000U // Activate to Precharge timing.
|
||||
#define EMIF_SDRAM_TR_T_WR_S 16U
|
||||
#define EMIF_SDRAM_TR_T_WR_M 0x70000U // Last Write to Precharge timing.
|
||||
#define EMIF_SDRAM_TR_T_RCD_S 20U
|
||||
#define EMIF_SDRAM_TR_T_RCD_M 0x700000U // Activate to Read/Write timing.
|
||||
#define EMIF_SDRAM_TR_T_RP_S 24U
|
||||
#define EMIF_SDRAM_TR_T_RP_M 0x7000000U // Precharge to Activate/Refresh timing.
|
||||
#define EMIF_SDRAM_TR_T_RFC_S 27U
|
||||
#define EMIF_SDRAM_TR_T_RFC_M 0xF8000000U // Refresh/Load Mode to Refresh/Activate timing
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDR_EXT_TMNG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_SDR_EXT_TMNG_T_XS_S 0U
|
||||
#define EMIF_SDR_EXT_TMNG_T_XS_M 0x1FU // Self Refresh exit to new command timing.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the INT_RAW register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_INT_RAW_AT 0x1U // Asynchronous Timeout.
|
||||
#define EMIF_INT_RAW_LT 0x2U // Line Trap.
|
||||
#define EMIF_INT_RAW_WR_S 2U
|
||||
#define EMIF_INT_RAW_WR_M 0x3CU // Wait Rise.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the INT_MSK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_INT_MSK_AT_MASKED 0x1U // Asynchronous Timeout.
|
||||
#define EMIF_INT_MSK_LT_MASKED 0x2U // Line Trap.
|
||||
#define EMIF_INT_MSK_WR_MASKED_S 2U
|
||||
#define EMIF_INT_MSK_WR_MASKED_M 0x3CU // Wait Rise.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the INT_MSK_SET register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_INT_MSK_SET_AT_MASK_SET 0x1U // Asynchronous Timeout.
|
||||
#define EMIF_INT_MSK_SET_LT_MASK_SET 0x2U // Line Trap.
|
||||
#define EMIF_INT_MSK_SET_WR_MASK_SET_S 2U
|
||||
#define EMIF_INT_MSK_SET_WR_MASK_SET_M 0x3CU // Wait Rise.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the INT_MSK_CLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EMIF_INT_MSK_CLR_AT_MASK_CLR 0x1U // Asynchronous Timeout.
|
||||
#define EMIF_INT_MSK_CLR_LT_MASK_CLR 0x2U // Line Trap.
|
||||
#define EMIF_INT_MSK_CLR_WR_MASK_CLR_S 2U
|
||||
#define EMIF_INT_MSK_CLR_WR_MASK_CLR_M 0x3CU // Wait Rise.
|
||||
|
||||
|
||||
|
||||
#endif
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,223 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_eqep.h
|
||||
//
|
||||
// TITLE: Definitions for the EQEP registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_EQEP_H
|
||||
#define HW_EQEP_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the EQEP register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EQEP_O_QPOSCNT 0x0U // Position Counter
|
||||
#define EQEP_O_QPOSINIT 0x2U // Position Counter Init
|
||||
#define EQEP_O_QPOSMAX 0x4U // Maximum Position Count
|
||||
#define EQEP_O_QPOSCMP 0x6U // Position Compare
|
||||
#define EQEP_O_QPOSILAT 0x8U // Index Position Latch
|
||||
#define EQEP_O_QPOSSLAT 0xAU // Strobe Position Latch
|
||||
#define EQEP_O_QPOSLAT 0xCU // Position Latch
|
||||
#define EQEP_O_QUTMR 0xEU // QEP Unit Timer
|
||||
#define EQEP_O_QUPRD 0x10U // QEP Unit Period
|
||||
#define EQEP_O_QWDTMR 0x12U // QEP Watchdog Timer
|
||||
#define EQEP_O_QWDPRD 0x13U // QEP Watchdog Period
|
||||
#define EQEP_O_QDECCTL 0x14U // Quadrature Decoder Control
|
||||
#define EQEP_O_QEPCTL 0x15U // QEP Control
|
||||
#define EQEP_O_QCAPCTL 0x16U // Qaudrature Capture Control
|
||||
#define EQEP_O_QPOSCTL 0x17U // Position Compare Control
|
||||
#define EQEP_O_QEINT 0x18U // QEP Interrupt Control
|
||||
#define EQEP_O_QFLG 0x19U // QEP Interrupt Flag
|
||||
#define EQEP_O_QCLR 0x1AU // QEP Interrupt Clear
|
||||
#define EQEP_O_QFRC 0x1BU // QEP Interrupt Force
|
||||
#define EQEP_O_QEPSTS 0x1CU // QEP Status
|
||||
#define EQEP_O_QCTMR 0x1DU // QEP Capture Timer
|
||||
#define EQEP_O_QCPRD 0x1EU // QEP Capture Period
|
||||
#define EQEP_O_QCTMRLAT 0x1FU // QEP Capture Latch
|
||||
#define EQEP_O_QCPRDLAT 0x20U // QEP Capture Period Latch
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QDECCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EQEP_QDECCTL_QSP 0x20U // QEPS input polarity
|
||||
#define EQEP_QDECCTL_QIP 0x40U // QEPI input polarity
|
||||
#define EQEP_QDECCTL_QBP 0x80U // QEPB input polarity
|
||||
#define EQEP_QDECCTL_QAP 0x100U // QEPA input polarity
|
||||
#define EQEP_QDECCTL_IGATE 0x200U // Index pulse gating option
|
||||
#define EQEP_QDECCTL_SWAP 0x400U // CLK/DIR Signal Source for Position Counter
|
||||
#define EQEP_QDECCTL_XCR 0x800U // External Clock Rate
|
||||
#define EQEP_QDECCTL_SPSEL 0x1000U // Sync output pin selection
|
||||
#define EQEP_QDECCTL_SOEN 0x2000U // Sync output-enable
|
||||
#define EQEP_QDECCTL_QSRC_S 14U
|
||||
#define EQEP_QDECCTL_QSRC_M 0xC000U // Position-counter source selection
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEPCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EQEP_QEPCTL_WDE 0x1U // QEP watchdog enable
|
||||
#define EQEP_QEPCTL_UTE 0x2U // QEP unit timer enable
|
||||
#define EQEP_QEPCTL_QCLM 0x4U // QEP capture latch mode
|
||||
#define EQEP_QEPCTL_QPEN 0x8U // Quadrature postotion counter enable
|
||||
#define EQEP_QEPCTL_IEL_S 4U
|
||||
#define EQEP_QEPCTL_IEL_M 0x30U // Index event latch
|
||||
#define EQEP_QEPCTL_SEL 0x40U // Strobe event latch
|
||||
#define EQEP_QEPCTL_SWI 0x80U // Software init position counter
|
||||
#define EQEP_QEPCTL_IEI_S 8U
|
||||
#define EQEP_QEPCTL_IEI_M 0x300U // Index event init of position count
|
||||
#define EQEP_QEPCTL_SEI_S 10U
|
||||
#define EQEP_QEPCTL_SEI_M 0xC00U // Strobe event init
|
||||
#define EQEP_QEPCTL_PCRM_S 12U
|
||||
#define EQEP_QEPCTL_PCRM_M 0x3000U // Postion counter reset
|
||||
#define EQEP_QEPCTL_FREE_SOFT_S 14U
|
||||
#define EQEP_QEPCTL_FREE_SOFT_M 0xC000U // Emulation mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QCAPCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EQEP_QCAPCTL_UPPS_S 0U
|
||||
#define EQEP_QCAPCTL_UPPS_M 0xFU // Unit position event prescaler
|
||||
#define EQEP_QCAPCTL_CCPS_S 4U
|
||||
#define EQEP_QCAPCTL_CCPS_M 0x70U // eQEP capture timer clock prescaler
|
||||
#define EQEP_QCAPCTL_CEN 0x8000U // Enable eQEP capture
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QPOSCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EQEP_QPOSCTL_PCSPW_S 0U
|
||||
#define EQEP_QPOSCTL_PCSPW_M 0xFFFU // Position compare sync pulse width
|
||||
#define EQEP_QPOSCTL_PCE 0x1000U // Position compare enable/disable
|
||||
#define EQEP_QPOSCTL_PCPOL 0x2000U // Polarity of sync output
|
||||
#define EQEP_QPOSCTL_PCLOAD 0x4000U // Position compare of shadow load
|
||||
#define EQEP_QPOSCTL_PCSHDW 0x8000U // Position compare of shadow enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEINT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EQEP_QEINT_PCE 0x2U // Position counter error interrupt enable
|
||||
#define EQEP_QEINT_QPE 0x4U // Quadrature phase error interrupt enable
|
||||
#define EQEP_QEINT_QDC 0x8U // Quadrature direction change interrupt enable
|
||||
#define EQEP_QEINT_WTO 0x10U // Watchdog time out interrupt enable
|
||||
#define EQEP_QEINT_PCU 0x20U // Position counter underflow interrupt enable
|
||||
#define EQEP_QEINT_PCO 0x40U // Position counter overflow interrupt enable
|
||||
#define EQEP_QEINT_PCR 0x80U // Position-compare ready interrupt enable
|
||||
#define EQEP_QEINT_PCM 0x100U // Position-compare match interrupt enable
|
||||
#define EQEP_QEINT_SEL 0x200U // Strobe event latch interrupt enable
|
||||
#define EQEP_QEINT_IEL 0x400U // Index event latch interrupt enable
|
||||
#define EQEP_QEINT_UTO 0x800U // Unit time out interrupt enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EQEP_QFLG_INT 0x1U // Global interrupt status flag
|
||||
#define EQEP_QFLG_PCE 0x2U // Position counter error interrupt flag
|
||||
#define EQEP_QFLG_PHE 0x4U // Quadrature phase error interrupt flag
|
||||
#define EQEP_QFLG_QDC 0x8U // Quadrature direction change interrupt flag
|
||||
#define EQEP_QFLG_WTO 0x10U // Watchdog timeout interrupt flag
|
||||
#define EQEP_QFLG_PCU 0x20U // Position counter underflow interrupt flag
|
||||
#define EQEP_QFLG_PCO 0x40U // Position counter overflow interrupt flag
|
||||
#define EQEP_QFLG_PCR 0x80U // Position-compare ready interrupt flag
|
||||
#define EQEP_QFLG_PCM 0x100U // eQEP compare match event interrupt flag
|
||||
#define EQEP_QFLG_SEL 0x200U // Strobe event latch interrupt flag
|
||||
#define EQEP_QFLG_IEL 0x400U // Index event latch interrupt flag
|
||||
#define EQEP_QFLG_UTO 0x800U // Unit time out interrupt flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EQEP_QCLR_INT 0x1U // Global interrupt clear flag
|
||||
#define EQEP_QCLR_PCE 0x2U // Clear position counter error interrupt flag
|
||||
#define EQEP_QCLR_PHE 0x4U // Clear quadrature phase error interrupt flag
|
||||
#define EQEP_QCLR_QDC 0x8U // Clear quadrature direction change interrupt flag
|
||||
#define EQEP_QCLR_WTO 0x10U // Clear watchdog timeout interrupt flag
|
||||
#define EQEP_QCLR_PCU 0x20U // Clear position counter underflow interrupt flag
|
||||
#define EQEP_QCLR_PCO 0x40U // Clear position counter overflow interrupt flag
|
||||
#define EQEP_QCLR_PCR 0x80U // Clear position-compare ready interrupt flag
|
||||
#define EQEP_QCLR_PCM 0x100U // Clear eQEP compare match event interrupt flag
|
||||
#define EQEP_QCLR_SEL 0x200U // Clear strobe event latch interrupt flag
|
||||
#define EQEP_QCLR_IEL 0x400U // Clear index event latch interrupt flag
|
||||
#define EQEP_QCLR_UTO 0x800U // Clear unit time out interrupt flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QFRC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EQEP_QFRC_PCE 0x2U // Force position counter error interrupt
|
||||
#define EQEP_QFRC_PHE 0x4U // Force quadrature phase error interrupt
|
||||
#define EQEP_QFRC_QDC 0x8U // Force quadrature direction change interrupt
|
||||
#define EQEP_QFRC_WTO 0x10U // Force watchdog time out interrupt
|
||||
#define EQEP_QFRC_PCU 0x20U // Force position counter underflow interrupt
|
||||
#define EQEP_QFRC_PCO 0x40U // Force position counter overflow interrupt
|
||||
#define EQEP_QFRC_PCR 0x80U // Force position-compare ready interrupt
|
||||
#define EQEP_QFRC_PCM 0x100U // Force position-compare match interrupt
|
||||
#define EQEP_QFRC_SEL 0x200U // Force strobe event latch interrupt
|
||||
#define EQEP_QFRC_IEL 0x400U // Force index event latch interrupt
|
||||
#define EQEP_QFRC_UTO 0x800U // Force unit time out interrupt
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEPSTS register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define EQEP_QEPSTS_PCEF 0x1U // Position counter error flag.
|
||||
#define EQEP_QEPSTS_FIMF 0x2U // First index marker flag
|
||||
#define EQEP_QEPSTS_CDEF 0x4U // Capture direction error flag
|
||||
#define EQEP_QEPSTS_COEF 0x8U // Capture overflow error flag
|
||||
#define EQEP_QEPSTS_QDLF 0x10U // eQEP direction latch flag
|
||||
#define EQEP_QEPSTS_QDF 0x20U // Quadrature direction flag
|
||||
#define EQEP_QEPSTS_FIDF 0x40U // The first index marker
|
||||
#define EQEP_QEPSTS_UPEVNT 0x80U // Unit position event flag
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,284 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_flash.h
|
||||
//
|
||||
// TITLE: Definitions for the FLASH registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_FLASH_H
|
||||
#define HW_FLASH_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the FLASH register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_O_FRDCNTL 0x0U // Flash Read Control Register
|
||||
#define FLASH_O_FBAC 0x1EU // Flash Bank Access Control Register
|
||||
#define FLASH_O_FBFALLBACK 0x20U // Flash Bank Fallback Power Register
|
||||
#define FLASH_O_FBPRDY 0x22U // Flash Bank Pump Ready Register
|
||||
#define FLASH_O_FPAC1 0x24U // Flash Pump Access Control Register 1
|
||||
#define FLASH_O_FMSTAT 0x2AU // Flash Module Status Register
|
||||
#define FLASH_O_FRD_INTF_CTRL 0x180U // Flash Read Interface Control Register
|
||||
|
||||
#define FLASH_O_ECC_ENABLE 0x0U // ECC Enable
|
||||
#define FLASH_O_SINGLE_ERR_ADDR_LOW 0x2U // Single Error Address Low
|
||||
#define FLASH_O_SINGLE_ERR_ADDR_HIGH 0x4U // Single Error Address High
|
||||
#define FLASH_O_UNC_ERR_ADDR_LOW 0x6U // Uncorrectable Error Address Low
|
||||
#define FLASH_O_UNC_ERR_ADDR_HIGH 0x8U // Uncorrectable Error Address High
|
||||
#define FLASH_O_ERR_STATUS 0xAU // Error Status
|
||||
#define FLASH_O_ERR_POS 0xCU // Error Position
|
||||
#define FLASH_O_ERR_STATUS_CLR 0xEU // Error Status Clear
|
||||
#define FLASH_O_ERR_CNT 0x10U // Error Control
|
||||
#define FLASH_O_ERR_THRESHOLD 0x12U // Error Threshold
|
||||
#define FLASH_O_ERR_INTFLG 0x14U // Error Interrupt Flag
|
||||
#define FLASH_O_ERR_INTCLR 0x16U // Error Interrupt Flag Clear
|
||||
#define FLASH_O_FDATAH_TEST 0x18U // Data High Test
|
||||
#define FLASH_O_FDATAL_TEST 0x1AU // Data Low Test
|
||||
#define FLASH_O_FADDR_TEST 0x1CU // ECC Test Address
|
||||
#define FLASH_O_FECC_TEST 0x1EU // ECC Test Address
|
||||
#define FLASH_O_FECC_CTRL 0x20U // ECC Control
|
||||
#define FLASH_O_FOUTH_TEST 0x22U // Test Data Out High
|
||||
#define FLASH_O_FOUTL_TEST 0x24U // Test Data Out Low
|
||||
#define FLASH_O_FECC_STATUS 0x26U // ECC Status
|
||||
|
||||
#define FLASH_O_PUMPREQUEST 0x0U // Flash programming semaphore PUMP request register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FRDCNTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_FRDCNTL_RWAIT_S 8U
|
||||
#define FLASH_FRDCNTL_RWAIT_M 0xF00U // Random Read Waitstate
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FBAC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_FBAC_VREADST_S 0U
|
||||
#define FLASH_FBAC_VREADST_M 0xFFU // VREAD Setup Time Count
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FBFALLBACK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_FBFALLBACK_BNKPWR0_S 0U
|
||||
#define FLASH_FBFALLBACK_BNKPWR0_M 0x3U // Bank Power Mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FBPRDY register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_FBPRDY_BANKRDY 0x1U // Flash Bank Active Power State
|
||||
#define FLASH_FBPRDY_PUMPRDY 0x8000U // Flash Pump Active Power Mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FPAC1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_FPAC1_PMPPWR 0x1U // Charge Pump Fallback Power Mode
|
||||
#define FLASH_FPAC1_PSLEEP_S 16U
|
||||
#define FLASH_FPAC1_PSLEEP_M 0xFFF0000U // Pump Sleep Down Count
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FMSTAT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_FMSTAT_PSUSP 0x2U // Program Suspend.
|
||||
#define FLASH_FMSTAT_ESUSP 0x4U // Erase Suspend.
|
||||
#define FLASH_FMSTAT_VOLTSTAT 0x8U // Flash Pump Power Status
|
||||
#define FLASH_FMSTAT_CSTAT 0x10U // Command Fail Status
|
||||
#define FLASH_FMSTAT_INVDAT 0x20U // Invalid Data
|
||||
#define FLASH_FMSTAT_PGM 0x40U // Program Operation Status
|
||||
#define FLASH_FMSTAT_ERS 0x80U // Erase Operation Status
|
||||
#define FLASH_FMSTAT_BUSY 0x100U // Busy Bit
|
||||
#define FLASH_FMSTAT_EV 0x400U // Erase Verify Status
|
||||
#define FLASH_FMSTAT_PGV 0x1000U // Programming Verify Status
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FRD_INTF_CTRL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_FRD_INTF_CTRL_PREFETCH_EN 0x1U // Prefetch Enable
|
||||
#define FLASH_FRD_INTF_CTRL_DATA_CACHE_EN 0x2U // Data Cache Enable
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ECC_ENABLE register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_ECC_ENABLE_ENABLE_S 0U
|
||||
#define FLASH_ECC_ENABLE_ENABLE_M 0xFU // Enable ECC
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ERR_STATUS register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_ERR_STATUS_FAIL_0_L 0x1U // Lower 64bits Single Bit Error Corrected Value 0
|
||||
#define FLASH_ERR_STATUS_FAIL_1_L 0x2U // Lower 64bits Single Bit Error Corrected Value 1
|
||||
#define FLASH_ERR_STATUS_UNC_ERR_L 0x4U // Lower 64 bits Uncorrectable error occurred
|
||||
#define FLASH_ERR_STATUS_FAIL_0_H 0x10000U // Upper 64bits Single Bit Error Corrected Value 0
|
||||
#define FLASH_ERR_STATUS_FAIL_1_H 0x20000U // Upper 64bits Single Bit Error Corrected Value 1
|
||||
#define FLASH_ERR_STATUS_UNC_ERR_H 0x40000U // Upper 64 bits Uncorrectable error occurred
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ERR_POS register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_ERR_POS_ERR_POS_L_S 0U
|
||||
#define FLASH_ERR_POS_ERR_POS_L_M 0x3FU // Bit Position of Single bit Error in lower 64
|
||||
// bits
|
||||
#define FLASH_ERR_POS_ERR_TYPE_L 0x100U // Error Type in lower 64 bits
|
||||
#define FLASH_ERR_POS_ERR_POS_H_S 16U
|
||||
#define FLASH_ERR_POS_ERR_POS_H_M 0x3F0000U // Bit Position of Single bit Error in upper 64
|
||||
// bits
|
||||
#define FLASH_ERR_POS_ERR_TYPE_H 0x1000000U // Error Type in upper 64 bits
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ERR_STATUS_CLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_ERR_STATUS_CLR_FAIL_0_L_CLR 0x1U // Lower 64bits Single Bit Error Corrected
|
||||
// Value 0 Clear
|
||||
#define FLASH_ERR_STATUS_CLR_FAIL_1_L_CLR 0x2U // Lower 64bits Single Bit Error Corrected
|
||||
// Value 1 Clear
|
||||
#define FLASH_ERR_STATUS_CLR_UNC_ERR_L_CLR 0x4U // Lower 64 bits Uncorrectable error
|
||||
// occurred Clear
|
||||
#define FLASH_ERR_STATUS_CLR_FAIL_0_H_CLR 0x10000U // Upper 64bits Single Bit Error Corrected
|
||||
// Value 0 Clear
|
||||
#define FLASH_ERR_STATUS_CLR_FAIL_1_H_CLR 0x20000U // Upper 64bits Single Bit Error Corrected
|
||||
// Value 1 Clear
|
||||
#define FLASH_ERR_STATUS_CLR_UNC_ERR_H_CLR 0x40000U // Upper 64 bits Uncorrectable error
|
||||
// occurred Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ERR_CNT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_ERR_CNT_ERR_CNT_S 0U
|
||||
#define FLASH_ERR_CNT_ERR_CNT_M 0xFFFFU // Error counter
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ERR_THRESHOLD register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_S 0U
|
||||
#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_M 0xFFFFU // Error Threshold
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ERR_INTFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_ERR_INTFLG_SINGLE_ERR_INTFLG 0x1U // Single Error Interrupt Flag
|
||||
#define FLASH_ERR_INTFLG_UNC_ERR_INTFLG 0x2U // Uncorrectable Interrupt Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ERR_INTCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_ERR_INTCLR_SINGLE_ERR_INTCLR 0x1U // Single Error Interrupt Flag Clear
|
||||
#define FLASH_ERR_INTCLR_UNC_ERR_INTCLR 0x2U // Uncorrectable Interrupt Flag Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FADDR_TEST register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_FADDR_TEST_ADDRL_S 3U
|
||||
#define FLASH_FADDR_TEST_ADDRL_M 0xFFF8U // ECC Address Low
|
||||
#define FLASH_FADDR_TEST_ADDRH_S 16U
|
||||
#define FLASH_FADDR_TEST_ADDRH_M 0x3F0000U // ECC Address High
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FECC_TEST register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_FECC_TEST_ECC_S 0U
|
||||
#define FLASH_FECC_TEST_ECC_M 0xFFU // ECC Control Bits
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FECC_CTRL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_FECC_CTRL_ECC_TEST_EN 0x1U // Enable ECC Test Logic
|
||||
#define FLASH_FECC_CTRL_ECC_SELECT 0x2U // ECC Bit Select
|
||||
#define FLASH_FECC_CTRL_DO_ECC_CALC 0x4U // Enable ECC Calculation
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FECC_STATUS register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_FECC_STATUS_SINGLE_ERR 0x1U // Test Result is Single Bit Error
|
||||
#define FLASH_FECC_STATUS_UNC_ERR 0x2U // Test Result is Uncorrectable Error
|
||||
#define FLASH_FECC_STATUS_DATA_ERR_POS_S 2U
|
||||
#define FLASH_FECC_STATUS_DATA_ERR_POS_M 0xFCU // Holds Bit Position of Error
|
||||
#define FLASH_FECC_STATUS_ERR_TYPE 0x100U // Holds Bit Position of 8 Check Bits of Error
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PUMPREQUEST register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_S 0U
|
||||
#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_M 0x3U // Flash Pump Request Semaphore between
|
||||
// CPU1 and CPU2
|
||||
#define FLASH_PUMPREQUEST_KEY_S 16U
|
||||
#define FLASH_PUMPREQUEST_KEY_M 0xFFFF0000U // Key Qualifier for writes to this
|
||||
// register
|
||||
|
||||
|
||||
|
||||
#endif
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,342 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_hic.h
|
||||
//
|
||||
// TITLE: Definitions for the HIC registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_HIC_H
|
||||
#define HW_HIC_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the HIC register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_O_REV 0x0U // Module Revision Register
|
||||
#define HIC_O_GCR 0x2U // Global Control Register
|
||||
#define HIC_O_LOCK 0x4U // Lock Register
|
||||
#define HIC_O_MODECR 0x6U // Mode Control Register
|
||||
#define HIC_O_PINPOLCR 0x8U // Pin Polarity Control Register
|
||||
#define HIC_O_BASESEL 0xAU // Base Select Register
|
||||
#define HIC_O_HOSTCR 0xCU // Host Control Register
|
||||
#define HIC_O_ERRADDR 0xEU // Host Error Address register
|
||||
#define HIC_O_H2DTOKEN 0x10U // Host to Device Token Register
|
||||
#define HIC_O_D2HTOKEN 0x12U // Devie to Host Token Register
|
||||
#define HIC_O_DBADDR0 0x14U // Device Base Address Register 0
|
||||
#define HIC_O_DBADDR1 0x16U // Device Base Address Register 1
|
||||
#define HIC_O_DBADDR2 0x18U // Device Base Address Register 2
|
||||
#define HIC_O_DBADDR3 0x1AU // Device Base Address Register 3
|
||||
#define HIC_O_DBADDR4 0x1CU // Device Base Address Register 4
|
||||
#define HIC_O_DBADDR5 0x1EU // Device Base Address Register 5
|
||||
#define HIC_O_DBADDR6 0x20U // Device Base Address Register 6
|
||||
#define HIC_O_DBADDR7 0x22U // Device Base Address Register 7
|
||||
#define HIC_O_H2DINTEN 0x28U // H2D Interrupt Enable
|
||||
#define HIC_O_H2DINTFLG 0x2AU // H2D Interrupt status Flag
|
||||
#define HIC_O_H2DINTCLR 0x2CU // H2D Interrupt status Clear
|
||||
#define HIC_O_H2DINTFRC 0x2EU // H2D Interrupt Set Force
|
||||
#define HIC_O_D2HINTEN 0x30U // D2H Interrupt Enable
|
||||
#define HIC_O_D2HINTFLG 0x32U // D2H Interrupt status Flag
|
||||
#define HIC_O_D2HINTCLR 0x34U // D2H Interrupt status Clear
|
||||
#define HIC_O_D2HINTFRC 0x36U // D2H Interrupt Set Force
|
||||
#define HIC_O_ACCVIOADDR 0x38U // Access Violation Address
|
||||
#define HIC_O_H2D_BUF0 0x40U // Host to Device Buffer 0
|
||||
#define HIC_O_H2D_BUF1 0x42U // Host to Device Buffer 1
|
||||
#define HIC_O_H2D_BUF2 0x44U // Host to Device Buffer 2
|
||||
#define HIC_O_H2D_BUF3 0x46U // Host to Device Buffer 3
|
||||
#define HIC_O_H2D_BUF4 0x48U // Host to Device Buffer 4
|
||||
#define HIC_O_H2D_BUF5 0x4AU // Host to Device Buffer 5
|
||||
#define HIC_O_H2D_BUF6 0x4CU // Host to Device Buffer 6
|
||||
#define HIC_O_H2D_BUF7 0x4EU // Host to Device Buffer 7
|
||||
#define HIC_O_H2D_BUF8 0x50U // Host to Device Buffer 8
|
||||
#define HIC_O_H2D_BUF9 0x52U // Host to Device Buffer 9
|
||||
#define HIC_O_H2D_BUF10 0x54U // Host to Device Buffer 10
|
||||
#define HIC_O_H2D_BUF11 0x56U // Host to Device Buffer 11
|
||||
#define HIC_O_H2D_BUF12 0x58U // Host to Device Buffer 12
|
||||
#define HIC_O_H2D_BUF13 0x5AU // Host to Device Buffer 13
|
||||
#define HIC_O_H2D_BUF14 0x5CU // Host to Device Buffer 14
|
||||
#define HIC_O_H2D_BUF15 0x5EU // Host to Device Buffer 15
|
||||
#define HIC_O_D2H_BUF0 0x60U // Device to Host Buffer 0
|
||||
#define HIC_O_D2H_BUF1 0x62U // Device to Host Buffer 1
|
||||
#define HIC_O_D2H_BUF2 0x64U // Device to Host Buffer 2
|
||||
#define HIC_O_D2H_BUF3 0x66U // Device to Host Buffer 3
|
||||
#define HIC_O_D2H_BUF4 0x68U // Device to Host Buffer 4
|
||||
#define HIC_O_D2H_BUF5 0x6AU // Device to Host Buffer 5
|
||||
#define HIC_O_D2H_BUF6 0x6CU // Device to Host Buffer 6
|
||||
#define HIC_O_D2H_BUF7 0x6EU // Device to Host Buffer 7
|
||||
#define HIC_O_D2H_BUF8 0x70U // Device to Host Buffer 8
|
||||
#define HIC_O_D2H_BUF9 0x72U // Device to Host Buffer 9
|
||||
#define HIC_O_D2H_BUF10 0x74U // Device to Host Buffer 10
|
||||
#define HIC_O_D2H_BUF11 0x76U // Device to Host Buffer 11
|
||||
#define HIC_O_D2H_BUF12 0x78U // Device to Host Buffer 12
|
||||
#define HIC_O_D2H_BUF13 0x7AU // Device to Host Buffer 13
|
||||
#define HIC_O_D2H_BUF14 0x7CU // Device to Host Buffer 14
|
||||
#define HIC_O_D2H_BUF15 0x7EU // Device to Host Buffer 15
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICREV register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_REV_MINOR_S 0U
|
||||
#define HIC_REV_MINOR_M 0x3FU // Minor Revision Number
|
||||
#define HIC_REV_CUSTOM_S 6U
|
||||
#define HIC_REV_CUSTOM_M 0xC0U // Custom Module Number
|
||||
#define HIC_REV_MAJOR_S 8U
|
||||
#define HIC_REV_MAJOR_M 0x700U // Major Revision Number
|
||||
#define HIC_REV_RTL_S 11U
|
||||
#define HIC_REV_RTL_M 0xF800U // Design Release Number
|
||||
#define HIC_REV_FUNC_S 16U
|
||||
#define HIC_REV_FUNC_M 0xFFF0000U // Functional Release Number
|
||||
#define HIC_REV_SCHEME_S 30U
|
||||
#define HIC_REV_SCHEME_M 0xC0000000U // Defines Scheme for Module
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICGCR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_GCR_HICEN_S 0U
|
||||
#define HIC_GCR_HICEN_M 0xFU // Host Interface Enable
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICLOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_LOCK_LOCK 0x1U // LOCK enable
|
||||
#define HIC_LOCK_WRITE_ENABLE_KEY_S 16U
|
||||
#define HIC_LOCK_WRITE_ENABLE_KEY_M 0xFFFF0000U // Key for enabling write
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICMODECR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_MODECR_DW_MODE_S 0U
|
||||
#define HIC_MODECR_DW_MODE_M 0x3U // Data Width Mode
|
||||
#define HIC_MODECR_RW_MODE 0x10U // Read-Write Mode
|
||||
#define HIC_MODECR_BEN_PRESENT 0x20U // Byte Enable Pins are present
|
||||
#define HIC_MODECR_RDY_PRESENT 0x40U // Ready pin present
|
||||
#define HIC_MODECR_H2DBUF_DEVWREN 0x100U // Write Enable for Device to H2D Buffer
|
||||
#define HIC_MODECR_D2HBUF_HOSTWREN 0x200U // Write Enable for Host to D2H Buffer
|
||||
#define HIC_MODECR_EN_DEVACC 0x400U // Enable Host access to Device region
|
||||
#define HIC_MODECR_EN_HOSTWREALLOW 0x800U // Enable Host Write to EALLOWCTL register
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICPINPOLCR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_PINPOLCR_CS_POL 0x1U // Chip Select Polarity
|
||||
#define HIC_PINPOLCR_BEN_POL 0x2U // Byte Enable Polarity
|
||||
#define HIC_PINPOLCR_OE_POL 0x4U // Output Enable Polarity
|
||||
#define HIC_PINPOLCR_WE_POL 0x8U // Write Enable Polarity
|
||||
#define HIC_PINPOLCR_RDY_POL 0x10U // Ready Polarity
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICBASESEL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_BASESEL_BASE_SELECT_S 0U
|
||||
#define HIC_BASESEL_BASE_SELECT_M 0x7U // Base Select
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICHOSTCR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_HOSTCR_EALLOW_EN 0x1U // EALLOW Enable
|
||||
#define HIC_HOSTCR_ACCSIZE 0x2U // Access Size
|
||||
#define HIC_HOSTCR_PAGESEL 0x4U // Page Select
|
||||
#define HIC_HOSTCR_HKEY_S 8U
|
||||
#define HIC_HOSTCR_HKEY_M 0xFF00U // Host Key
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICERRADDR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_ERRADDR_H2D_ERR_ADDR_S 0U
|
||||
#define HIC_ERRADDR_H2D_ERR_ADDR_M 0xFFU // Address of the Host bus captured upon an
|
||||
// error for Device
|
||||
#define HIC_ERRADDR_H2D_BASE_SEL_S 12U
|
||||
#define HIC_ERRADDR_H2D_BASE_SEL_M 0x7000U // Base Select corresponding to H2D error event
|
||||
#define HIC_ERRADDR_D2H_ERR_ADDR_S 16U
|
||||
#define HIC_ERRADDR_D2H_ERR_ADDR_M 0xFF0000U // Address of the Host bus captured upon an
|
||||
// error for Host
|
||||
#define HIC_ERRADDR_D2H_BASE_SEL_S 28U
|
||||
#define HIC_ERRADDR_D2H_BASE_SEL_M 0x70000000U // Base Select corresponding to D2H error event
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICDBADDR0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_DBADDR0_BASE_ADDR_S 7U
|
||||
#define HIC_DBADDR0_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICDBADDR1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_DBADDR1_BASE_ADDR_S 7U
|
||||
#define HIC_DBADDR1_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICDBADDR2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_DBADDR2_BASE_ADDR_S 7U
|
||||
#define HIC_DBADDR2_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICDBADDR3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_DBADDR3_BASE_ADDR_S 7U
|
||||
#define HIC_DBADDR3_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICDBADDR4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_DBADDR4_BASE_ADDR_S 7U
|
||||
#define HIC_DBADDR4_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICDBADDR5 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_DBADDR5_BASE_ADDR_S 7U
|
||||
#define HIC_DBADDR5_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICDBADDR6 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_DBADDR6_BASE_ADDR_S 7U
|
||||
#define HIC_DBADDR6_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICDBADDR7 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_DBADDR7_BASE_ADDR_S 7U
|
||||
#define HIC_DBADDR7_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICH2DINTEN register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_H2DINTEN_H2D_INTEN 0x1U // Host To Device Interrupt Enable
|
||||
#define HIC_H2DINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable
|
||||
#define HIC_H2DINTEN_ILLWR_INTEN 0x4U // Illegal Write event interrupt enable
|
||||
#define HIC_H2DINTEN_ILLRD_INTEN 0x8U // Illegal Read event interrupt enable
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICH2DINTFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_H2DINTFLG_H2D_FLG 0x1U // Host To Device Interrupt Flag
|
||||
#define HIC_H2DINTFLG_BUSERR_FLG 0x2U // BusError Interrupt Flag
|
||||
#define HIC_H2DINTFLG_ILLWR_FLG 0x4U // Illegal write event interrupt flag
|
||||
#define HIC_H2DINTFLG_ILLRD_FLG 0x8U // Illegal read event interrupt flag
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICH2DINTCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_H2DINTCLR_H2D_CLR 0x1U // Host To Device Interrupt Clear
|
||||
#define HIC_H2DINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear
|
||||
#define HIC_H2DINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear
|
||||
#define HIC_H2DINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICH2DINTFRC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_H2DINTFRC_H2D_INTFRC 0x1U // Host To Device Force Set
|
||||
#define HIC_H2DINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set
|
||||
#define HIC_H2DINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set
|
||||
#define HIC_H2DINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICD2HINTEN register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_D2HINTEN_D2H_INTEN 0x1U // Device to Host Data Ready Interrupt Enable
|
||||
#define HIC_D2HINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable
|
||||
#define HIC_D2HINTEN_ILLWR_INTEN 0x4U // Illegal Write event Interrupt Enable
|
||||
#define HIC_D2HINTEN_ILLRD_INTEN 0x8U // Illegal Read event Interrupt Enable
|
||||
#define HIC_D2HINTEN_ACCVIO_INTEN 0x10U // Access Violation Interrupt Enable
|
||||
#define HIC_D2HINTEN_EVTRIG_INTEN_S 16U
|
||||
#define HIC_D2HINTEN_EVTRIG_INTEN_M 0xFFFF0000U // Event Trigger Interrupt Enable
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICD2HINTFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_D2HINTFLG_D2H_FLG 0x1U // Device to Host Data Ready Flag
|
||||
#define HIC_D2HINTFLG_BUSERR_FLG 0x2U // BusError Flag
|
||||
#define HIC_D2HINTFLG_ILLWR_FLG 0x4U // Illegal Write event Flag
|
||||
#define HIC_D2HINTFLG_ILLRD_FLG 0x8U // Illegal Read event Flag
|
||||
#define HIC_D2HINTFLG_ACCVIO_FLG 0x10U // Access Violation Flag
|
||||
#define HIC_D2HINTFLG_EVTRIG_FLG_S 16U
|
||||
#define HIC_D2HINTFLG_EVTRIG_FLG_M 0xFFFF0000U // Event Trigger Flag
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICD2HINTCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_D2HINTCLR_D2H_CLR 0x1U // Device to Host Interrupt Clear
|
||||
#define HIC_D2HINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear
|
||||
#define HIC_D2HINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear
|
||||
#define HIC_D2HINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear
|
||||
#define HIC_D2HINTCLR_ACCVIO_CLR 0x10U // Access Violation Interrupt Clear
|
||||
#define HIC_D2HINTCLR_EVTRIG_CLR_S 16U
|
||||
#define HIC_D2HINTCLR_EVTRIG_CLR_M 0xFFFF0000U // Event Trigger Interrupt Clear
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HICD2HINTFRC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define HIC_D2HINTFRC_D2H_INTFRC 0x1U // Device to Host Force Set
|
||||
#define HIC_D2HINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set
|
||||
#define HIC_D2HINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set
|
||||
#define HIC_D2HINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set
|
||||
#define HIC_D2HINTFRC_ACCVIO_INTFRC 0x10U // Access Violation Interrupt Force Set
|
||||
#define HIC_D2HINTFRC_EVTRIG_INTFRC_S 16U
|
||||
#define HIC_D2HINTFRC_EVTRIG_INTFRC_M 0xFFFF0000U // Event Trigger Interrupt Force Set
|
||||
|
||||
|
||||
#endif
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,206 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_i2c.h
|
||||
//
|
||||
// TITLE: Definitions for the I2C registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_I2C_H
|
||||
#define HW_I2C_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the I2C register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_O_OAR 0x0U // I2C Own address
|
||||
#define I2C_O_IER 0x1U // I2C Interrupt Enable
|
||||
#define I2C_O_STR 0x2U // I2C Status
|
||||
#define I2C_O_CLKL 0x3U // I2C Clock low-time divider
|
||||
#define I2C_O_CLKH 0x4U // I2C Clock high-time divider
|
||||
#define I2C_O_CNT 0x5U // I2C Data count
|
||||
#define I2C_O_DRR 0x6U // I2C Data receive
|
||||
#define I2C_O_SAR 0x7U // I2C Slave address
|
||||
#define I2C_O_DXR 0x8U // I2C Data Transmit
|
||||
#define I2C_O_MDR 0x9U // I2C Mode
|
||||
#define I2C_O_ISRC 0xAU // I2C Interrupt Source
|
||||
#define I2C_O_EMDR 0xBU // I2C Extended Mode
|
||||
#define I2C_O_PSC 0xCU // I2C Prescaler
|
||||
#define I2C_O_FFTX 0x20U // I2C FIFO Transmit
|
||||
#define I2C_O_FFRX 0x21U // I2C FIFO Receive
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2COAR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_OAR_OAR_S 0U
|
||||
#define I2C_OAR_OAR_M 0x3FFU // I2C Own address
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2CIER register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_IER_ARBL 0x1U // Arbitration-lost interrupt enable
|
||||
#define I2C_IER_NACK 0x2U // No-acknowledgment interrupt enable
|
||||
#define I2C_IER_ARDY 0x4U // Register-access-ready interrupt enable
|
||||
#define I2C_IER_RRDY 0x8U // Receive-data-ready interrupt enable
|
||||
#define I2C_IER_XRDY 0x10U // Transmit-data-ready interrupt enable
|
||||
#define I2C_IER_SCD 0x20U // Stop condition detected interrupt enable
|
||||
#define I2C_IER_AAS 0x40U // Addressed as slave interrupt enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2CSTR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_STR_ARBL 0x1U // Arbitration-lost interrupt flag bit
|
||||
#define I2C_STR_NACK 0x2U // No-acknowledgment interrupt flag bit.
|
||||
#define I2C_STR_ARDY 0x4U // Register-access-ready interrupt flag bit
|
||||
#define I2C_STR_RRDY 0x8U // Receive-data-ready interrupt flag bit.
|
||||
#define I2C_STR_XRDY 0x10U // Transmit-data-ready interrupt flag bit.
|
||||
#define I2C_STR_SCD 0x20U // Stop condition detected bit.
|
||||
#define I2C_STR_AD0 0x100U // Address 0 bits
|
||||
#define I2C_STR_AAS 0x200U // Addressed-as-slave bit
|
||||
#define I2C_STR_XSMT 0x400U // Transmit shift register empty bit.
|
||||
#define I2C_STR_RSFULL 0x800U // Receive shift register full bit.
|
||||
#define I2C_STR_BB 0x1000U // Bus busy bit.
|
||||
#define I2C_STR_NACKSNT 0x2000U // NACK sent bit.
|
||||
#define I2C_STR_SDIR 0x4000U // Slave direction bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2CDRR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_DRR_DATA_S 0U
|
||||
#define I2C_DRR_DATA_M 0xFFU // Receive data
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2CSAR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_SAR_SAR_S 0U
|
||||
#define I2C_SAR_SAR_M 0x3FFU // Slave Address
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2CDXR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_DXR_DATA_S 0U
|
||||
#define I2C_DXR_DATA_M 0xFFU // Transmit data
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2CMDR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_MDR_BC_S 0U
|
||||
#define I2C_MDR_BC_M 0x7U // Bit count bits.
|
||||
#define I2C_MDR_FDF 0x8U // Free Data Format
|
||||
#define I2C_MDR_STB 0x10U // START Byte Mode
|
||||
#define I2C_MDR_IRS 0x20U // I2C Module Reset
|
||||
#define I2C_MDR_DLB 0x40U // Digital Loopback Mode
|
||||
#define I2C_MDR_RM 0x80U // Repeat Mode
|
||||
#define I2C_MDR_XA 0x100U // Expanded Address Mode
|
||||
#define I2C_MDR_TRX 0x200U // Transmitter Mode
|
||||
#define I2C_MDR_MST 0x400U // Master Mode
|
||||
#define I2C_MDR_STP 0x800U // STOP Condition
|
||||
#define I2C_MDR_STT 0x2000U // START condition bit
|
||||
#define I2C_MDR_FREE 0x4000U // Debug Action
|
||||
#define I2C_MDR_NACKMOD 0x8000U // NACK mode bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2CISRC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_ISRC_INTCODE_S 0U
|
||||
#define I2C_ISRC_INTCODE_M 0x7U // Interrupt code bits.
|
||||
#define I2C_ISRC_WRITE_ZEROS_S 8U
|
||||
#define I2C_ISRC_WRITE_ZEROS_M 0xF00U // Always write all 0s to this field
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2CEMDR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_EMDR_BC 0x1U // Backwards compatibility mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2CPSC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_PSC_IPSC_S 0U
|
||||
#define I2C_PSC_IPSC_M 0xFFU // I2C Prescaler Divide Down
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2CFFTX register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_FFTX_TXFFIL_S 0U
|
||||
#define I2C_FFTX_TXFFIL_M 0x1FU // Transmit FIFO Interrupt Level
|
||||
#define I2C_FFTX_TXFFIENA 0x20U // Transmit FIFO Interrupt Enable
|
||||
#define I2C_FFTX_TXFFINTCLR 0x40U // Transmit FIFO Interrupt Flag Clear
|
||||
#define I2C_FFTX_TXFFINT 0x80U // Transmit FIFO Interrupt Flag
|
||||
#define I2C_FFTX_TXFFST_S 8U
|
||||
#define I2C_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status
|
||||
#define I2C_FFTX_TXFFRST 0x2000U // Transmit FIFO Reset
|
||||
#define I2C_FFTX_I2CFFEN 0x4000U // Transmit FIFO Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2CFFRX register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define I2C_FFRX_RXFFIL_S 0U
|
||||
#define I2C_FFRX_RXFFIL_M 0x1FU // Receive FIFO Interrupt Level
|
||||
#define I2C_FFRX_RXFFIENA 0x20U // Receive FIFO Interrupt Enable
|
||||
#define I2C_FFRX_RXFFINTCLR 0x40U // Receive FIFO Interrupt Flag Clear
|
||||
#define I2C_FFRX_RXFFINT 0x80U // Receive FIFO Interrupt Flag
|
||||
#define I2C_FFRX_RXFFST_S 8U
|
||||
#define I2C_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status
|
||||
#define I2C_FFRX_RXFFRST 0x2000U // Receive FIFO Reset
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,90 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_inputxbar.h
|
||||
//
|
||||
// TITLE: Definitions for the XBAR registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_INPUTXBAR_H
|
||||
#define HW_INPUTXBAR_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the XBAR register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define XBAR_O_INPUT1SELECT 0x0U // INPUT1 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT2SELECT 0x1U // INPUT2 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT3SELECT 0x2U // INPUT3 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT4SELECT 0x3U // INPUT4 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT5SELECT 0x4U // INPUT5 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT6SELECT 0x5U // INPUT6 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT7SELECT 0x6U // INPUT7 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT8SELECT 0x7U // INPUT8 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT9SELECT 0x8U // INPUT9 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT10SELECT 0x9U // INPUT10 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT11SELECT 0xAU // INPUT11 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT12SELECT 0xBU // INPUT12 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT13SELECT 0xCU // INPUT13 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUT14SELECT 0xDU // INPUT14 Input Select Register (GPIO0 to x)
|
||||
#define XBAR_O_INPUTSELECTLOCK 0x1EU // Input Select Lock Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the INPUTSELECTLOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT1SELECT 0x1U // Lock bit for INPUT1SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT2SELECT 0x2U // Lock bit for INPUT2SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT3SELECT 0x4U // Lock bit for INPUT3SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT4SELECT 0x8U // Lock bit for INPUT4SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT5SELECT 0x10U // Lock bit for INPUT5SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT6SELECT 0x20U // Lock bit for INPUT6SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT7SELECT 0x40U // Lock bit for INPUT7SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT8SELECT 0x80U // Lock bit for INPUT8SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT9SELECT 0x100U // Lock bit for INPUT9SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT10SELECT 0x200U // Lock bit for INPUT10SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT11SELECT 0x400U // Lock bit for INPUT11SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT12SELECT 0x800U // Lock bit for INPUT12SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT13SELECT 0x1000U // Lock bit for INPUT13SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT14SELECT 0x2000U // Lock bit for INPUT14SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT15SELECT 0x4000U // Lock bit for INPUT15SELECT Register
|
||||
#define XBAR_INPUTSELECTLOCK_INPUT16SELECT 0x8000U // Lock bit for INPUT16SELECT Register
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,212 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_ints.h
|
||||
//
|
||||
// TITLE: Definitions of interrupt numbers for use with interrupt.c.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
//
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_INTS_H
|
||||
#define HW_INTS_H
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PIE Interrupt Numbers
|
||||
//
|
||||
// 0x00FF = PIE Table Row #
|
||||
// 0xFF00 = PIE Table Column #
|
||||
// 0xFFFF0000 = PIE Vector ID
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
// Lower PIE Group 1
|
||||
#define INT_ADCA1 0x00200101U // 1.1 - ADCA Interrupt 1
|
||||
#define INT_ADCB1 0x00210102U // 1.2 - ADCB Interrupt 1
|
||||
#define INT_ADCC1 0x00220103U // 1.3 - ADCC Interrupt 1
|
||||
#define INT_XINT1 0x00230104U // 1.4 - XINT1 Interrupt
|
||||
#define INT_XINT2 0x00240105U // 1.5 - XINT2 Interrupt
|
||||
#define INT_ADCD1 0x00250106U // 1.6 - ADCD Interrupt 1
|
||||
#define INT_TIMER0 0x00260107U // 1.7 - Timer 0 Interrupt
|
||||
#define INT_WAKE 0x00270108U // 1.8 - Standby and Halt Wakeup Interrupt
|
||||
|
||||
// Lower PIE Group 2
|
||||
#define INT_EPWM1_TZ 0x00280201U // 2.1 - ePWM1 Trip Zone Interrupt
|
||||
#define INT_EPWM2_TZ 0x00290202U // 2.2 - ePWM2 Trip Zone Interrupt
|
||||
#define INT_EPWM3_TZ 0x002A0203U // 2.3 - ePWM3 Trip Zone Interrupt
|
||||
#define INT_EPWM4_TZ 0x002B0204U // 2.4 - ePWM4 Trip Zone Interrupt
|
||||
#define INT_EPWM5_TZ 0x002C0205U // 2.5 - ePWM5 Trip Zone Interrupt
|
||||
#define INT_EPWM6_TZ 0x002D0206U // 2.6 - ePWM6 Trip Zone Interrupt
|
||||
#define INT_EPWM7_TZ 0x002E0207U // 2.7 - ePWM7 Trip Zone Interrupt
|
||||
#define INT_EPWM8_TZ 0x002F0208U // 2.8 - ePWM8 Trip Zone Interrupt
|
||||
|
||||
// Lower PIE Group 3
|
||||
#define INT_EPWM1 0x00300301U // 3.1 - ePWM1 Interrupt
|
||||
#define INT_EPWM2 0x00310302U // 3.2 - ePWM2 Interrupt
|
||||
#define INT_EPWM3 0x00320303U // 3.3 - ePWM3 Interrupt
|
||||
#define INT_EPWM4 0x00330304U // 3.4 - ePWM4 Interrupt
|
||||
#define INT_EPWM5 0x00340305U // 3.5 - ePWM5 Interrupt
|
||||
#define INT_EPWM6 0x00350306U // 3.6 - ePWM6 Interrupt
|
||||
#define INT_EPWM7 0x00360307U // 3.7 - ePWM7 Interrupt
|
||||
#define INT_EPWM8 0x00370308U // 3.8 - ePWM8 Interrupt
|
||||
|
||||
// Lower PIE Group 4
|
||||
#define INT_ECAP1 0x00380401U // 4.1 - eCAP1 Interrupt
|
||||
#define INT_ECAP2 0x00390402U // 4.2 - eCAP2 Interrupt
|
||||
#define INT_ECAP3 0x003A0403U // 4.3 - eCAP3 Interrupt
|
||||
#define INT_ECAP4 0x003B0404U // 4.4 - eCAP4 Interrupt
|
||||
#define INT_ECAP5 0x003C0405U // 4.5 - eCAP5 Interrupt
|
||||
#define INT_ECAP6 0x003D0406U // 4.6 - eCAP6 Interrupt
|
||||
// Lower PIE Group 5
|
||||
#define INT_EQEP1 0x00400501U // 5.1 - eQEP1 Interrupt
|
||||
#define INT_EQEP2 0x00410502U // 5.2 - eQEP2 Interrupt
|
||||
#define INT_EQEP3 0x00420503U // 5.3 - eQEP3 Interrupt
|
||||
#define INT_CLB1 0x00440505U // 5.5 - CLB1 (Reconfigurable Logic) Interrupt
|
||||
#define INT_CLB2 0x00450506U // 5.6 - CLB2 (Reconfigurable Logic) Interrupt
|
||||
#define INT_CLB3 0x00460507U // 5.7 - CLB3 (Reconfigurable Logic) Interrupt
|
||||
#define INT_CLB4 0x00470508U // 5.8 - CLB4 (Reconfigurable Logic) Interrupt
|
||||
|
||||
// Lower PIE Group 6
|
||||
#define INT_SPIA_RX 0x00480601U // 6.1 - SPIA Receive Interrupt
|
||||
#define INT_SPIA_TX 0x00490602U // 6.2 - SPIA Transmit Interrupt
|
||||
#define INT_SPIB_RX 0x004A0603U // 6.3 - SPIB Receive Interrupt
|
||||
#define INT_SPIB_TX 0x004B0604U // 6.4 - SPIB Transmit Interrupt
|
||||
#define INT_MCBSPA_RX 0x004C0605U // 6.5 - McBSPA Receive Interrupt
|
||||
#define INT_MCBSPA_TX 0x004D0606U // 6.6 - McBSPA Transmit Interrupt
|
||||
#define INT_MCBSPB_RX 0x004E0607U // 6.7 - McBSPB Receive Interrupt
|
||||
#define INT_MCBSPB_TX 0x004F0608U // 6.8 - McBSPB Transmit Interrupt
|
||||
|
||||
// Lower PIE Group 7
|
||||
#define INT_DMA_CH1 0x00500701U // 7.1 - DMA Channel 1 Interrupt
|
||||
#define INT_DMA_CH2 0x00510702U // 7.2 - DMA Channel 2 Interrupt
|
||||
#define INT_DMA_CH3 0x00520703U // 7.3 - DMA Channel 3 Interrupt
|
||||
#define INT_DMA_CH4 0x00530704U // 7.4 - DMA Channel 4 Interrupt
|
||||
#define INT_DMA_CH5 0x00540705U // 7.5 - DMA Channel 5 Interrupt
|
||||
#define INT_DMA_CH6 0x00550706U // 7.6 - DMA Channel 6 Interrupt
|
||||
|
||||
// Lower PIE Group 8
|
||||
#define INT_I2CA 0x00580801U // 8.1 - I2CA Interrupt 1
|
||||
#define INT_I2CA_FIFO 0x00590802U // 8.2 - I2CA Interrupt 2
|
||||
#define INT_I2CB 0x005A0803U // 8.3 - I2CB Interrupt 1
|
||||
#define INT_I2CB_FIFO 0x005B0804U // 8.4 - I2CB Interrupt 2
|
||||
#define INT_SCIC_RX 0x005C0805U // 8.5 - SCIC Receive Interrupt
|
||||
#define INT_SCIC_TX 0x005D0806U // 8.6 - SCIC Transmit Interrupt
|
||||
#define INT_SCID_RX 0x005E0807U // 8.7 - SCID Receive Interrupt
|
||||
#define INT_SCID_TX 0x005F0808U // 8.8 - SCID Transmit Interrupt
|
||||
|
||||
// Lower PIE Group 9
|
||||
#define INT_SCIA_RX 0x00600901U // 9.1 - SCIA Receive Interrupt
|
||||
#define INT_SCIA_TX 0x00610902U // 9.2 - SCIA Transmit Interrupt
|
||||
#define INT_SCIB_RX 0x00620903U // 9.3 - SCIB Receive Interrupt
|
||||
#define INT_SCIB_TX 0x00630904U // 9.4 - SCIB Transmit Interrupt
|
||||
#define INT_CANA0 0x00640905U // 9.5 - CANA Interrupt 0
|
||||
#define INT_CANA1 0x00650906U // 9.6 - CANA Interrupt 1
|
||||
#define INT_CANB0 0x00660907U // 9.7 - CANB Interrupt 0
|
||||
#define INT_CANB1 0x00670908U // 9.8 - CANB Interrupt 1
|
||||
|
||||
// Lower PIE Group 10
|
||||
#define INT_ADCA_EVT 0x00680A01U // 10.1 - ADCA Event Interrupt
|
||||
#define INT_ADCA2 0x00690A02U // 10.2 - ADCA Interrupt 2
|
||||
#define INT_ADCA3 0x006A0A03U // 10.3 - ADCA Interrupt 3
|
||||
#define INT_ADCA4 0x006B0A04U // 10.4 - ADCA Interrupt 4
|
||||
#define INT_ADCB_EVT 0x006C0A05U // 10.5 - ADCB Event Interrupt
|
||||
#define INT_ADCB2 0x006D0A06U // 10.6 - ADCB Interrupt 2
|
||||
#define INT_ADCB3 0x006E0A07U // 10.7 - ADCB Interrupt 3
|
||||
#define INT_ADCB4 0x006F0A08U // 10.8 - ADCB Interrupt 4
|
||||
|
||||
// Lower PIE Group 11
|
||||
#define INT_CLA1_1 0x00700B01U // 11.1 - CLA1 Interrupt 1
|
||||
#define INT_CLA1_2 0x00710B02U // 11.2 - CLA1 Interrupt 2
|
||||
#define INT_CLA1_3 0x00720B03U // 11.3 - CLA1 Interrupt 3
|
||||
#define INT_CLA1_4 0x00730B04U // 11.4 - CLA1 Interrupt 4
|
||||
#define INT_CLA1_5 0x00740B05U // 11.5 - CLA1 Interrupt 5
|
||||
#define INT_CLA1_6 0x00750B06U // 11.6 - CLA1 Interrupt 6
|
||||
#define INT_CLA1_7 0x00760B07U // 11.7 - CLA1 Interrupt 7
|
||||
#define INT_CLA1_8 0x00770B08U // 11.8 - CLA1 Interrupt 8
|
||||
|
||||
// Lower PIE Group 12
|
||||
#define INT_XINT3 0x00780C01U // 12.1 - XINT3 Interrupt
|
||||
#define INT_XINT4 0x00790C02U // 12.2 - XINT4 Interrupt
|
||||
#define INT_XINT5 0x007A0C03U // 12.3 - XINT5 Interrupt
|
||||
#define INT_PBIST 0x007B0C04U // 12.4 - PBIST Interrupt
|
||||
#define INT_FMC 0x007C0C05U // 12.5 - Flash Wrapper Operation Done Interrupt
|
||||
#define INT_VCU 0x007D0C06U // 12.6 - VCU Interrupt
|
||||
#define INT_FPU_OVERFLOW 0x007E0C07U // 12.7 - FPU Overflow Interrupt
|
||||
#define INT_FPU_UNDERFLOW 0x007F0C08U // 12.8 - FPU Underflow Interrupt
|
||||
|
||||
// Upper PIE Group 1
|
||||
#define INT_IPC_0 0x0084010DU // 1.13 - IPC Interrupt 1
|
||||
#define INT_IPC_1 0x0085010EU // 1.14 - IPC Interrupt 2
|
||||
#define INT_IPC_2 0x0086010FU // 1.15 - IPC Interrupt 3
|
||||
#define INT_IPC_3 0x00870110U // 1.16 - IPC Interrupt 4
|
||||
|
||||
// Upper PIE Group 2
|
||||
#define INT_EPWM9_TZ 0x00880209U // 2.9 - ePWM9 Trip Zone Interrupt
|
||||
#define INT_EPWM10_TZ 0x0089020AU // 2.10 - ePWM10 Trip Zone Interrupt
|
||||
#define INT_EPWM11_TZ 0x008A020BU // 2.11 - ePWM11 Trip Zone Interrupt
|
||||
#define INT_EPWM12_TZ 0x008B020CU // 2.12 - ePWM12 Trip Zone Interrupt
|
||||
|
||||
// Upper PIE Group 3
|
||||
#define INT_EPWM9 0x00900309U // 3.9 - ePWM9 Interrupt
|
||||
#define INT_EPWM10 0x0091030AU // 3.10 - ePWM10 Interrupt
|
||||
#define INT_EPWM11 0x0092030BU // 3.11 - ePWM11 Interrupt
|
||||
#define INT_EPWM12 0x0093030CU // 3.12 - ePWM12 Interrupt
|
||||
|
||||
// Upper PIE Group 5
|
||||
#define INT_SD1 0x00A00509U // 5.9 - SD1 Interrupt
|
||||
#define INT_SD2 0x00A1050AU // 5.10 - SD2 Interrupt
|
||||
|
||||
// Upper PIE Group 6
|
||||
#define INT_SPIC_RX 0x00A80609U // 6.9 - SPIC Receive Interrupt
|
||||
#define INT_SPIC_TX 0x00A9060AU // 6.10 - SPIC Transmit Interrupt
|
||||
|
||||
// Upper PIE Group 8
|
||||
#define INT_UPPA 0x00BE080FU // 8.15 - uPPA Interrupt
|
||||
|
||||
// Upper PIE Group 9
|
||||
#define INT_USBA 0x00C6090FU // 9.15 - USBA Interrupt
|
||||
|
||||
// Upper PIE Group 10
|
||||
#define INT_ADCC_EVT 0x00C80A09U // 10.9 - ADCC Event Interrupt
|
||||
#define INT_ADCC2 0x00C90A0AU // 10.10 - ADCC Interrupt 2
|
||||
#define INT_ADCC3 0x00CA0A0BU // 10.11 - ADCC Interrupt 3
|
||||
#define INT_ADCC4 0x00CB0A0CU // 10.12 - ADCC Interrupt 4
|
||||
#define INT_ADCD_EVT 0x00CC0A0DU // 10.13 - ADCD Event Interrupt
|
||||
#define INT_ADCD2 0x00CD0A0EU // 10.14 - ADCD Interrupt 2
|
||||
#define INT_ADCD3 0x00CE0A0FU // 10.15 - ADCD Interrupt 3
|
||||
#define INT_ADCD4 0x00CF0A10U // 10.16 - ADCD Interrupt 4
|
||||
|
||||
// Upper PIE Group 12
|
||||
#define INT_EMIF_ERROR 0x00D80C09U // 12.9 - EMIF Error Interrupt
|
||||
#define INT_RAM_CORR_ERR 0x00D90C0AU // 12.10 - RAM Correctable Error Interrupt
|
||||
#define INT_FLASH_CORR_ERR 0x00DA0C0BU // 12.11 - Flash Correctable Error Interrupt
|
||||
#define INT_RAM_ACC_VIOL 0x00DB0C0CU // 12.12 - RAM Access Violation Interrupt
|
||||
#define INT_SYS_PLL_SLIP 0x00DC0C0DU // 12.13 - System PLL Slip Interrupt
|
||||
#define INT_AUX_PLL_SLIP 0x00DD0C0EU // 12.14 - Auxiliary PLL Slip Interrupt
|
||||
#define INT_CLA_OVERFLOW 0x00DE0C0FU // 12.15 - CLA Overflow Interrupt
|
||||
#define INT_CLA_UNDERFLOW 0x00DF0C10U // 12.16 - CLA Underflow Interrupt
|
||||
|
||||
// Other interrupts
|
||||
#define INT_TIMER1 0x000D0000U // CPU Timer 1 Interrupt
|
||||
#define INT_TIMER2 0x000E0000U // CPU Timer 2 Interrupt
|
||||
#define INT_DATALOG 0x000F0000U // Datalogging Interrupt
|
||||
#define INT_RTOS 0x00100000U // RTOS Interrupt
|
||||
#define INT_EMU 0x00110000U // Emulation Interrupt
|
||||
#define INT_NMI 0x00120000U // Non-Maskable Interrupt
|
||||
#define INT_ILLEGAL 0x00130000U // Illegal Operation Trap
|
||||
#define INT_USER1 0x00140000U // User Defined Trap 1
|
||||
#define INT_USER2 0x00150000U // User Defined Trap 2
|
||||
#define INT_USER3 0x00160000U // User Defined Trap 3
|
||||
#define INT_USER4 0x00170000U // User Defined Trap 4
|
||||
#define INT_USER5 0x00180000U // User Defined Trap 5
|
||||
#define INT_USER6 0x00190000U // User Defined Trap 6
|
||||
#define INT_USER7 0x001A0000U // User Defined Trap 7
|
||||
#define INT_USER8 0x001B0000U // User Defined Trap 8
|
||||
#define INT_USER9 0x001C0000U // User Defined Trap 9
|
||||
#define INT_USER10 0x001D0000U // User Defined Trap 10
|
||||
#define INT_USER11 0x001E0000U // User Defined Trap 11
|
||||
#define INT_USER12 0x001F0000U // User Defined Trap 12
|
||||
|
||||
#endif // HW_INTS_H
|
|
@ -0,0 +1,321 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_ipc.h
|
||||
//
|
||||
// TITLE: Definitions for the IPC registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_IPC_H
|
||||
#define HW_IPC_H
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the IPC register offsets
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define IPC_O_ACK 0x0U // IPC incoming flag clear
|
||||
// (acknowledge) register
|
||||
#define IPC_O_STS 0x2U // IPC incoming flag status
|
||||
// register
|
||||
#define IPC_O_SET 0x4U // IPC remote flag set register
|
||||
#define IPC_O_CLR 0x6U // IPC remote flag clear
|
||||
// register
|
||||
#define IPC_O_FLG 0x8U // IPC remote flag status
|
||||
// register
|
||||
#define IPC_O_COUNTERL 0xCU // IPC Counter Low Register
|
||||
#define IPC_O_COUNTERH 0xEU // IPC Counter High Register
|
||||
#ifndef CPU2
|
||||
#define IPC_O_SENDCOM 0x10U // Local to Remote IPC Command
|
||||
// Register
|
||||
#define IPC_O_SENDADDR 0x12U // Local to Remote IPC Address
|
||||
// Register
|
||||
#define IPC_O_SENDDATA 0x14U // Local to Remote IPC Data
|
||||
// Register
|
||||
#define IPC_O_REMOTEREPLY 0x16U // Remote to Local IPC Reply
|
||||
// Data Register
|
||||
#define IPC_O_RECVCOM 0x18U // Remote to Local IPC Command
|
||||
// Register
|
||||
#define IPC_O_RECVADDR 0x1AU // Remote to Local IPC Address
|
||||
// Register
|
||||
#define IPC_O_RECVDATA 0x1CU // Remote to Local IPC Data
|
||||
// Register
|
||||
#define IPC_O_LOCALREPLY 0x1EU // Local to Remote IPC Reply
|
||||
// Data Register
|
||||
#else
|
||||
#define IPC_O_RECVCOM 0x10U // Remote to Local IPC Command
|
||||
// Register
|
||||
#define IPC_O_RECVADDR 0x12U // Remote to Local IPC Address
|
||||
// Register
|
||||
#define IPC_O_RECVDATA 0x14U // Remote to Local IPC Data
|
||||
// Register
|
||||
#define IPC_O_LOCALREPLY 0x16U // Local to Remote IPC Reply
|
||||
// Data Register
|
||||
#define IPC_O_SENDCOM 0x18U // Local to Remote IPC Command
|
||||
// Register
|
||||
#define IPC_O_SENDADDR 0x1AU // Local to Remote IPC Address
|
||||
// Register
|
||||
#define IPC_O_SENDDATA 0x1CU // Local to Remote IPC Data
|
||||
// Register
|
||||
#define IPC_O_REMOTEREPLY 0x1EU // Remote to Local IPC Reply
|
||||
// Data Register
|
||||
#endif
|
||||
#define IPC_O_BOOTSTS 0x20U // CPU2 to CPU1 IPC Boot Status
|
||||
// Register
|
||||
#define IPC_O_BOOTMODE 0x22U // CPU1 to CPU2 IPC Boot Mode
|
||||
// Register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the IPCACK register
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define IPC_ACK_IPC0 0x1U // Local IPC Flag 0
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC1 0x2U // Local IPC Flag 1
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC2 0x4U // Local IPC Flag 2
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC3 0x8U // Local IPC Flag 3
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC4 0x10U // Local IPC Flag 4
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC5 0x20U // Local IPC Flag 5
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC6 0x40U // Local IPC Flag 6
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC7 0x80U // Local IPC Flag 7
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC8 0x100U // Local IPC Flag 8
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC9 0x200U // Local IPC Flag 9
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC10 0x400U // Local IPC Flag 10
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC11 0x800U // Local IPC Flag 11
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC12 0x1000U // Local IPC Flag 12
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC13 0x2000U // Local IPC Flag 13
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC14 0x4000U // Local IPC Flag 14
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC15 0x8000U // Local IPC Flag 15
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC16 0x10000U // Local IPC Flag 16
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC17 0x20000U // Local IPC Flag 17
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC18 0x40000U // Local IPC Flag 18
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC19 0x80000U // Local IPC Flag 19
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC20 0x100000U // Local IPC Flag 20
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC21 0x200000U // Local IPC Flag 21
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC22 0x400000U // Local IPC Flag 22
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC23 0x800000U // Local IPC Flag 23
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC24 0x1000000U // Local IPC Flag 24
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC25 0x2000000U // Local IPC Flag 25
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC26 0x4000000U // Local IPC Flag 26
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC27 0x8000000U // Local IPC Flag 27
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC28 0x10000000U // Local IPC Flag 28
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC29 0x20000000U // Local IPC Flag 29
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC30 0x40000000U // Local IPC Flag 30
|
||||
// Acknowledgement
|
||||
#define IPC_ACK_IPC31 0x80000000U // Local IPC Flag 31
|
||||
// Acknowledgement
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the IPCSTS register
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define IPC_STS_IPC0 0x1U // Local IPC Flag 0 Status
|
||||
#define IPC_STS_IPC1 0x2U // Local IPC Flag 1 Status
|
||||
#define IPC_STS_IPC2 0x4U // Local IPC Flag 2 Status
|
||||
#define IPC_STS_IPC3 0x8U // Local IPC Flag 3 Status
|
||||
#define IPC_STS_IPC4 0x10U // Local IPC Flag 4 Status
|
||||
#define IPC_STS_IPC5 0x20U // Local IPC Flag 5 Status
|
||||
#define IPC_STS_IPC6 0x40U // Local IPC Flag 6 Status
|
||||
#define IPC_STS_IPC7 0x80U // Local IPC Flag 7 Status
|
||||
#define IPC_STS_IPC8 0x100U // Local IPC Flag 8 Status
|
||||
#define IPC_STS_IPC9 0x200U // Local IPC Flag 9 Status
|
||||
#define IPC_STS_IPC10 0x400U // Local IPC Flag 10 Status
|
||||
#define IPC_STS_IPC11 0x800U // Local IPC Flag 11 Status
|
||||
#define IPC_STS_IPC12 0x1000U // Local IPC Flag 12 Status
|
||||
#define IPC_STS_IPC13 0x2000U // Local IPC Flag 13 Status
|
||||
#define IPC_STS_IPC14 0x4000U // Local IPC Flag 14 Status
|
||||
#define IPC_STS_IPC15 0x8000U // Local IPC Flag 15 Status
|
||||
#define IPC_STS_IPC16 0x10000U // Local IPC Flag 16 Status
|
||||
#define IPC_STS_IPC17 0x20000U // Local IPC Flag 17 Status
|
||||
#define IPC_STS_IPC18 0x40000U // Local IPC Flag 18 Status
|
||||
#define IPC_STS_IPC19 0x80000U // Local IPC Flag 19 Status
|
||||
#define IPC_STS_IPC20 0x100000U // Local IPC Flag 20 Status
|
||||
#define IPC_STS_IPC21 0x200000U // Local IPC Flag 21 Status
|
||||
#define IPC_STS_IPC22 0x400000U // Local IPC Flag 22 Status
|
||||
#define IPC_STS_IPC23 0x800000U // Local IPC Flag 23 Status
|
||||
#define IPC_STS_IPC24 0x1000000U // Local IPC Flag 24 Status
|
||||
#define IPC_STS_IPC25 0x2000000U // Local IPC Flag 25 Status
|
||||
#define IPC_STS_IPC26 0x4000000U // Local IPC Flag 26 Status
|
||||
#define IPC_STS_IPC27 0x8000000U // Local IPC Flag 27 Status
|
||||
#define IPC_STS_IPC28 0x10000000U // Local IPC Flag 28 Status
|
||||
#define IPC_STS_IPC29 0x20000000U // Local IPC Flag 29 Status
|
||||
#define IPC_STS_IPC30 0x40000000U // Local IPC Flag 30 Status
|
||||
#define IPC_STS_IPC31 0x80000000U // Local IPC Flag 31 Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the IPCSET register
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define IPC_SET_IPC0 0x1U // Set Remote IPC0 Flag
|
||||
#define IPC_SET_IPC1 0x2U // Set Remote IPC1 Flag
|
||||
#define IPC_SET_IPC2 0x4U // Set Remote IPC2 Flag
|
||||
#define IPC_SET_IPC3 0x8U // Set Remote IPC3 Flag
|
||||
#define IPC_SET_IPC4 0x10U // Set Remote IPC4 Flag
|
||||
#define IPC_SET_IPC5 0x20U // Set Remote IPC5 Flag
|
||||
#define IPC_SET_IPC6 0x40U // Set Remote IPC6 Flag
|
||||
#define IPC_SET_IPC7 0x80U // Set Remote IPC7 Flag
|
||||
#define IPC_SET_IPC8 0x100U // Set Remote IPC8 Flag
|
||||
#define IPC_SET_IPC9 0x200U // Set Remote IPC9 Flag
|
||||
#define IPC_SET_IPC10 0x400U // Set Remote IPC10 Flag
|
||||
#define IPC_SET_IPC11 0x800U // Set Remote IPC11 Flag
|
||||
#define IPC_SET_IPC12 0x1000U // Set Remote IPC12 Flag
|
||||
#define IPC_SET_IPC13 0x2000U // Set Remote IPC13 Flag
|
||||
#define IPC_SET_IPC14 0x4000U // Set Remote IPC14 Flag
|
||||
#define IPC_SET_IPC15 0x8000U // Set Remote IPC15 Flag
|
||||
#define IPC_SET_IPC16 0x10000U // Set Remote IPC16 Flag
|
||||
#define IPC_SET_IPC17 0x20000U // Set Remote IPC17 Flag
|
||||
#define IPC_SET_IPC18 0x40000U // Set Remote IPC18 Flag
|
||||
#define IPC_SET_IPC19 0x80000U // Set Remote IPC19 Flag
|
||||
#define IPC_SET_IPC20 0x100000U // Set Remote IPC20 Flag
|
||||
#define IPC_SET_IPC21 0x200000U // Set Remote IPC21 Flag
|
||||
#define IPC_SET_IPC22 0x400000U // Set Remote IPC22 Flag
|
||||
#define IPC_SET_IPC23 0x800000U // Set Remote IPC23 Flag
|
||||
#define IPC_SET_IPC24 0x1000000U // Set Remote IPC24 Flag
|
||||
#define IPC_SET_IPC25 0x2000000U // Set Remote IPC25 Flag
|
||||
#define IPC_SET_IPC26 0x4000000U // Set Remote IPC26 Flag
|
||||
#define IPC_SET_IPC27 0x8000000U // Set Remote IPC27 Flag
|
||||
#define IPC_SET_IPC28 0x10000000U // Set Remote IPC28 Flag
|
||||
#define IPC_SET_IPC29 0x20000000U // Set Remote IPC29 Flag
|
||||
#define IPC_SET_IPC30 0x40000000U // Set Remote IPC30 Flag
|
||||
#define IPC_SET_IPC31 0x80000000U // Set Remote IPC31 Flag
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the IPCCLR register
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define IPC_CLR_IPC0 0x1U // Clear Remote IPC0 Flag
|
||||
#define IPC_CLR_IPC1 0x2U // Clear Remote IPC1 Flag
|
||||
#define IPC_CLR_IPC2 0x4U // Clear Remote IPC2 Flag
|
||||
#define IPC_CLR_IPC3 0x8U // Clear Remote IPC3 Flag
|
||||
#define IPC_CLR_IPC4 0x10U // Clear Remote IPC4 Flag
|
||||
#define IPC_CLR_IPC5 0x20U // Clear Remote IPC5 Flag
|
||||
#define IPC_CLR_IPC6 0x40U // Clear Remote IPC6 Flag
|
||||
#define IPC_CLR_IPC7 0x80U // Clear Remote IPC7 Flag
|
||||
#define IPC_CLR_IPC8 0x100U // Clear Remote IPC8 Flag
|
||||
#define IPC_CLR_IPC9 0x200U // Clear Remote IPC9 Flag
|
||||
#define IPC_CLR_IPC10 0x400U // Clear Remote IPC10 Flag
|
||||
#define IPC_CLR_IPC11 0x800U // Clear Remote IPC11 Flag
|
||||
#define IPC_CLR_IPC12 0x1000U // Clear Remote IPC12 Flag
|
||||
#define IPC_CLR_IPC13 0x2000U // Clear Remote IPC13 Flag
|
||||
#define IPC_CLR_IPC14 0x4000U // Clear Remote IPC14 Flag
|
||||
#define IPC_CLR_IPC15 0x8000U // Clear Remote IPC15 Flag
|
||||
#define IPC_CLR_IPC16 0x10000U // Clear Remote IPC16 Flag
|
||||
#define IPC_CLR_IPC17 0x20000U // Clear Remote IPC17 Flag
|
||||
#define IPC_CLR_IPC18 0x40000U // Clear Remote IPC18 Flag
|
||||
#define IPC_CLR_IPC19 0x80000U // Clear Remote IPC19 Flag
|
||||
#define IPC_CLR_IPC20 0x100000U // Clear Remote IPC20 Flag
|
||||
#define IPC_CLR_IPC21 0x200000U // Clear Remote IPC21 Flag
|
||||
#define IPC_CLR_IPC22 0x400000U // Clear Remote IPC22 Flag
|
||||
#define IPC_CLR_IPC23 0x800000U // Clear Remote IPC23 Flag
|
||||
#define IPC_CLR_IPC24 0x1000000U // Clear Remote IPC24 Flag
|
||||
#define IPC_CLR_IPC25 0x2000000U // Clear Remote IPC25 Flag
|
||||
#define IPC_CLR_IPC26 0x4000000U // Clear Remote IPC26 Flag
|
||||
#define IPC_CLR_IPC27 0x8000000U // Clear Remote IPC27 Flag
|
||||
#define IPC_CLR_IPC28 0x10000000U // Clear Remote IPC28 Flag
|
||||
#define IPC_CLR_IPC29 0x20000000U // Clear Remote IPC29 Flag
|
||||
#define IPC_CLR_IPC30 0x40000000U // Clear Remote IPC30 Flag
|
||||
#define IPC_CLR_IPC31 0x80000000U // Clear Remote IPC31 Flag
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the IPCFLG register
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define IPC_FLG_IPC0 0x1U // Remote IPC0 Flag Status
|
||||
#define IPC_FLG_IPC1 0x2U // Remote IPC1 Flag Status
|
||||
#define IPC_FLG_IPC2 0x4U // Remote IPC2 Flag Status
|
||||
#define IPC_FLG_IPC3 0x8U // Remote IPC3 Flag Status
|
||||
#define IPC_FLG_IPC4 0x10U // Remote IPC4 Flag Status
|
||||
#define IPC_FLG_IPC5 0x20U // Remote IPC5 Flag Status
|
||||
#define IPC_FLG_IPC6 0x40U // Remote IPC6 Flag Status
|
||||
#define IPC_FLG_IPC7 0x80U // Remote IPC7 Flag Status
|
||||
#define IPC_FLG_IPC8 0x100U // Remote IPC8 Flag Status
|
||||
#define IPC_FLG_IPC9 0x200U // Remote IPC9 Flag Status
|
||||
#define IPC_FLG_IPC10 0x400U // Remote IPC10 Flag Status
|
||||
#define IPC_FLG_IPC11 0x800U // Remote IPC11 Flag Status
|
||||
#define IPC_FLG_IPC12 0x1000U // Remote IPC12 Flag Status
|
||||
#define IPC_FLG_IPC13 0x2000U // Remote IPC13 Flag Status
|
||||
#define IPC_FLG_IPC14 0x4000U // Remote IPC14 Flag Status
|
||||
#define IPC_FLG_IPC15 0x8000U // Remote IPC15 Flag Status
|
||||
#define IPC_FLG_IPC16 0x10000U // Remote IPC16 Flag Status
|
||||
#define IPC_FLG_IPC17 0x20000U // Remote IPC17 Flag Status
|
||||
#define IPC_FLG_IPC18 0x40000U // Remote IPC18 Flag Status
|
||||
#define IPC_FLG_IPC19 0x80000U // Remote IPC19 Flag Status
|
||||
#define IPC_FLG_IPC20 0x100000U // Remote IPC20 Flag Status
|
||||
#define IPC_FLG_IPC21 0x200000U // Remote IPC21 Flag Status
|
||||
#define IPC_FLG_IPC22 0x400000U // Remote IPC22 Flag Status
|
||||
#define IPC_FLG_IPC23 0x800000U // Remote IPC23 Flag Status
|
||||
#define IPC_FLG_IPC24 0x1000000U // Remote IPC24 Flag Status
|
||||
#define IPC_FLG_IPC25 0x2000000U // Remote IPC25 Flag Status
|
||||
#define IPC_FLG_IPC26 0x4000000U // Remote IPC26 Flag Status
|
||||
#define IPC_FLG_IPC27 0x8000000U // Remote IPC27 Flag Status
|
||||
#define IPC_FLG_IPC28 0x10000000U // Remote IPC28 Flag Status
|
||||
#define IPC_FLG_IPC29 0x20000000U // Remote IPC29 Flag Status
|
||||
#define IPC_FLG_IPC30 0x40000000U // Remote IPC30 Flag Status
|
||||
#define IPC_FLG_IPC31 0x80000000U // Remote IPC31 Flag Status
|
||||
#endif
|
|
@ -0,0 +1,284 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_mcbsp.h
|
||||
//
|
||||
// TITLE: Definitions for the MCBSP registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_MCBSP_H
|
||||
#define HW_MCBSP_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the MCBSP register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_O_DRR2 0x0U // Data receive register bits 31-16
|
||||
#define MCBSP_O_DRR1 0x1U // Data receive register bits 15-0
|
||||
#define MCBSP_O_DXR2 0x2U // Data transmit register bits 31-16
|
||||
#define MCBSP_O_DXR1 0x3U // Data transmit register bits 15-0
|
||||
#define MCBSP_O_SPCR2 0x4U // Serial port control register 2
|
||||
#define MCBSP_O_SPCR1 0x5U // Serial port control register 1
|
||||
#define MCBSP_O_RCR2 0x6U // Receive Control register 2
|
||||
#define MCBSP_O_RCR1 0x7U // Receive Control register 1
|
||||
#define MCBSP_O_XCR2 0x8U // Transmit Control register 2
|
||||
#define MCBSP_O_XCR1 0x9U // Transmit Control register 1
|
||||
#define MCBSP_O_SRGR2 0xAU // Sample rate generator register 2
|
||||
#define MCBSP_O_SRGR1 0xBU // Sample rate generator register 1
|
||||
#define MCBSP_O_MCR2 0xCU // Multi-channel control register 2
|
||||
#define MCBSP_O_MCR1 0xDU // Multi-channel control register 1
|
||||
#define MCBSP_O_RCERA 0xEU // Receive channel enable partition A
|
||||
#define MCBSP_O_RCERB 0xFU // Receive channel enable partition B
|
||||
#define MCBSP_O_XCERA 0x10U // Transmit channel enable partition A
|
||||
#define MCBSP_O_XCERB 0x11U // Transmit channel enable partition B
|
||||
#define MCBSP_O_PCR 0x12U // Pin Control register
|
||||
#define MCBSP_O_RCERC 0x13U // Receive channel enable partition C
|
||||
#define MCBSP_O_RCERD 0x14U // Receive channel enable partition D
|
||||
#define MCBSP_O_XCERC 0x15U // Transmit channel enable partition C
|
||||
#define MCBSP_O_XCERD 0x16U // Transmit channel enable partition D
|
||||
#define MCBSP_O_RCERE 0x17U // Receive channel enable partition E
|
||||
#define MCBSP_O_RCERF 0x18U // Receive channel enable partition F
|
||||
#define MCBSP_O_XCERE 0x19U // Transmit channel enable partition E
|
||||
#define MCBSP_O_XCERF 0x1AU // Transmit channel enable partition F
|
||||
#define MCBSP_O_RCERG 0x1BU // Receive channel enable partition G
|
||||
#define MCBSP_O_RCERH 0x1CU // Receive channel enable partition H
|
||||
#define MCBSP_O_XCERG 0x1DU // Transmit channel enable partition G
|
||||
#define MCBSP_O_XCERH 0x1EU // Transmit channel enable partition H
|
||||
#define MCBSP_O_MFFINT 0x23U // Interrupt enable
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DRR2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_DRR2_HWLB_S 0U
|
||||
#define MCBSP_DRR2_HWLB_M 0xFFU // High word low byte
|
||||
#define MCBSP_DRR2_HWHB_S 8U
|
||||
#define MCBSP_DRR2_HWHB_M 0xFF00U // High word high byte
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DRR1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_DRR1_LWLB_S 0U
|
||||
#define MCBSP_DRR1_LWLB_M 0xFFU // Low word low byte
|
||||
#define MCBSP_DRR1_LWHB_S 8U
|
||||
#define MCBSP_DRR1_LWHB_M 0xFF00U // Low word high byte
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DXR2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_DXR2_HWLB_S 0U
|
||||
#define MCBSP_DXR2_HWLB_M 0xFFU // High word low byte
|
||||
#define MCBSP_DXR2_HWHB_S 8U
|
||||
#define MCBSP_DXR2_HWHB_M 0xFF00U // High word high byte
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DXR1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_DXR1_LWLB_S 0U
|
||||
#define MCBSP_DXR1_LWLB_M 0xFFU // Low word low byte
|
||||
#define MCBSP_DXR1_LWHB_S 8U
|
||||
#define MCBSP_DXR1_LWHB_M 0xFF00U // Low word high byte
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SPCR2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_SPCR2_XRST 0x1U // Transmitter reset
|
||||
#define MCBSP_SPCR2_XRDY 0x2U // Transmitter ready
|
||||
#define MCBSP_SPCR2_XEMPTY 0x4U // Transmitter empty
|
||||
#define MCBSP_SPCR2_XSYNCERR 0x8U // Transmit sync error INT flag
|
||||
#define MCBSP_SPCR2_XINTM_S 4U
|
||||
#define MCBSP_SPCR2_XINTM_M 0x30U // Transmit Interupt mode bits
|
||||
#define MCBSP_SPCR2_GRST 0x40U // Sample rate generator reset
|
||||
#define MCBSP_SPCR2_FRST 0x80U // Frame sync logic reset
|
||||
#define MCBSP_SPCR2_SOFT 0x100U // SOFT bit
|
||||
#define MCBSP_SPCR2_FREE 0x200U // FREE bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SPCR1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_SPCR1_RRST 0x1U // Receiver reset
|
||||
#define MCBSP_SPCR1_RRDY 0x2U // Receiver ready
|
||||
#define MCBSP_SPCR1_RFULL 0x4U // Receiver full
|
||||
#define MCBSP_SPCR1_RSYNCERR 0x8U // Receive sync error INT flag
|
||||
#define MCBSP_SPCR1_RINTM_S 4U
|
||||
#define MCBSP_SPCR1_RINTM_M 0x30U // Receive Interupt mode bits
|
||||
#define MCBSP_SPCR1_DXENA 0x80U // DX delay enable
|
||||
#define MCBSP_SPCR1_CLKSTP_S 11U
|
||||
#define MCBSP_SPCR1_CLKSTP_M 0x1800U // Clock stop mode
|
||||
#define MCBSP_SPCR1_RJUST_S 13U
|
||||
#define MCBSP_SPCR1_RJUST_M 0x6000U // Rx sign extension and justification mode
|
||||
#define MCBSP_SPCR1_DLB 0x8000U // Digital loopback
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the RCR2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_RCR2_RDATDLY_S 0U
|
||||
#define MCBSP_RCR2_RDATDLY_M 0x3U // Receive data delay
|
||||
#define MCBSP_RCR2_RFIG 0x4U // Receive frame sync ignore
|
||||
#define MCBSP_RCR2_RCOMPAND_S 3U
|
||||
#define MCBSP_RCR2_RCOMPAND_M 0x18U // Receive Companding Mode selects
|
||||
#define MCBSP_RCR2_RWDLEN2_S 5U
|
||||
#define MCBSP_RCR2_RWDLEN2_M 0xE0U // Receive word length 2
|
||||
#define MCBSP_RCR2_RFRLEN2_S 8U
|
||||
#define MCBSP_RCR2_RFRLEN2_M 0x7F00U // Receive Frame length 2
|
||||
#define MCBSP_RCR2_RPHASE 0x8000U // Receive Phase
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the RCR1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_RCR1_RWDLEN1_S 5U
|
||||
#define MCBSP_RCR1_RWDLEN1_M 0xE0U // Receive word length 1
|
||||
#define MCBSP_RCR1_RFRLEN1_S 8U
|
||||
#define MCBSP_RCR1_RFRLEN1_M 0x7F00U // Receive Frame length 1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the XCR2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_XCR2_XDATDLY_S 0U
|
||||
#define MCBSP_XCR2_XDATDLY_M 0x3U // Transmit data delay
|
||||
#define MCBSP_XCR2_XFIG 0x4U // Transmit frame sync ignore
|
||||
#define MCBSP_XCR2_XCOMPAND_S 3U
|
||||
#define MCBSP_XCR2_XCOMPAND_M 0x18U // Transmit Companding Mode selects
|
||||
#define MCBSP_XCR2_XWDLEN2_S 5U
|
||||
#define MCBSP_XCR2_XWDLEN2_M 0xE0U // Transmit word length 2
|
||||
#define MCBSP_XCR2_XFRLEN2_S 8U
|
||||
#define MCBSP_XCR2_XFRLEN2_M 0x7F00U // Transmit Frame length 2
|
||||
#define MCBSP_XCR2_XPHASE 0x8000U // Transmit Phase
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the XCR1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_XCR1_XWDLEN1_S 5U
|
||||
#define MCBSP_XCR1_XWDLEN1_M 0xE0U // Transmit word length 1
|
||||
#define MCBSP_XCR1_XFRLEN1_S 8U
|
||||
#define MCBSP_XCR1_XFRLEN1_M 0x7F00U // Transmit Frame length 1
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SRGR2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_SRGR2_FPER_S 0U
|
||||
#define MCBSP_SRGR2_FPER_M 0xFFFU // Frame-sync period
|
||||
#define MCBSP_SRGR2_FSGM 0x1000U // Frame sync generator mode
|
||||
#define MCBSP_SRGR2_CLKSM 0x2000U // Sample rate generator mode
|
||||
#define MCBSP_SRGR2_GSYNC 0x8000U // CLKG sync
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SRGR1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_SRGR1_CLKGDV_S 0U
|
||||
#define MCBSP_SRGR1_CLKGDV_M 0xFFU // CLKG divider
|
||||
#define MCBSP_SRGR1_FWID_S 8U
|
||||
#define MCBSP_SRGR1_FWID_M 0xFF00U // Frame width
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MCR2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_MCR2_XMCM_S 0U
|
||||
#define MCBSP_MCR2_XMCM_M 0x3U // Transmit data delay
|
||||
#define MCBSP_MCR2_XCBLK_S 2U
|
||||
#define MCBSP_MCR2_XCBLK_M 0x1CU // Transmit frame sync ignore
|
||||
#define MCBSP_MCR2_XPABLK_S 5U
|
||||
#define MCBSP_MCR2_XPABLK_M 0x60U // Transmit Companding Mode selects
|
||||
#define MCBSP_MCR2_XPBBLK_S 7U
|
||||
#define MCBSP_MCR2_XPBBLK_M 0x180U // Transmit word length 2
|
||||
#define MCBSP_MCR2_XMCME 0x200U // Transmit Frame length 2
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MCR1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_MCR1_RMCM 0x1U // Receive multichannel mode
|
||||
#define MCBSP_MCR1_RCBLK_S 2U
|
||||
#define MCBSP_MCR1_RCBLK_M 0x1CU // eceive current block
|
||||
#define MCBSP_MCR1_RPABLK_S 5U
|
||||
#define MCBSP_MCR1_RPABLK_M 0x60U // Receive partition A Block
|
||||
#define MCBSP_MCR1_RPBBLK_S 7U
|
||||
#define MCBSP_MCR1_RPBBLK_M 0x180U // Receive partition B Block
|
||||
#define MCBSP_MCR1_RMCME 0x200U // Receive multi-channel enhance mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PCR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_PCR_CLKRP 0x1U // Receive Clock polarity
|
||||
#define MCBSP_PCR_CLKXP 0x2U // Transmit clock polarity
|
||||
#define MCBSP_PCR_FSRP 0x4U // Receive Frame synchronization polarity
|
||||
#define MCBSP_PCR_FSXP 0x8U // Transmit Frame synchronization polarity
|
||||
#define MCBSP_PCR_SCLKME 0x80U // Sample clock mode selection
|
||||
#define MCBSP_PCR_CLKRM 0x100U // Receiver Clock Mode
|
||||
#define MCBSP_PCR_CLKXM 0x200U // Transmit Clock Mode.
|
||||
#define MCBSP_PCR_FSRM 0x400U // Receive Frame Synchronization Mode
|
||||
#define MCBSP_PCR_FSXM 0x800U // Transmit Frame Synchronization Mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MFFINT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MCBSP_MFFINT_XINT 0x1U // Enable for Receive Interrupt
|
||||
#define MCBSP_MFFINT_RINT 0x4U // Enable for transmit Interrupt
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,868 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_memcfg.h
|
||||
//
|
||||
// TITLE: Definitions for the MEMCFG registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_MEMCFG_H
|
||||
#define HW_MEMCFG_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the MEMCFG register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_O_DXLOCK 0x0U // Dedicated RAM Config Lock Register
|
||||
#define MEMCFG_O_DXCOMMIT 0x2U // Dedicated RAM Config Lock Commit Register
|
||||
#define MEMCFG_O_DXACCPROT0 0x8U // Dedicated RAM Config Register
|
||||
#define MEMCFG_O_DXTEST 0x10U // Dedicated RAM TEST Register
|
||||
#define MEMCFG_O_DXINIT 0x12U // Dedicated RAM Init Register
|
||||
#define MEMCFG_O_DXINITDONE 0x14U // Dedicated RAM InitDone Status Register
|
||||
#define MEMCFG_O_LSXLOCK 0x20U // Local Shared RAM Config Lock Register
|
||||
#define MEMCFG_O_LSXCOMMIT 0x22U // Local Shared RAM Config Lock Commit Register
|
||||
#define MEMCFG_O_LSXMSEL 0x24U // Local Shared RAM Master Sel Register
|
||||
#define MEMCFG_O_LSXCLAPGM 0x26U // Local Shared RAM Prog/Exe control Register
|
||||
#define MEMCFG_O_LSXACCPROT0 0x28U // Local Shared RAM Config Register 0
|
||||
#define MEMCFG_O_LSXACCPROT1 0x2AU // Local Shared RAM Config Register 1
|
||||
#define MEMCFG_O_LSXTEST 0x30U // Local Shared RAM TEST Register
|
||||
#define MEMCFG_O_LSXINIT 0x32U // Local Shared RAM Init Register
|
||||
#define MEMCFG_O_LSXINITDONE 0x34U // Local Shared RAM InitDone Status Register
|
||||
#define MEMCFG_O_GSXLOCK 0x40U // Global Shared RAM Config Lock Register
|
||||
#define MEMCFG_O_GSXCOMMIT 0x42U // Global Shared RAM Config Lock Commit Register
|
||||
#define MEMCFG_O_GSXMSEL 0x44U // Global Shared RAM Master Sel Register
|
||||
#define MEMCFG_O_GSXACCPROT0 0x48U // Global Shared RAM Config Register 0
|
||||
#define MEMCFG_O_GSXACCPROT1 0x4AU // Global Shared RAM Config Register 1
|
||||
#define MEMCFG_O_GSXACCPROT2 0x4CU // Global Shared RAM Config Register 2
|
||||
#define MEMCFG_O_GSXACCPROT3 0x4EU // Global Shared RAM Config Register 3
|
||||
#define MEMCFG_O_GSXTEST 0x50U // Global Shared RAM TEST Register
|
||||
#define MEMCFG_O_GSXINIT 0x52U // Global Shared RAM Init Register
|
||||
#define MEMCFG_O_GSXINITDONE 0x54U // Global Shared RAM InitDone Status Register
|
||||
#define MEMCFG_O_MSGXTEST 0x70U // Message RAM TEST Register
|
||||
#define MEMCFG_O_MSGXINIT 0x72U // Message RAM Init Register
|
||||
#define MEMCFG_O_MSGXINITDONE 0x74U // Message RAM InitDone Status Register
|
||||
|
||||
#define MEMCFG_O_EMIF1LOCK 0x0U // EMIF1 Config Lock Register
|
||||
#define MEMCFG_O_EMIF1COMMIT 0x2U // EMIF1 Config Lock Commit Register
|
||||
#define MEMCFG_O_EMIF1MSEL 0x4U // EMIF1 Master Sel Register
|
||||
#define MEMCFG_O_EMIF1ACCPROT0 0x8U // EMIF1 Config Register 0
|
||||
|
||||
#define MEMCFG_O_EMIF2LOCK 0x0U // EMIF2 Config Lock Register
|
||||
#define MEMCFG_O_EMIF2COMMIT 0x2U // EMIF2 Config Lock Commit Register
|
||||
#define MEMCFG_O_EMIF2ACCPROT0 0x8U // EMIF2 Config Register 0
|
||||
|
||||
#define MEMCFG_O_NMAVFLG 0x0U // Non-Master Access Violation Flag Register
|
||||
#define MEMCFG_O_NMAVSET 0x2U // Non-Master Access Violation Flag Set Register
|
||||
#define MEMCFG_O_NMAVCLR 0x4U // Non-Master Access Violation Flag Clear Register
|
||||
#define MEMCFG_O_NMAVINTEN 0x6U // Non-Master Access Violation Interrupt Enable Register
|
||||
#define MEMCFG_O_NMCPURDAVADDR 0x8U // Non-Master CPU Read Access Violation Address
|
||||
#define MEMCFG_O_NMCPUWRAVADDR 0xAU // Non-Master CPU Write Access Violation Address
|
||||
#define MEMCFG_O_NMCPUFAVADDR 0xCU // Non-Master CPU Fetch Access Violation Address
|
||||
#define MEMCFG_O_NMDMAWRAVADDR 0xEU // Non-Master DMA Write Access Violation Address
|
||||
#define MEMCFG_O_NMCLA1RDAVADDR 0x10U // Non-Master CLA1 Read Access Violation Address
|
||||
#define MEMCFG_O_NMCLA1WRAVADDR 0x12U // Non-Master CLA1 Write Access Violation Address
|
||||
#define MEMCFG_O_NMCLA1FAVADDR 0x14U // Non-Master CLA1 Fetch Access Violation Address
|
||||
#define MEMCFG_O_MAVFLG 0x20U // Master Access Violation Flag Register
|
||||
#define MEMCFG_O_MAVSET 0x22U // Master Access Violation Flag Set Register
|
||||
#define MEMCFG_O_MAVCLR 0x24U // Master Access Violation Flag Clear Register
|
||||
#define MEMCFG_O_MAVINTEN 0x26U // Master Access Violation Interrupt Enable Register
|
||||
#define MEMCFG_O_MCPUFAVADDR 0x28U // Master CPU Fetch Access Violation Address
|
||||
#define MEMCFG_O_MCPUWRAVADDR 0x2AU // Master CPU Write Access Violation Address
|
||||
#define MEMCFG_O_MDMAWRAVADDR 0x2CU // Master DMA Write Access Violation Address
|
||||
|
||||
#define MEMCFG_O_UCERRFLG 0x0U // Uncorrectable Error Flag Register
|
||||
#define MEMCFG_O_UCERRSET 0x2U // Uncorrectable Error Flag Set Register
|
||||
#define MEMCFG_O_UCERRCLR 0x4U // Uncorrectable Error Flag Clear Register
|
||||
#define MEMCFG_O_UCCPUREADDR 0x6U // Uncorrectable CPU Read Error Address
|
||||
#define MEMCFG_O_UCDMAREADDR 0x8U // Uncorrectable DMA Read Error Address
|
||||
#define MEMCFG_O_UCCLA1READDR 0xAU // Uncorrectable CLA1 Read Error Address
|
||||
#define MEMCFG_O_CERRFLG 0x20U // Correctable Error Flag Register
|
||||
#define MEMCFG_O_CERRSET 0x22U // Correctable Error Flag Set Register
|
||||
#define MEMCFG_O_CERRCLR 0x24U // Correctable Error Flag Clear Register
|
||||
#define MEMCFG_O_CCPUREADDR 0x26U // Correctable CPU Read Error Address
|
||||
#define MEMCFG_O_CERRCNT 0x2EU // Correctable Error Count Register
|
||||
#define MEMCFG_O_CERRTHRES 0x30U // Correctable Error Threshold Value Register
|
||||
#define MEMCFG_O_CEINTFLG 0x32U // Correctable Error Interrupt Flag Status Register
|
||||
#define MEMCFG_O_CEINTCLR 0x34U // Correctable Error Interrupt Flag Clear Register
|
||||
#define MEMCFG_O_CEINTSET 0x36U // Correctable Error Interrupt Flag Set Register
|
||||
#define MEMCFG_O_CEINTEN 0x38U // Correctable Error Interrupt Enable Register
|
||||
|
||||
#define MEMCFG_O_ROMWAITSTATE 0x0U // ROM Wait State Configuration Register
|
||||
|
||||
#define MEMCFG_O_ROMPREFETCH 0x0U // ROM Prefetch Configuration Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DxLOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_DXLOCK_LOCK_D0 0x4U // D0 RAM access protection and master select fields lock
|
||||
// bit
|
||||
#define MEMCFG_DXLOCK_LOCK_D1 0x8U // D1 RAM access protection and master select fields lock
|
||||
// bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DxCOMMIT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_DXCOMMIT_COMMIT_D0 0x4U // D0 RAM access protection and master select permanent
|
||||
// lock
|
||||
#define MEMCFG_DXCOMMIT_COMMIT_D1 0x8U // D1 RAM access protection and master select permanent
|
||||
// lock
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DxACCPROT0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_DXACCPROT0_FETCHPROT_D0 0x10000U // Fetch Protection For D0 RAM
|
||||
#define MEMCFG_DXACCPROT0_CPUWRPROT_D0 0x20000U // CPU WR Protection For D0 RAM
|
||||
#define MEMCFG_DXACCPROT0_FETCHPROT_D1 0x1000000U // Fetch Protection For D1 RAM
|
||||
#define MEMCFG_DXACCPROT0_CPUWRPROT_D1 0x2000000U // CPU WR Protection For D1 RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DxTEST register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_DXTEST_TEST_M0_S 0U
|
||||
#define MEMCFG_DXTEST_TEST_M0_M 0x3U // Selects the different modes for M0 RAM
|
||||
#define MEMCFG_DXTEST_TEST_M1_S 2U
|
||||
#define MEMCFG_DXTEST_TEST_M1_M 0xCU // Selects the different modes for M1 RAM
|
||||
#define MEMCFG_DXTEST_TEST_D0_S 4U
|
||||
#define MEMCFG_DXTEST_TEST_D0_M 0x30U // Selects the different modes for D0 RAM
|
||||
#define MEMCFG_DXTEST_TEST_D1_S 6U
|
||||
#define MEMCFG_DXTEST_TEST_D1_M 0xC0U // Selects the different modes for D1 RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DxINIT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_DXINIT_INIT_M0 0x1U // RAM Initialization control for M0 RAM.
|
||||
#define MEMCFG_DXINIT_INIT_M1 0x2U // RAM Initialization control for M1 RAM.
|
||||
#define MEMCFG_DXINIT_INIT_D0 0x4U // RAM Initialization control for D0 RAM.
|
||||
#define MEMCFG_DXINIT_INIT_D1 0x8U // RAM Initialization control for D1 RAM.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DxINITDONE register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_DXINITDONE_INITDONE_M0 0x1U // RAM Initialization status for M0 RAM.
|
||||
#define MEMCFG_DXINITDONE_INITDONE_M1 0x2U // RAM Initialization status for M1 RAM.
|
||||
#define MEMCFG_DXINITDONE_INITDONE_D0 0x4U // RAM Initialization status for D0 RAM.
|
||||
#define MEMCFG_DXINITDONE_INITDONE_D1 0x8U // RAM Initialization status for D1 RAM.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LSxLOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_LSXLOCK_LOCK_LS0 0x1U // LS0 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_LSXLOCK_LOCK_LS1 0x2U // LS1 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_LSXLOCK_LOCK_LS2 0x4U // LS2 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_LSXLOCK_LOCK_LS3 0x8U // LS3 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_LSXLOCK_LOCK_LS4 0x10U // LS4 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_LSXLOCK_LOCK_LS5 0x20U // LS5 RAM access protection and master select fields
|
||||
// lock bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LSxCOMMIT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_LSXCOMMIT_COMMIT_LS0 0x1U // LS0 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_LSXCOMMIT_COMMIT_LS1 0x2U // LS1 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_LSXCOMMIT_COMMIT_LS2 0x4U // LS2 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_LSXCOMMIT_COMMIT_LS3 0x8U // LS3 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_LSXCOMMIT_COMMIT_LS4 0x10U // LS4 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_LSXCOMMIT_COMMIT_LS5 0x20U // LS5 RAM access protection and master select
|
||||
// permanent lock
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LSxMSEL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS0_S 0U
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS0_M 0x3U // Master Select for LS0 RAM
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS1_S 2U
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS1_M 0xCU // Master Select for LS1 RAM
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS2_S 4U
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS2_M 0x30U // Master Select for LS2 RAM
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS3_S 6U
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS3_M 0xC0U // Master Select for LS3 RAM
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS4_S 8U
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS4_M 0x300U // Master Select for LS4 RAM
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS5_S 10U
|
||||
#define MEMCFG_LSXMSEL_MSEL_LS5_M 0xC00U // Master Select for LS5 RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LSxCLAPGM register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_LSXCLAPGM_CLAPGM_LS0 0x1U // Selects LS0 RAM as program vs data memory for CLA
|
||||
#define MEMCFG_LSXCLAPGM_CLAPGM_LS1 0x2U // Selects LS1 RAM as program vs data memory for CLA
|
||||
#define MEMCFG_LSXCLAPGM_CLAPGM_LS2 0x4U // Selects LS2 RAM as program vs data memory for CLA
|
||||
#define MEMCFG_LSXCLAPGM_CLAPGM_LS3 0x8U // Selects LS3 RAM as program vs data memory for CLA
|
||||
#define MEMCFG_LSXCLAPGM_CLAPGM_LS4 0x10U // Selects LS4 RAM as program vs data memory for CLA
|
||||
#define MEMCFG_LSXCLAPGM_CLAPGM_LS5 0x20U // Selects LS5 RAM as program vs data memory for CLA
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LSxACCPROT0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_LSXACCPROT0_FETCHPROT_LS0 0x1U // Fetch Protection For LS0 RAM
|
||||
#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS0 0x2U // CPU WR Protection For LS0 RAM
|
||||
#define MEMCFG_LSXACCPROT0_FETCHPROT_LS1 0x100U // Fetch Protection For LS1 RAM
|
||||
#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS1 0x200U // CPU WR Protection For LS1 RAM
|
||||
#define MEMCFG_LSXACCPROT0_FETCHPROT_LS2 0x10000U // Fetch Protection For LS2 RAM
|
||||
#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS2 0x20000U // CPU WR Protection For LS2 RAM
|
||||
#define MEMCFG_LSXACCPROT0_FETCHPROT_LS3 0x1000000U // Fetch Protection For LS3 RAM
|
||||
#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS3 0x2000000U // CPU WR Protection For LS3 RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LSxACCPROT1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_LSXACCPROT1_FETCHPROT_LS4 0x1U // Fetch Protection For LS4 RAM
|
||||
#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS4 0x2U // CPU WR Protection For LS4 RAM
|
||||
#define MEMCFG_LSXACCPROT1_FETCHPROT_LS5 0x100U // Fetch Protection For LS5 RAM
|
||||
#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS5 0x200U // CPU WR Protection For LS5 RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LSxTEST register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_LSXTEST_TEST_LS0_S 0U
|
||||
#define MEMCFG_LSXTEST_TEST_LS0_M 0x3U // Selects the different modes for LS0 RAM
|
||||
#define MEMCFG_LSXTEST_TEST_LS1_S 2U
|
||||
#define MEMCFG_LSXTEST_TEST_LS1_M 0xCU // Selects the different modes for LS1 RAM
|
||||
#define MEMCFG_LSXTEST_TEST_LS2_S 4U
|
||||
#define MEMCFG_LSXTEST_TEST_LS2_M 0x30U // Selects the different modes for LS2 RAM
|
||||
#define MEMCFG_LSXTEST_TEST_LS3_S 6U
|
||||
#define MEMCFG_LSXTEST_TEST_LS3_M 0xC0U // Selects the different modes for LS3 RAM
|
||||
#define MEMCFG_LSXTEST_TEST_LS4_S 8U
|
||||
#define MEMCFG_LSXTEST_TEST_LS4_M 0x300U // Selects the different modes for LS4 RAM
|
||||
#define MEMCFG_LSXTEST_TEST_LS5_S 10U
|
||||
#define MEMCFG_LSXTEST_TEST_LS5_M 0xC00U // Selects the different modes for LS5 RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LSxINIT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_LSXINIT_INIT_LS0 0x1U // RAM Initialization control for LS0 RAM.
|
||||
#define MEMCFG_LSXINIT_INIT_LS1 0x2U // RAM Initialization control for LS1 RAM.
|
||||
#define MEMCFG_LSXINIT_INIT_LS2 0x4U // RAM Initialization control for LS2 RAM.
|
||||
#define MEMCFG_LSXINIT_INIT_LS3 0x8U // RAM Initialization control for LS3 RAM.
|
||||
#define MEMCFG_LSXINIT_INIT_LS4 0x10U // RAM Initialization control for LS4 RAM.
|
||||
#define MEMCFG_LSXINIT_INIT_LS5 0x20U // RAM Initialization control for LS5 RAM.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LSxINITDONE register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_LSXINITDONE_INITDONE_LS0 0x1U // RAM Initialization status for LS0 RAM.
|
||||
#define MEMCFG_LSXINITDONE_INITDONE_LS1 0x2U // RAM Initialization status for LS1 RAM.
|
||||
#define MEMCFG_LSXINITDONE_INITDONE_LS2 0x4U // RAM Initialization status for LS2 RAM.
|
||||
#define MEMCFG_LSXINITDONE_INITDONE_LS3 0x8U // RAM Initialization status for LS3 RAM.
|
||||
#define MEMCFG_LSXINITDONE_INITDONE_LS4 0x10U // RAM Initialization status for LS4 RAM.
|
||||
#define MEMCFG_LSXINITDONE_INITDONE_LS5 0x20U // RAM Initialization status for LS5 RAM.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GSxLOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS0 0x1U // GS0 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS1 0x2U // GS1 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS2 0x4U // GS2 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS3 0x8U // GS3 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS4 0x10U // GS4 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS5 0x20U // GS5 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS6 0x40U // GS6 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS7 0x80U // GS7 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS8 0x100U // GS8 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS9 0x200U // GS9 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS10 0x400U // GS10 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS11 0x800U // GS11 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS12 0x1000U // GS12 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS13 0x2000U // GS13 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS14 0x4000U // GS14 RAM access protection and master select fields
|
||||
// lock bit
|
||||
#define MEMCFG_GSXLOCK_LOCK_GS15 0x8000U // GS15 RAM access protection and master select fields
|
||||
// lock bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GSxCOMMIT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS0 0x1U // GS0 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS1 0x2U // GS1 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS2 0x4U // GS2 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS3 0x8U // GS3 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS4 0x10U // GS4 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS5 0x20U // GS5 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS6 0x40U // GS6 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS7 0x80U // GS7 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS8 0x100U // GS8 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS9 0x200U // GS9 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS10 0x400U // GS10 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS11 0x800U // GS11 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS12 0x1000U // GS12 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS13 0x2000U // GS13 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS14 0x4000U // GS14 RAM access protection and master select
|
||||
// permanent lock
|
||||
#define MEMCFG_GSXCOMMIT_COMMIT_GS15 0x8000U // GS15 RAM access protection and master select
|
||||
// permanent lock
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GSxMSEL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS0 0x1U // Master Select for GS0 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS1 0x2U // Master Select for GS1 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS2 0x4U // Master Select for GS2 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS3 0x8U // Master Select for GS3 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS4 0x10U // Master Select for GS4 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS5 0x20U // Master Select for GS5 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS6 0x40U // Master Select for GS6 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS7 0x80U // Master Select for GS7 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS8 0x100U // Master Select for GS8 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS9 0x200U // Master Select for GS9 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS10 0x400U // Master Select for GS10 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS11 0x800U // Master Select for GS11 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS12 0x1000U // Master Select for GS12 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS13 0x2000U // Master Select for GS13 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS14 0x4000U // Master Select for GS14 RAM
|
||||
#define MEMCFG_GSXMSEL_MSEL_GS15 0x8000U // Master Select for GS15 RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GSxACCPROT0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_GSXACCPROT0_FETCHPROT_GS0 0x1U // Fetch Protection For GS0 RAM
|
||||
#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS0 0x2U // CPU WR Protection For GS0 RAM
|
||||
#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS0 0x4U // DMA WR Protection For GS0 RAM
|
||||
#define MEMCFG_GSXACCPROT0_FETCHPROT_GS1 0x100U // Fetch Protection For GS1 RAM
|
||||
#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS1 0x200U // CPU WR Protection For GS1 RAM
|
||||
#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS1 0x400U // DMA WR Protection For GS1 RAM
|
||||
#define MEMCFG_GSXACCPROT0_FETCHPROT_GS2 0x10000U // Fetch Protection For GS2 RAM
|
||||
#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS2 0x20000U // CPU WR Protection For GS2 RAM
|
||||
#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS2 0x40000U // DMA WR Protection For GS2 RAM
|
||||
#define MEMCFG_GSXACCPROT0_FETCHPROT_GS3 0x1000000U // Fetch Protection For GS3 RAM
|
||||
#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS3 0x2000000U // CPU WR Protection For GS3 RAM
|
||||
#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS3 0x4000000U // DMA WR Protection For GS3 RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GSxACCPROT1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_GSXACCPROT1_FETCHPROT_GS4 0x1U // Fetch Protection For GS4 RAM
|
||||
#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS4 0x2U // CPU WR Protection For GS4 RAM
|
||||
#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS4 0x4U // DMA WR Protection For GS4 RAM
|
||||
#define MEMCFG_GSXACCPROT1_FETCHPROT_GS5 0x100U // Fetch Protection For GS5 RAM
|
||||
#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS5 0x200U // CPU WR Protection For GS5 RAM
|
||||
#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS5 0x400U // DMA WR Protection For GS5RAM
|
||||
#define MEMCFG_GSXACCPROT1_FETCHPROT_GS6 0x10000U // Fetch Protection For GS6 RAM
|
||||
#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS6 0x20000U // CPU WR Protection For GS6 RAM
|
||||
#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS6 0x40000U // DMA WR Protection For GS6RAM
|
||||
#define MEMCFG_GSXACCPROT1_FETCHPROT_GS7 0x1000000U // Fetch Protection For GS7 RAM
|
||||
#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS7 0x2000000U // CPU WR Protection For GS7 RAM
|
||||
#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS7 0x4000000U // DMA WR Protection For GS7RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GSxACCPROT2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_GSXACCPROT2_FETCHPROT_GS8 0x1U // Fetch Protection For GS8 RAM
|
||||
#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS8 0x2U // CPU WR Protection For GS8 RAM
|
||||
#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS8 0x4U // DMA WR Protection For GS8 RAM
|
||||
#define MEMCFG_GSXACCPROT2_FETCHPROT_GS9 0x100U // Fetch Protection For GS9 RAM
|
||||
#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS9 0x200U // CPU WR Protection For GS9 RAM
|
||||
#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS9 0x400U // DMA WR Protection For GS9RAM
|
||||
#define MEMCFG_GSXACCPROT2_FETCHPROT_GS10 0x10000U // Fetch Protection For GS10 RAM
|
||||
#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS10 0x20000U // CPU WR Protection For GS10 RAM
|
||||
#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS10 0x40000U // DMA WR Protection For GS10RAM
|
||||
#define MEMCFG_GSXACCPROT2_FETCHPROT_GS11 0x1000000U // Fetch Protection For GS11 RAM
|
||||
#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS11 0x2000000U // CPU WR Protection For GS11 RAM
|
||||
#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS11 0x4000000U // DMA WR Protection For GS11RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GSxACCPROT3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_GSXACCPROT3_FETCHPROT_GS12 0x1U // Fetch Protection For GS12 RAM
|
||||
#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS12 0x2U // CPU WR Protection For GS12 RAM
|
||||
#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS12 0x4U // DMA WR Protection For GS12 RAM
|
||||
#define MEMCFG_GSXACCPROT3_FETCHPROT_GS13 0x100U // Fetch Protection For GS13 RAM
|
||||
#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS13 0x200U // CPU WR Protection For GS13 RAM
|
||||
#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS13 0x400U // DMA WR Protection For GS13RAM
|
||||
#define MEMCFG_GSXACCPROT3_FETCHPROT_GS14 0x10000U // Fetch Protection For GS14 RAM
|
||||
#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS14 0x20000U // CPU WR Protection For GS14 RAM
|
||||
#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS14 0x40000U // DMA WR Protection For GS14RAM
|
||||
#define MEMCFG_GSXACCPROT3_FETCHPROT_GS15 0x1000000U // Fetch Protection For GS15 RAM
|
||||
#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS15 0x2000000U // CPU WR Protection For GS15 RAM
|
||||
#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS15 0x4000000U // DMA WR Protection For GS15RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GSxTEST register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_GSXTEST_TEST_GS0_S 0U
|
||||
#define MEMCFG_GSXTEST_TEST_GS0_M 0x3U // Selects the different modes for GS0 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS1_S 2U
|
||||
#define MEMCFG_GSXTEST_TEST_GS1_M 0xCU // Selects the different modes for GS1 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS2_S 4U
|
||||
#define MEMCFG_GSXTEST_TEST_GS2_M 0x30U // Selects the different modes for GS2 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS3_S 6U
|
||||
#define MEMCFG_GSXTEST_TEST_GS3_M 0xC0U // Selects the different modes for GS3 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS4_S 8U
|
||||
#define MEMCFG_GSXTEST_TEST_GS4_M 0x300U // Selects the different modes for GS4 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS5_S 10U
|
||||
#define MEMCFG_GSXTEST_TEST_GS5_M 0xC00U // Selects the different modes for GS5 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS6_S 12U
|
||||
#define MEMCFG_GSXTEST_TEST_GS6_M 0x3000U // Selects the different modes for GS6 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS7_S 14U
|
||||
#define MEMCFG_GSXTEST_TEST_GS7_M 0xC000U // Selects the different modes for GS7 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS8_S 16U
|
||||
#define MEMCFG_GSXTEST_TEST_GS8_M 0x30000U // Selects the different modes for GS8 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS9_S 18U
|
||||
#define MEMCFG_GSXTEST_TEST_GS9_M 0xC0000U // Selects the different modes for GS9 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS10_S 20U
|
||||
#define MEMCFG_GSXTEST_TEST_GS10_M 0x300000U // Selects the different modes for GS10 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS11_S 22U
|
||||
#define MEMCFG_GSXTEST_TEST_GS11_M 0xC00000U // Selects the different modes for GS11 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS12_S 24U
|
||||
#define MEMCFG_GSXTEST_TEST_GS12_M 0x3000000U // Selects the different modes for GS12 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS13_S 26U
|
||||
#define MEMCFG_GSXTEST_TEST_GS13_M 0xC000000U // Selects the different modes for GS13 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS14_S 28U
|
||||
#define MEMCFG_GSXTEST_TEST_GS14_M 0x30000000U // Selects the different modes for GS14 RAM
|
||||
#define MEMCFG_GSXTEST_TEST_GS15_S 30U
|
||||
#define MEMCFG_GSXTEST_TEST_GS15_M 0xC0000000U // Selects the different modes for GS15 RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GSxINIT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_GSXINIT_INIT_GS0 0x1U // RAM Initialization control for GS0 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS1 0x2U // RAM Initialization control for GS1 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS2 0x4U // RAM Initialization control for GS2 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS3 0x8U // RAM Initialization control for GS3 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS4 0x10U // RAM Initialization control for GS4 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS5 0x20U // RAM Initialization control for GS5 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS6 0x40U // RAM Initialization control for GS6 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS7 0x80U // RAM Initialization control for GS7 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS8 0x100U // RAM Initialization control for GS8 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS9 0x200U // RAM Initialization control for GS9 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS10 0x400U // RAM Initialization control for GS10 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS11 0x800U // RAM Initialization control for GS11 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS12 0x1000U // RAM Initialization control for GS12 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS13 0x2000U // RAM Initialization control for GS13 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS14 0x4000U // RAM Initialization control for GS14 RAM.
|
||||
#define MEMCFG_GSXINIT_INIT_GS15 0x8000U // RAM Initialization control for GS15 RAM.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GSxINITDONE register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS0 0x1U // RAM Initialization status for GS0 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS1 0x2U // RAM Initialization status for GS1 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS2 0x4U // RAM Initialization status for GS2 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS3 0x8U // RAM Initialization status for GS3 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS4 0x10U // RAM Initialization status for GS4 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS5 0x20U // RAM Initialization status for GS5 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS6 0x40U // RAM Initialization status for GS6 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS7 0x80U // RAM Initialization status for GS7 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS8 0x100U // RAM Initialization status for GS8 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS9 0x200U // RAM Initialization status for GS9 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS10 0x400U // RAM Initialization status for GS10 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS11 0x800U // RAM Initialization status for GS11 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS12 0x1000U // RAM Initialization status for GS12 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS13 0x2000U // RAM Initialization status for GS13 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS14 0x4000U // RAM Initialization status for GS14 RAM.
|
||||
#define MEMCFG_GSXINITDONE_INITDONE_GS15 0x8000U // RAM Initialization status for GS15 RAM.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MSGxTEST register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_S 0U
|
||||
#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_M 0x3U // CPU to CPU Mode Select
|
||||
#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_S 2U
|
||||
#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_M 0xCU // CPU to CLA1 MSG RAM Mode Select
|
||||
#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_S 4U
|
||||
#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_M 0x30U // CLA1 to CPU MSG RAM Mode Select
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MSGxINIT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_MSGXINIT_INIT_CPUTOCPU 0x1U // Initialization control for CPU to CPU MSG RAM
|
||||
#define MEMCFG_MSGXINIT_INIT_CPUTOCLA1 0x2U // Initialization control for CPUTOCLA1 MSG RAM
|
||||
#define MEMCFG_MSGXINIT_INIT_CLA1TOCPU 0x4U // Initialization control for CLA1TOCPU MSG RAM
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MSGxINITDONE register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCPU 0x1U // Initialization status for CPU to CPU MSG
|
||||
// RAM
|
||||
#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCLA1 0x2U // Initialization status for CPU to CLA1
|
||||
// MSG RAM
|
||||
#define MEMCFG_MSGXINITDONE_INITDONE_CLA1TOCPU 0x4U // Initialization status for CLA1 to CPU
|
||||
// MSG RAM
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EMIF1LOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_EMIF1LOCK_LOCK_EMIF1 0x1U // EMIF1 access protection and master select fields
|
||||
// lock bit
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EMIF1COMMIT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_EMIF1COMMIT_COMMIT_EMIF1 0x1U // EMIF1 access protection and master select
|
||||
// permanent lock
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EMIF1MSEL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_S 0U
|
||||
#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_M 0x3U // Master Select for EMIF1.
|
||||
#define MEMCFG_EMIF1MSEL_KEY_S 4U
|
||||
#define MEMCFG_EMIF1MSEL_KEY_M 0xFFFFFFF0U // KEY to enable the write into MSEL_EMIF1
|
||||
// bits
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EMIF1ACCPROT0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 0x1U // Fetch Protection For EMIF1
|
||||
#define MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 0x2U // CPU WR Protection For EMIF1
|
||||
#define MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1 0x4U // DMA WR Protection For EMIF1
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EMIF2LOCK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_EMIF2LOCK_LOCK_EMIF2 0x1U // EMIF2 access protection and master select permanent
|
||||
// lock
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EMIF2COMMIT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_EMIF2COMMIT_COMMIT_EMIF2 0x1U // EMIF2 access protection and master select
|
||||
// permanent lock
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EMIF2ACCPROT0 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_EMIF2ACCPROT0_FETCHPROT_EMIF2 0x1U // Fetch Protection For EMIF2
|
||||
#define MEMCFG_EMIF2ACCPROT0_CPUWRPROT_EMIF2 0x2U // CPU WR Protection For EMIF2
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the NMAVFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_NMAVFLG_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag
|
||||
#define MEMCFG_NMAVFLG_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag
|
||||
#define MEMCFG_NMAVFLG_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag
|
||||
#define MEMCFG_NMAVFLG_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag
|
||||
#define MEMCFG_NMAVFLG_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag
|
||||
#define MEMCFG_NMAVFLG_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag
|
||||
#define MEMCFG_NMAVFLG_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the NMAVSET register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_NMAVSET_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Set
|
||||
#define MEMCFG_NMAVSET_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Set
|
||||
#define MEMCFG_NMAVSET_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Set
|
||||
#define MEMCFG_NMAVSET_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Set
|
||||
#define MEMCFG_NMAVSET_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Set
|
||||
#define MEMCFG_NMAVSET_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Set
|
||||
#define MEMCFG_NMAVSET_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Set
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the NMAVCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_NMAVCLR_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Clear
|
||||
#define MEMCFG_NMAVCLR_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Clear
|
||||
#define MEMCFG_NMAVCLR_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Clear
|
||||
#define MEMCFG_NMAVCLR_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Clear
|
||||
#define MEMCFG_NMAVCLR_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Clear
|
||||
#define MEMCFG_NMAVCLR_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Clear
|
||||
#define MEMCFG_NMAVCLR_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the NMAVINTEN register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_NMAVINTEN_CPUREAD 0x1U // Non Master CPU Read Access Violation Interrupt
|
||||
// Enable
|
||||
#define MEMCFG_NMAVINTEN_CPUWRITE 0x2U // Non Master CPU Write Access Violation Interrupt
|
||||
// Enable
|
||||
#define MEMCFG_NMAVINTEN_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Interrupt
|
||||
// Enable
|
||||
#define MEMCFG_NMAVINTEN_DMAWRITE 0x8U // Non Master DMA Write Access Violation Interrupt
|
||||
// Enable
|
||||
#define MEMCFG_NMAVINTEN_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Interrupt
|
||||
// Enable
|
||||
#define MEMCFG_NMAVINTEN_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Interrupt
|
||||
// Enable
|
||||
#define MEMCFG_NMAVINTEN_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Interrupt
|
||||
// Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MAVFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_MAVFLG_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag
|
||||
#define MEMCFG_MAVFLG_CPUWRITE 0x2U // Master CPU Write Access Violation Flag
|
||||
#define MEMCFG_MAVFLG_DMAWRITE 0x4U // Master DMA Write Access Violation Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MAVSET register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_MAVSET_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Set
|
||||
#define MEMCFG_MAVSET_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Set
|
||||
#define MEMCFG_MAVSET_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Set
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MAVCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_MAVCLR_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Clear
|
||||
#define MEMCFG_MAVCLR_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Clear
|
||||
#define MEMCFG_MAVCLR_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the MAVINTEN register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_MAVINTEN_CPUFETCH 0x1U // Master CPU Fetch Access Violation Interrupt Enable
|
||||
#define MEMCFG_MAVINTEN_CPUWRITE 0x2U // Master CPU Write Access Violation Interrupt Enable
|
||||
#define MEMCFG_MAVINTEN_DMAWRITE 0x4U // Master DMA Write Access Violation Interrupt Enable
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UCERRFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_UCERRFLG_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag
|
||||
#define MEMCFG_UCERRFLG_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag
|
||||
#define MEMCFG_UCERRFLG_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UCERRSET register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_UCERRSET_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Set
|
||||
#define MEMCFG_UCERRSET_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Set
|
||||
#define MEMCFG_UCERRSET_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Set
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UCERRCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_UCERRCLR_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Clear
|
||||
#define MEMCFG_UCERRCLR_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Clear
|
||||
#define MEMCFG_UCERRCLR_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CERRFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_CERRFLG_CPURDERR 0x1U // CPU Correctable Read Error Flag
|
||||
#define MEMCFG_CERRFLG_DMARDERR 0x2U // DMA Correctable Read Error Flag
|
||||
#define MEMCFG_CERRFLG_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CERRSET register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_CERRSET_CPURDERR 0x1U // CPU Correctable Read Error Flag Set
|
||||
#define MEMCFG_CERRSET_DMARDERR 0x2U // DMA Correctable Read Error Flag Set
|
||||
#define MEMCFG_CERRSET_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Set
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CERRCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_CERRCLR_CPURDERR 0x1U // CPU Correctable Read Error Flag Clear
|
||||
#define MEMCFG_CERRCLR_DMARDERR 0x2U // DMA Correctable Read Error Flag Clear
|
||||
#define MEMCFG_CERRCLR_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CEINTFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_CEINTFLG_CEINTFLAG 0x1U // Total corrected error count exceeded threshold flag.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CEINTCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_CEINTCLR_CEINTCLR 0x1U // CPU Corrected Error Threshold Exceeded Error Clear.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CEINTSET register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_CEINTSET_CEINTSET 0x1U // Total corrected error count exceeded flag set.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CEINTEN register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_CEINTEN_CEINTEN 0x1U // CPU/DMA Correctable Error Interrupt Enable.
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ROMWAITSTATE register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_ROMWAITSTATE_WSDISABLE 0x1U // C28x ROM Wait State Enable/Disable Control
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the ROMPREFETCH register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define MEMCFG_ROMPREFETCH_PFENABLE 0x1U // ROM Prefetch Enable/Disable Control
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,204 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_memmap.h
|
||||
//
|
||||
// TITLE: Macros defining the memory map of the C28x.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_MEMMAP_H
|
||||
#define HW_MEMMAP_H
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the base address of the memories and
|
||||
// peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define M0_RAM_BASE 0x00000000U
|
||||
#define M1_RAM_BASE 0x00000400U
|
||||
#define ADCARESULT_BASE 0x00000B00U
|
||||
#define ADCBRESULT_BASE 0x00000B20U
|
||||
#define ADCCRESULT_BASE 0x00000B40U
|
||||
#define ADCDRESULT_BASE 0x00000B60U
|
||||
#define CPUTIMER0_BASE 0x00000C00U
|
||||
#define CPUTIMER1_BASE 0x00000C08U
|
||||
#define CPUTIMER2_BASE 0x00000C10U
|
||||
#define PIECTRL_BASE 0x00000CE0U
|
||||
#define PIEVECTTABLE_BASE 0x00000D00U
|
||||
#define DMA_BASE 0x00001000U
|
||||
#define DMA_CH1_BASE 0x00001020U
|
||||
#define DMA_CH2_BASE 0x00001040U
|
||||
#define DMA_CH3_BASE 0x00001060U
|
||||
#define DMA_CH4_BASE 0x00001080U
|
||||
#define DMA_CH5_BASE 0x000010A0U
|
||||
#define DMA_CH6_BASE 0x000010C0U
|
||||
#define CLA1_BASE 0x00001400U
|
||||
#define CLATOCPU_RAM_BASE 0x00001480U
|
||||
#define CPUTOCLA_RAM_BASE 0x00001500U
|
||||
#define CLB1_BASE 0x00003000U
|
||||
#define CLB1_LOGICCFG_BASE 0x00003000U
|
||||
#define CLB1_LOGICCTL_BASE 0x00003100U
|
||||
#define CLB1_DATAEXCH_BASE 0x00003200U
|
||||
#define CLB2_BASE 0x00003400U
|
||||
#define CLB2_LOGICCFG_BASE 0x00003400U
|
||||
#define CLB2_LOGICCTL_BASE 0x00003500U
|
||||
#define CLB2_DATAEXCH_BASE 0x00003600U
|
||||
#define CLB3_BASE 0x00003800U
|
||||
#define CLB3_LOGICCFG_BASE 0x00003800U
|
||||
#define CLB3_LOGICCTL_BASE 0x00003900U
|
||||
#define CLB3_DATAEXCH_BASE 0x00003A00U
|
||||
#define CLB4_BASE 0x00003C00U
|
||||
#define CLB4_LOGICCFG_BASE 0x00003C00U
|
||||
#define CLB4_LOGICCTL_BASE 0x00003D00U
|
||||
#define CLB4_DATAEXCH_BASE 0x00003E00U
|
||||
#define EPWM1_BASE 0x00004000U
|
||||
#define EPWM2_BASE 0x00004100U
|
||||
#define EPWM3_BASE 0x00004200U
|
||||
#define EPWM4_BASE 0x00004300U
|
||||
#define EPWM5_BASE 0x00004400U
|
||||
#define EPWM6_BASE 0x00004500U
|
||||
#define EPWM7_BASE 0x00004600U
|
||||
#define EPWM8_BASE 0x00004700U
|
||||
#define EPWM9_BASE 0x00004800U
|
||||
#define EPWM10_BASE 0x00004900U
|
||||
#define EPWM11_BASE 0x00004A00U
|
||||
#define EPWM12_BASE 0x00004B00U
|
||||
#define ECAP1_BASE 0x00005000U
|
||||
#define ECAP2_BASE 0x00005020U
|
||||
#define ECAP3_BASE 0x00005040U
|
||||
#define ECAP4_BASE 0x00005060U
|
||||
#define ECAP5_BASE 0x00005080U
|
||||
#define ECAP6_BASE 0x000050A0U
|
||||
#define EQEP1_BASE 0x00005100U
|
||||
#define EQEP2_BASE 0x00005140U
|
||||
#define EQEP3_BASE 0x00005180U
|
||||
#define DACA_BASE 0x00005C00U
|
||||
#define DACB_BASE 0x00005C10U
|
||||
#define DACC_BASE 0x00005C20U
|
||||
#define CMPSS1_BASE 0x00005C80U
|
||||
#define CMPSS2_BASE 0x00005CA0U
|
||||
#define CMPSS3_BASE 0x00005CC0U
|
||||
#define CMPSS4_BASE 0x00005CE0U
|
||||
#define CMPSS5_BASE 0x00005D00U
|
||||
#define CMPSS6_BASE 0x00005D20U
|
||||
#define CMPSS7_BASE 0x00005D40U
|
||||
#define CMPSS8_BASE 0x00005D60U
|
||||
#define SDFM1_BASE 0x00005E00U
|
||||
#define SDFM2_BASE 0x00005E80U
|
||||
#define MCBSPA_BASE 0x00006000U
|
||||
#define MCBSPB_BASE 0x00006040U
|
||||
#define SPIA_BASE 0x00006100U
|
||||
#define SPIB_BASE 0x00006110U
|
||||
#define SPIC_BASE 0x00006120U
|
||||
#define UPP_BASE 0x00006200U
|
||||
#define UPP_TX_MSG_RAM_BASE 0x00006C00U
|
||||
#define UPP_RX_MSG_RAM_BASE 0x00006E00U
|
||||
#define WD_BASE 0x00007000U
|
||||
#define NMI_BASE 0x00007060U
|
||||
#define XINT_BASE 0x00007070U
|
||||
#define SCIA_BASE 0x00007200U
|
||||
#define SCIB_BASE 0x00007210U
|
||||
#define SCIC_BASE 0x00007220U
|
||||
#define SCID_BASE 0x00007230U
|
||||
#define I2CA_BASE 0x00007300U
|
||||
#define I2CB_BASE 0x00007340U
|
||||
#define ADCA_BASE 0x00007400U
|
||||
#define ADCB_BASE 0x00007480U
|
||||
#define ADCC_BASE 0x00007500U
|
||||
#define ADCD_BASE 0x00007580U
|
||||
#define INPUTXBAR_BASE 0x00007900U
|
||||
#define XBAR_BASE 0x00007920U
|
||||
#define SYNCSOC_BASE 0x00007940U
|
||||
#define DMACLASRCSEL_BASE 0x00007980U
|
||||
#define EPWMXBAR_BASE 0x00007A00U
|
||||
#define CLBXBAR_BASE 0x00007A40U
|
||||
#define OUTPUTXBAR_BASE 0x00007A80U
|
||||
#define GPIOCTRL_BASE 0x00007C00U
|
||||
#define GPIODATA_BASE 0x00007F00U
|
||||
#define LS0_RAM_BASE 0x00008000U
|
||||
#define LS1_RAM_BASE 0x00008800U
|
||||
#define LS2_RAM_BASE 0x00009000U
|
||||
#define LS3_RAM_BASE 0x00009800U
|
||||
#define LS4_RAM_BASE 0x0000A000U
|
||||
#define LS5_RAM_BASE 0x0000A800U
|
||||
#define D0_RAM_BASE 0x0000B000U
|
||||
#define D1_RAM_BASE 0x0000B800U
|
||||
#define GS0_RAM_BASE 0x0000C000U
|
||||
#define GS1_RAM_BASE 0x0000D000U
|
||||
#define GS2_RAM_BASE 0x0000E000U
|
||||
#define GS3_RAM_BASE 0x0000F000U
|
||||
#define GS4_RAM_BASE 0x00010000U
|
||||
#define GS5_RAM_BASE 0x00011000U
|
||||
#define GS6_RAM_BASE 0x00012000U
|
||||
#define GS7_RAM_BASE 0x00013000U
|
||||
#define GS8_RAM_BASE 0x00014000U
|
||||
#define GS9_RAM_BASE 0x00015000U
|
||||
#define GS10_RAM_BASE 0x00016000U
|
||||
#define GS11_RAM_BASE 0x00017000U
|
||||
#define GS12_RAM_BASE 0x00018000U
|
||||
#define GS13_RAM_BASE 0x00019000U
|
||||
#define GS14_RAM_BASE 0x0001A000U
|
||||
#define GS15_RAM_BASE 0x0001B000U
|
||||
#define CPU2_TO_CPU1_MSG_RAM_BASE 0x0003F800U
|
||||
#define CPU1_TO_CPU2_MSG_RAM_BASE 0x0003FC00U
|
||||
#define USBA_BASE 0x00040000U
|
||||
#define EMIF1_BASE 0x00047000U
|
||||
#define EMIF2_BASE 0x00047800U
|
||||
#define CANA_BASE 0x00048000U
|
||||
#define CANA_MSG_RAM_BASE 0x00049000U
|
||||
#define CANB_BASE 0x0004A000U
|
||||
#define CANB_MSG_RAM_BASE 0x0004B000U
|
||||
#define IPC_BASE 0x00050000U
|
||||
#define FLASHPUMPSEMAPHORE_BASE 0x00050024U
|
||||
#define DEVCFG_BASE 0x0005D000U
|
||||
#define ANALOGSUBSYS_BASE 0x0005D180U
|
||||
#define CLKCFG_BASE 0x0005D200U
|
||||
#define CPUSYS_BASE 0x0005D300U
|
||||
#define ROMPREFETCH_BASE 0x0005E608U
|
||||
#define DCSM_Z1_BASE 0x0005F000U
|
||||
#define DCSM_Z2_BASE 0x0005F040U
|
||||
#define DCSMCOMMON_BASE 0x0005F070U
|
||||
#define MEMCFG_BASE 0x0005F400U
|
||||
#define EMIF1CONFIG_BASE 0x0005F480U
|
||||
#define EMIF2CONFIG_BASE 0x0005F4A0U
|
||||
#define ACCESSPROTECTION_BASE 0x0005F4C0U
|
||||
#define MEMORYERROR_BASE 0x0005F500U
|
||||
#define ROMWAITSTATE_BASE 0x0005F540U
|
||||
#define FLASH0CTRL_BASE 0x0005F800U
|
||||
#define FLASH0ECC_BASE 0x0005FB00U
|
||||
#define DCSM_Z1OTP_BASE 0x00078000U
|
||||
#define DCSM_Z2OTP_BASE 0x00078200U
|
||||
#endif
|
|
@ -0,0 +1,132 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_nmi.h
|
||||
//
|
||||
// TITLE: Definitions for the NMI registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_NMI_H
|
||||
#define HW_NMI_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the NMI register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define NMI_O_CFG 0x0U // NMI Configuration Register
|
||||
#define NMI_O_FLG 0x1U // NMI Flag Register (XRSn Clear)
|
||||
#define NMI_O_FLGCLR 0x2U // NMI Flag Clear Register
|
||||
#define NMI_O_FLGFRC 0x3U // NMI Flag Force Register
|
||||
#define NMI_O_WDCNT 0x4U // NMI Watchdog Counter Register
|
||||
#define NMI_O_WDPRD 0x5U // NMI Watchdog Period Register
|
||||
#define NMI_O_SHDFLG 0x6U // NMI Shadow Flag Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the NMICFG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define NMI_CFG_NMIE 0x1U // Global NMI Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the NMIFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define NMI_FLG_NMIINT 0x1U // NMI Interrupt Flag
|
||||
#define NMI_FLG_CLOCKFAIL 0x2U // Clock Fail Interrupt Flag
|
||||
#define NMI_FLG_RAMUNCERR 0x4U // RAM Uncorrectable Error NMI Flag
|
||||
#define NMI_FLG_FLUNCERR 0x8U // Flash Uncorrectable Error NMI Flag
|
||||
#define NMI_FLG_CPU1HWBISTERR 0x10U // HW BIST Error NMI Flag
|
||||
#define NMI_FLG_CPU2HWBISTERR 0x20U // HW BIST Error NMI Flag
|
||||
#define NMI_FLG_PIEVECTERR 0x40U // PIE Vector Fetch Error Flag
|
||||
#define NMI_FLG_CLBNMI 0x100U // Configurable Logic Block NMI Flag
|
||||
#define NMI_FLG_CPU2WDRSN 0x200U // CPU2 WDRSn Reset Indication Flag
|
||||
#define NMI_FLG_CPU2NMIWDRSN 0x400U // CPU2 NMIWDRSn Reset Indication Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the NMIFLGCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define NMI_FLGCLR_NMIINT 0x1U // NMIINT Flag Clear
|
||||
#define NMI_FLGCLR_CLOCKFAIL 0x2U // CLOCKFAIL Flag Clear
|
||||
#define NMI_FLGCLR_RAMUNCERR 0x4U // RAMUNCERR Flag Clear
|
||||
#define NMI_FLGCLR_FLUNCERR 0x8U // FLUNCERR Flag Clear
|
||||
#define NMI_FLGCLR_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Clear
|
||||
#define NMI_FLGCLR_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Clear
|
||||
#define NMI_FLGCLR_PIEVECTERR 0x40U // PIEVECTERR Flag Clear
|
||||
#define NMI_FLGCLR_CLBNMI 0x100U // CLBNMI Flag Clear
|
||||
#define NMI_FLGCLR_CPU2WDRSN 0x200U // CPU2WDRSn Flag Clear
|
||||
#define NMI_FLGCLR_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Clear
|
||||
#define NMI_FLGCLR_OVF 0x800U // OVF Flag Clear
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the NMIFLGFRC register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define NMI_FLGFRC_CLOCKFAIL 0x2U // CLOCKFAIL Flag Force
|
||||
#define NMI_FLGFRC_RAMUNCERR 0x4U // RAMUNCERR Flag Force
|
||||
#define NMI_FLGFRC_FLUNCERR 0x8U // FLUNCERR Flag Force
|
||||
#define NMI_FLGFRC_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Force
|
||||
#define NMI_FLGFRC_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Force
|
||||
#define NMI_FLGFRC_PIEVECTERR 0x40U // PIEVECTERR Flag Force
|
||||
#define NMI_FLGFRC_CLBNMI 0x100U // CLBNMI Flag Force
|
||||
#define NMI_FLGFRC_CPU2WDRSN 0x200U // CPU2WDRSn Flag Force
|
||||
#define NMI_FLGFRC_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Force
|
||||
#define NMI_FLGFRC_OVF 0x800U // OVF Flag Force
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the NMISHDFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define NMI_SHDFLG_CLOCKFAIL 0x2U // Shadow CLOCKFAIL Flag
|
||||
#define NMI_SHDFLG_RAMUNCERR 0x4U // Shadow RAMUNCERR Flag
|
||||
#define NMI_SHDFLG_FLUNCERR 0x8U // Shadow FLUNCERR Flag
|
||||
#define NMI_SHDFLG_CPU1HWBISTERR 0x10U // Shadow CPU1HWBISTERR Flag
|
||||
#define NMI_SHDFLG_CPU2HWBISTERR 0x20U // Shadow CPU2HWBISTERR Flag
|
||||
#define NMI_SHDFLG_PIEVECTERR 0x40U // Shadow PIEVECTERR Flag
|
||||
#define NMI_SHDFLG_CLBNMI 0x100U // Shadow CLBNMI Flag
|
||||
#define NMI_SHDFLG_CPU2WDRSN 0x200U // Shadow CPU2WDRSn Flag
|
||||
#define NMI_SHDFLG_CPU2NMIWDRSN 0x400U // Shadow CPU2NMIWDRSn Flag
|
||||
#define NMI_SHDFLG_OVF 0x800U // Shadow OVF Flag
|
||||
|
||||
|
||||
|
||||
#endif
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,634 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_pie.h
|
||||
//
|
||||
// TITLE: Definitions for the PIE registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_PIE_H
|
||||
#define HW_PIE_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the PIE register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_O_CTRL 0x0U // ePIE Control Register
|
||||
#define PIE_O_ACK 0x1U // Interrupt Acknowledge Register
|
||||
#define PIE_O_IER1 0x2U // Interrupt Group 1 Enable Register
|
||||
#define PIE_O_IFR1 0x3U // Interrupt Group 1 Flag Register
|
||||
#define PIE_O_IER2 0x4U // Interrupt Group 2 Enable Register
|
||||
#define PIE_O_IFR2 0x5U // Interrupt Group 2 Flag Register
|
||||
#define PIE_O_IER3 0x6U // Interrupt Group 3 Enable Register
|
||||
#define PIE_O_IFR3 0x7U // Interrupt Group 3 Flag Register
|
||||
#define PIE_O_IER4 0x8U // Interrupt Group 4 Enable Register
|
||||
#define PIE_O_IFR4 0x9U // Interrupt Group 4 Flag Register
|
||||
#define PIE_O_IER5 0xAU // Interrupt Group 5 Enable Register
|
||||
#define PIE_O_IFR5 0xBU // Interrupt Group 5 Flag Register
|
||||
#define PIE_O_IER6 0xCU // Interrupt Group 6 Enable Register
|
||||
#define PIE_O_IFR6 0xDU // Interrupt Group 6 Flag Register
|
||||
#define PIE_O_IER7 0xEU // Interrupt Group 7 Enable Register
|
||||
#define PIE_O_IFR7 0xFU // Interrupt Group 7 Flag Register
|
||||
#define PIE_O_IER8 0x10U // Interrupt Group 8 Enable Register
|
||||
#define PIE_O_IFR8 0x11U // Interrupt Group 8 Flag Register
|
||||
#define PIE_O_IER9 0x12U // Interrupt Group 9 Enable Register
|
||||
#define PIE_O_IFR9 0x13U // Interrupt Group 9 Flag Register
|
||||
#define PIE_O_IER10 0x14U // Interrupt Group 10 Enable Register
|
||||
#define PIE_O_IFR10 0x15U // Interrupt Group 10 Flag Register
|
||||
#define PIE_O_IER11 0x16U // Interrupt Group 11 Enable Register
|
||||
#define PIE_O_IFR11 0x17U // Interrupt Group 11 Flag Register
|
||||
#define PIE_O_IER12 0x18U // Interrupt Group 12 Enable Register
|
||||
#define PIE_O_IFR12 0x19U // Interrupt Group 12 Flag Register
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIECTRL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_CTRL_ENPIE 0x1U // PIE Enable
|
||||
#define PIE_CTRL_PIEVECT_S 1U
|
||||
#define PIE_CTRL_PIEVECT_M 0xFFFEU // PIE Vector Address
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEACK register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_ACK_ACK1 0x1U // Acknowledge PIE Interrupt Group 1
|
||||
#define PIE_ACK_ACK2 0x2U // Acknowledge PIE Interrupt Group 2
|
||||
#define PIE_ACK_ACK3 0x4U // Acknowledge PIE Interrupt Group 3
|
||||
#define PIE_ACK_ACK4 0x8U // Acknowledge PIE Interrupt Group 4
|
||||
#define PIE_ACK_ACK5 0x10U // Acknowledge PIE Interrupt Group 5
|
||||
#define PIE_ACK_ACK6 0x20U // Acknowledge PIE Interrupt Group 6
|
||||
#define PIE_ACK_ACK7 0x40U // Acknowledge PIE Interrupt Group 7
|
||||
#define PIE_ACK_ACK8 0x80U // Acknowledge PIE Interrupt Group 8
|
||||
#define PIE_ACK_ACK9 0x100U // Acknowledge PIE Interrupt Group 9
|
||||
#define PIE_ACK_ACK10 0x200U // Acknowledge PIE Interrupt Group 10
|
||||
#define PIE_ACK_ACK11 0x400U // Acknowledge PIE Interrupt Group 11
|
||||
#define PIE_ACK_ACK12 0x800U // Acknowledge PIE Interrupt Group 12
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER1_INTX1 0x1U // Enable for Interrupt 1.1
|
||||
#define PIE_IER1_INTX2 0x2U // Enable for Interrupt 1.2
|
||||
#define PIE_IER1_INTX3 0x4U // Enable for Interrupt 1.3
|
||||
#define PIE_IER1_INTX4 0x8U // Enable for Interrupt 1.4
|
||||
#define PIE_IER1_INTX5 0x10U // Enable for Interrupt 1.5
|
||||
#define PIE_IER1_INTX6 0x20U // Enable for Interrupt 1.6
|
||||
#define PIE_IER1_INTX7 0x40U // Enable for Interrupt 1.7
|
||||
#define PIE_IER1_INTX8 0x80U // Enable for Interrupt 1.8
|
||||
#define PIE_IER1_INTX9 0x100U // Enable for Interrupt 1.9
|
||||
#define PIE_IER1_INTX10 0x200U // Enable for Interrupt 1.10
|
||||
#define PIE_IER1_INTX11 0x400U // Enable for Interrupt 1.11
|
||||
#define PIE_IER1_INTX12 0x800U // Enable for Interrupt 1.12
|
||||
#define PIE_IER1_INTX13 0x1000U // Enable for Interrupt 1.13
|
||||
#define PIE_IER1_INTX14 0x2000U // Enable for Interrupt 1.14
|
||||
#define PIE_IER1_INTX15 0x4000U // Enable for Interrupt 1.15
|
||||
#define PIE_IER1_INTX16 0x8000U // Enable for Interrupt 1.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR1_INTX1 0x1U // Flag for Interrupt 1.1
|
||||
#define PIE_IFR1_INTX2 0x2U // Flag for Interrupt 1.2
|
||||
#define PIE_IFR1_INTX3 0x4U // Flag for Interrupt 1.3
|
||||
#define PIE_IFR1_INTX4 0x8U // Flag for Interrupt 1.4
|
||||
#define PIE_IFR1_INTX5 0x10U // Flag for Interrupt 1.5
|
||||
#define PIE_IFR1_INTX6 0x20U // Flag for Interrupt 1.6
|
||||
#define PIE_IFR1_INTX7 0x40U // Flag for Interrupt 1.7
|
||||
#define PIE_IFR1_INTX8 0x80U // Flag for Interrupt 1.8
|
||||
#define PIE_IFR1_INTX9 0x100U // Flag for Interrupt 1.9
|
||||
#define PIE_IFR1_INTX10 0x200U // Flag for Interrupt 1.10
|
||||
#define PIE_IFR1_INTX11 0x400U // Flag for Interrupt 1.11
|
||||
#define PIE_IFR1_INTX12 0x800U // Flag for Interrupt 1.12
|
||||
#define PIE_IFR1_INTX13 0x1000U // Flag for Interrupt 1.13
|
||||
#define PIE_IFR1_INTX14 0x2000U // Flag for Interrupt 1.14
|
||||
#define PIE_IFR1_INTX15 0x4000U // Flag for Interrupt 1.15
|
||||
#define PIE_IFR1_INTX16 0x8000U // Flag for Interrupt 1.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER2_INTX1 0x1U // Enable for Interrupt 2.1
|
||||
#define PIE_IER2_INTX2 0x2U // Enable for Interrupt 2.2
|
||||
#define PIE_IER2_INTX3 0x4U // Enable for Interrupt 2.3
|
||||
#define PIE_IER2_INTX4 0x8U // Enable for Interrupt 2.4
|
||||
#define PIE_IER2_INTX5 0x10U // Enable for Interrupt 2.5
|
||||
#define PIE_IER2_INTX6 0x20U // Enable for Interrupt 2.6
|
||||
#define PIE_IER2_INTX7 0x40U // Enable for Interrupt 2.7
|
||||
#define PIE_IER2_INTX8 0x80U // Enable for Interrupt 2.8
|
||||
#define PIE_IER2_INTX9 0x100U // Enable for Interrupt 2.9
|
||||
#define PIE_IER2_INTX10 0x200U // Enable for Interrupt 2.10
|
||||
#define PIE_IER2_INTX11 0x400U // Enable for Interrupt 2.11
|
||||
#define PIE_IER2_INTX12 0x800U // Enable for Interrupt 2.12
|
||||
#define PIE_IER2_INTX13 0x1000U // Enable for Interrupt 2.13
|
||||
#define PIE_IER2_INTX14 0x2000U // Enable for Interrupt 2.14
|
||||
#define PIE_IER2_INTX15 0x4000U // Enable for Interrupt 2.15
|
||||
#define PIE_IER2_INTX16 0x8000U // Enable for Interrupt 2.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR2_INTX1 0x1U // Flag for Interrupt 2.1
|
||||
#define PIE_IFR2_INTX2 0x2U // Flag for Interrupt 2.2
|
||||
#define PIE_IFR2_INTX3 0x4U // Flag for Interrupt 2.3
|
||||
#define PIE_IFR2_INTX4 0x8U // Flag for Interrupt 2.4
|
||||
#define PIE_IFR2_INTX5 0x10U // Flag for Interrupt 2.5
|
||||
#define PIE_IFR2_INTX6 0x20U // Flag for Interrupt 2.6
|
||||
#define PIE_IFR2_INTX7 0x40U // Flag for Interrupt 2.7
|
||||
#define PIE_IFR2_INTX8 0x80U // Flag for Interrupt 2.8
|
||||
#define PIE_IFR2_INTX9 0x100U // Flag for Interrupt 2.9
|
||||
#define PIE_IFR2_INTX10 0x200U // Flag for Interrupt 2.10
|
||||
#define PIE_IFR2_INTX11 0x400U // Flag for Interrupt 2.11
|
||||
#define PIE_IFR2_INTX12 0x800U // Flag for Interrupt 2.12
|
||||
#define PIE_IFR2_INTX13 0x1000U // Flag for Interrupt 2.13
|
||||
#define PIE_IFR2_INTX14 0x2000U // Flag for Interrupt 2.14
|
||||
#define PIE_IFR2_INTX15 0x4000U // Flag for Interrupt 2.15
|
||||
#define PIE_IFR2_INTX16 0x8000U // Flag for Interrupt 2.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER3_INTX1 0x1U // Enable for Interrupt 3.1
|
||||
#define PIE_IER3_INTX2 0x2U // Enable for Interrupt 3.2
|
||||
#define PIE_IER3_INTX3 0x4U // Enable for Interrupt 3.3
|
||||
#define PIE_IER3_INTX4 0x8U // Enable for Interrupt 3.4
|
||||
#define PIE_IER3_INTX5 0x10U // Enable for Interrupt 3.5
|
||||
#define PIE_IER3_INTX6 0x20U // Enable for Interrupt 3.6
|
||||
#define PIE_IER3_INTX7 0x40U // Enable for Interrupt 3.7
|
||||
#define PIE_IER3_INTX8 0x80U // Enable for Interrupt 3.8
|
||||
#define PIE_IER3_INTX9 0x100U // Enable for Interrupt 3.9
|
||||
#define PIE_IER3_INTX10 0x200U // Enable for Interrupt 3.10
|
||||
#define PIE_IER3_INTX11 0x400U // Enable for Interrupt 3.11
|
||||
#define PIE_IER3_INTX12 0x800U // Enable for Interrupt 3.12
|
||||
#define PIE_IER3_INTX13 0x1000U // Enable for Interrupt 3.13
|
||||
#define PIE_IER3_INTX14 0x2000U // Enable for Interrupt 3.14
|
||||
#define PIE_IER3_INTX15 0x4000U // Enable for Interrupt 3.15
|
||||
#define PIE_IER3_INTX16 0x8000U // Enable for Interrupt 3.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR3_INTX1 0x1U // Flag for Interrupt 3.1
|
||||
#define PIE_IFR3_INTX2 0x2U // Flag for Interrupt 3.2
|
||||
#define PIE_IFR3_INTX3 0x4U // Flag for Interrupt 3.3
|
||||
#define PIE_IFR3_INTX4 0x8U // Flag for Interrupt 3.4
|
||||
#define PIE_IFR3_INTX5 0x10U // Flag for Interrupt 3.5
|
||||
#define PIE_IFR3_INTX6 0x20U // Flag for Interrupt 3.6
|
||||
#define PIE_IFR3_INTX7 0x40U // Flag for Interrupt 3.7
|
||||
#define PIE_IFR3_INTX8 0x80U // Flag for Interrupt 3.8
|
||||
#define PIE_IFR3_INTX9 0x100U // Flag for Interrupt 3.9
|
||||
#define PIE_IFR3_INTX10 0x200U // Flag for Interrupt 3.10
|
||||
#define PIE_IFR3_INTX11 0x400U // Flag for Interrupt 3.11
|
||||
#define PIE_IFR3_INTX12 0x800U // Flag for Interrupt 3.12
|
||||
#define PIE_IFR3_INTX13 0x1000U // Flag for Interrupt 3.13
|
||||
#define PIE_IFR3_INTX14 0x2000U // Flag for Interrupt 3.14
|
||||
#define PIE_IFR3_INTX15 0x4000U // Flag for Interrupt 3.15
|
||||
#define PIE_IFR3_INTX16 0x8000U // Flag for Interrupt 3.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER4_INTX1 0x1U // Enable for Interrupt 4.1
|
||||
#define PIE_IER4_INTX2 0x2U // Enable for Interrupt 4.2
|
||||
#define PIE_IER4_INTX3 0x4U // Enable for Interrupt 4.3
|
||||
#define PIE_IER4_INTX4 0x8U // Enable for Interrupt 4.4
|
||||
#define PIE_IER4_INTX5 0x10U // Enable for Interrupt 4.5
|
||||
#define PIE_IER4_INTX6 0x20U // Enable for Interrupt 4.6
|
||||
#define PIE_IER4_INTX7 0x40U // Enable for Interrupt 4.7
|
||||
#define PIE_IER4_INTX8 0x80U // Enable for Interrupt 4.8
|
||||
#define PIE_IER4_INTX9 0x100U // Enable for Interrupt 4.9
|
||||
#define PIE_IER4_INTX10 0x200U // Enable for Interrupt 4.10
|
||||
#define PIE_IER4_INTX11 0x400U // Enable for Interrupt 4.11
|
||||
#define PIE_IER4_INTX12 0x800U // Enable for Interrupt 4.12
|
||||
#define PIE_IER4_INTX13 0x1000U // Enable for Interrupt 4.13
|
||||
#define PIE_IER4_INTX14 0x2000U // Enable for Interrupt 4.14
|
||||
#define PIE_IER4_INTX15 0x4000U // Enable for Interrupt 4.15
|
||||
#define PIE_IER4_INTX16 0x8000U // Enable for Interrupt 4.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR4_INTX1 0x1U // Flag for Interrupt 4.1
|
||||
#define PIE_IFR4_INTX2 0x2U // Flag for Interrupt 4.2
|
||||
#define PIE_IFR4_INTX3 0x4U // Flag for Interrupt 4.3
|
||||
#define PIE_IFR4_INTX4 0x8U // Flag for Interrupt 4.4
|
||||
#define PIE_IFR4_INTX5 0x10U // Flag for Interrupt 4.5
|
||||
#define PIE_IFR4_INTX6 0x20U // Flag for Interrupt 4.6
|
||||
#define PIE_IFR4_INTX7 0x40U // Flag for Interrupt 4.7
|
||||
#define PIE_IFR4_INTX8 0x80U // Flag for Interrupt 4.8
|
||||
#define PIE_IFR4_INTX9 0x100U // Flag for Interrupt 4.9
|
||||
#define PIE_IFR4_INTX10 0x200U // Flag for Interrupt 4.10
|
||||
#define PIE_IFR4_INTX11 0x400U // Flag for Interrupt 4.11
|
||||
#define PIE_IFR4_INTX12 0x800U // Flag for Interrupt 4.12
|
||||
#define PIE_IFR4_INTX13 0x1000U // Flag for Interrupt 4.13
|
||||
#define PIE_IFR4_INTX14 0x2000U // Flag for Interrupt 4.14
|
||||
#define PIE_IFR4_INTX15 0x4000U // Flag for Interrupt 4.15
|
||||
#define PIE_IFR4_INTX16 0x8000U // Flag for Interrupt 4.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER5 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER5_INTX1 0x1U // Enable for Interrupt 5.1
|
||||
#define PIE_IER5_INTX2 0x2U // Enable for Interrupt 5.2
|
||||
#define PIE_IER5_INTX3 0x4U // Enable for Interrupt 5.3
|
||||
#define PIE_IER5_INTX4 0x8U // Enable for Interrupt 5.4
|
||||
#define PIE_IER5_INTX5 0x10U // Enable for Interrupt 5.5
|
||||
#define PIE_IER5_INTX6 0x20U // Enable for Interrupt 5.6
|
||||
#define PIE_IER5_INTX7 0x40U // Enable for Interrupt 5.7
|
||||
#define PIE_IER5_INTX8 0x80U // Enable for Interrupt 5.8
|
||||
#define PIE_IER5_INTX9 0x100U // Enable for Interrupt 5.9
|
||||
#define PIE_IER5_INTX10 0x200U // Enable for Interrupt 5.10
|
||||
#define PIE_IER5_INTX11 0x400U // Enable for Interrupt 5.11
|
||||
#define PIE_IER5_INTX12 0x800U // Enable for Interrupt 5.12
|
||||
#define PIE_IER5_INTX13 0x1000U // Enable for Interrupt 5.13
|
||||
#define PIE_IER5_INTX14 0x2000U // Enable for Interrupt 5.14
|
||||
#define PIE_IER5_INTX15 0x4000U // Enable for Interrupt 5.15
|
||||
#define PIE_IER5_INTX16 0x8000U // Enable for Interrupt 5.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR5 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR5_INTX1 0x1U // Flag for Interrupt 5.1
|
||||
#define PIE_IFR5_INTX2 0x2U // Flag for Interrupt 5.2
|
||||
#define PIE_IFR5_INTX3 0x4U // Flag for Interrupt 5.3
|
||||
#define PIE_IFR5_INTX4 0x8U // Flag for Interrupt 5.4
|
||||
#define PIE_IFR5_INTX5 0x10U // Flag for Interrupt 5.5
|
||||
#define PIE_IFR5_INTX6 0x20U // Flag for Interrupt 5.6
|
||||
#define PIE_IFR5_INTX7 0x40U // Flag for Interrupt 5.7
|
||||
#define PIE_IFR5_INTX8 0x80U // Flag for Interrupt 5.8
|
||||
#define PIE_IFR5_INTX9 0x100U // Flag for Interrupt 5.9
|
||||
#define PIE_IFR5_INTX10 0x200U // Flag for Interrupt 5.10
|
||||
#define PIE_IFR5_INTX11 0x400U // Flag for Interrupt 5.11
|
||||
#define PIE_IFR5_INTX12 0x800U // Flag for Interrupt 5.12
|
||||
#define PIE_IFR5_INTX13 0x1000U // Flag for Interrupt 5.13
|
||||
#define PIE_IFR5_INTX14 0x2000U // Flag for Interrupt 5.14
|
||||
#define PIE_IFR5_INTX15 0x4000U // Flag for Interrupt 5.15
|
||||
#define PIE_IFR5_INTX16 0x8000U // Flag for Interrupt 5.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER6 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER6_INTX1 0x1U // Enable for Interrupt 6.1
|
||||
#define PIE_IER6_INTX2 0x2U // Enable for Interrupt 6.2
|
||||
#define PIE_IER6_INTX3 0x4U // Enable for Interrupt 6.3
|
||||
#define PIE_IER6_INTX4 0x8U // Enable for Interrupt 6.4
|
||||
#define PIE_IER6_INTX5 0x10U // Enable for Interrupt 6.5
|
||||
#define PIE_IER6_INTX6 0x20U // Enable for Interrupt 6.6
|
||||
#define PIE_IER6_INTX7 0x40U // Enable for Interrupt 6.7
|
||||
#define PIE_IER6_INTX8 0x80U // Enable for Interrupt 6.8
|
||||
#define PIE_IER6_INTX9 0x100U // Enable for Interrupt 6.9
|
||||
#define PIE_IER6_INTX10 0x200U // Enable for Interrupt 6.10
|
||||
#define PIE_IER6_INTX11 0x400U // Enable for Interrupt 6.11
|
||||
#define PIE_IER6_INTX12 0x800U // Enable for Interrupt 6.12
|
||||
#define PIE_IER6_INTX13 0x1000U // Enable for Interrupt 6.13
|
||||
#define PIE_IER6_INTX14 0x2000U // Enable for Interrupt 6.14
|
||||
#define PIE_IER6_INTX15 0x4000U // Enable for Interrupt 6.15
|
||||
#define PIE_IER6_INTX16 0x8000U // Enable for Interrupt 6.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR6 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR6_INTX1 0x1U // Flag for Interrupt 6.1
|
||||
#define PIE_IFR6_INTX2 0x2U // Flag for Interrupt 6.2
|
||||
#define PIE_IFR6_INTX3 0x4U // Flag for Interrupt 6.3
|
||||
#define PIE_IFR6_INTX4 0x8U // Flag for Interrupt 6.4
|
||||
#define PIE_IFR6_INTX5 0x10U // Flag for Interrupt 6.5
|
||||
#define PIE_IFR6_INTX6 0x20U // Flag for Interrupt 6.6
|
||||
#define PIE_IFR6_INTX7 0x40U // Flag for Interrupt 6.7
|
||||
#define PIE_IFR6_INTX8 0x80U // Flag for Interrupt 6.8
|
||||
#define PIE_IFR6_INTX9 0x100U // Flag for Interrupt 6.9
|
||||
#define PIE_IFR6_INTX10 0x200U // Flag for Interrupt 6.10
|
||||
#define PIE_IFR6_INTX11 0x400U // Flag for Interrupt 6.11
|
||||
#define PIE_IFR6_INTX12 0x800U // Flag for Interrupt 6.12
|
||||
#define PIE_IFR6_INTX13 0x1000U // Flag for Interrupt 6.13
|
||||
#define PIE_IFR6_INTX14 0x2000U // Flag for Interrupt 6.14
|
||||
#define PIE_IFR6_INTX15 0x4000U // Flag for Interrupt 6.15
|
||||
#define PIE_IFR6_INTX16 0x8000U // Flag for Interrupt 6.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER7 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER7_INTX1 0x1U // Enable for Interrupt 7.1
|
||||
#define PIE_IER7_INTX2 0x2U // Enable for Interrupt 7.2
|
||||
#define PIE_IER7_INTX3 0x4U // Enable for Interrupt 7.3
|
||||
#define PIE_IER7_INTX4 0x8U // Enable for Interrupt 7.4
|
||||
#define PIE_IER7_INTX5 0x10U // Enable for Interrupt 7.5
|
||||
#define PIE_IER7_INTX6 0x20U // Enable for Interrupt 7.6
|
||||
#define PIE_IER7_INTX7 0x40U // Enable for Interrupt 7.7
|
||||
#define PIE_IER7_INTX8 0x80U // Enable for Interrupt 7.8
|
||||
#define PIE_IER7_INTX9 0x100U // Enable for Interrupt 7.9
|
||||
#define PIE_IER7_INTX10 0x200U // Enable for Interrupt 7.10
|
||||
#define PIE_IER7_INTX11 0x400U // Enable for Interrupt 7.11
|
||||
#define PIE_IER7_INTX12 0x800U // Enable for Interrupt 7.12
|
||||
#define PIE_IER7_INTX13 0x1000U // Enable for Interrupt 7.13
|
||||
#define PIE_IER7_INTX14 0x2000U // Enable for Interrupt 7.14
|
||||
#define PIE_IER7_INTX15 0x4000U // Enable for Interrupt 7.15
|
||||
#define PIE_IER7_INTX16 0x8000U // Enable for Interrupt 7.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR7 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR7_INTX1 0x1U // Flag for Interrupt 7.1
|
||||
#define PIE_IFR7_INTX2 0x2U // Flag for Interrupt 7.2
|
||||
#define PIE_IFR7_INTX3 0x4U // Flag for Interrupt 7.3
|
||||
#define PIE_IFR7_INTX4 0x8U // Flag for Interrupt 7.4
|
||||
#define PIE_IFR7_INTX5 0x10U // Flag for Interrupt 7.5
|
||||
#define PIE_IFR7_INTX6 0x20U // Flag for Interrupt 7.6
|
||||
#define PIE_IFR7_INTX7 0x40U // Flag for Interrupt 7.7
|
||||
#define PIE_IFR7_INTX8 0x80U // Flag for Interrupt 7.8
|
||||
#define PIE_IFR7_INTX9 0x100U // Flag for Interrupt 7.9
|
||||
#define PIE_IFR7_INTX10 0x200U // Flag for Interrupt 7.10
|
||||
#define PIE_IFR7_INTX11 0x400U // Flag for Interrupt 7.11
|
||||
#define PIE_IFR7_INTX12 0x800U // Flag for Interrupt 7.12
|
||||
#define PIE_IFR7_INTX13 0x1000U // Flag for Interrupt 7.13
|
||||
#define PIE_IFR7_INTX14 0x2000U // Flag for Interrupt 7.14
|
||||
#define PIE_IFR7_INTX15 0x4000U // Flag for Interrupt 7.15
|
||||
#define PIE_IFR7_INTX16 0x8000U // Flag for Interrupt 7.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER8 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER8_INTX1 0x1U // Enable for Interrupt 8.1
|
||||
#define PIE_IER8_INTX2 0x2U // Enable for Interrupt 8.2
|
||||
#define PIE_IER8_INTX3 0x4U // Enable for Interrupt 8.3
|
||||
#define PIE_IER8_INTX4 0x8U // Enable for Interrupt 8.4
|
||||
#define PIE_IER8_INTX5 0x10U // Enable for Interrupt 8.5
|
||||
#define PIE_IER8_INTX6 0x20U // Enable for Interrupt 8.6
|
||||
#define PIE_IER8_INTX7 0x40U // Enable for Interrupt 8.7
|
||||
#define PIE_IER8_INTX8 0x80U // Enable for Interrupt 8.8
|
||||
#define PIE_IER8_INTX9 0x100U // Enable for Interrupt 8.9
|
||||
#define PIE_IER8_INTX10 0x200U // Enable for Interrupt 8.10
|
||||
#define PIE_IER8_INTX11 0x400U // Enable for Interrupt 8.11
|
||||
#define PIE_IER8_INTX12 0x800U // Enable for Interrupt 8.12
|
||||
#define PIE_IER8_INTX13 0x1000U // Enable for Interrupt 8.13
|
||||
#define PIE_IER8_INTX14 0x2000U // Enable for Interrupt 8.14
|
||||
#define PIE_IER8_INTX15 0x4000U // Enable for Interrupt 8.15
|
||||
#define PIE_IER8_INTX16 0x8000U // Enable for Interrupt 8.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR8 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR8_INTX1 0x1U // Flag for Interrupt 8.1
|
||||
#define PIE_IFR8_INTX2 0x2U // Flag for Interrupt 8.2
|
||||
#define PIE_IFR8_INTX3 0x4U // Flag for Interrupt 8.3
|
||||
#define PIE_IFR8_INTX4 0x8U // Flag for Interrupt 8.4
|
||||
#define PIE_IFR8_INTX5 0x10U // Flag for Interrupt 8.5
|
||||
#define PIE_IFR8_INTX6 0x20U // Flag for Interrupt 8.6
|
||||
#define PIE_IFR8_INTX7 0x40U // Flag for Interrupt 8.7
|
||||
#define PIE_IFR8_INTX8 0x80U // Flag for Interrupt 8.8
|
||||
#define PIE_IFR8_INTX9 0x100U // Flag for Interrupt 8.9
|
||||
#define PIE_IFR8_INTX10 0x200U // Flag for Interrupt 8.10
|
||||
#define PIE_IFR8_INTX11 0x400U // Flag for Interrupt 8.11
|
||||
#define PIE_IFR8_INTX12 0x800U // Flag for Interrupt 8.12
|
||||
#define PIE_IFR8_INTX13 0x1000U // Flag for Interrupt 8.13
|
||||
#define PIE_IFR8_INTX14 0x2000U // Flag for Interrupt 8.14
|
||||
#define PIE_IFR8_INTX15 0x4000U // Flag for Interrupt 8.15
|
||||
#define PIE_IFR8_INTX16 0x8000U // Flag for Interrupt 8.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER9 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER9_INTX1 0x1U // Enable for Interrupt 9.1
|
||||
#define PIE_IER9_INTX2 0x2U // Enable for Interrupt 9.2
|
||||
#define PIE_IER9_INTX3 0x4U // Enable for Interrupt 9.3
|
||||
#define PIE_IER9_INTX4 0x8U // Enable for Interrupt 9.4
|
||||
#define PIE_IER9_INTX5 0x10U // Enable for Interrupt 9.5
|
||||
#define PIE_IER9_INTX6 0x20U // Enable for Interrupt 9.6
|
||||
#define PIE_IER9_INTX7 0x40U // Enable for Interrupt 9.7
|
||||
#define PIE_IER9_INTX8 0x80U // Enable for Interrupt 9.8
|
||||
#define PIE_IER9_INTX9 0x100U // Enable for Interrupt 9.9
|
||||
#define PIE_IER9_INTX10 0x200U // Enable for Interrupt 9.10
|
||||
#define PIE_IER9_INTX11 0x400U // Enable for Interrupt 9.11
|
||||
#define PIE_IER9_INTX12 0x800U // Enable for Interrupt 9.12
|
||||
#define PIE_IER9_INTX13 0x1000U // Enable for Interrupt 9.13
|
||||
#define PIE_IER9_INTX14 0x2000U // Enable for Interrupt 9.14
|
||||
#define PIE_IER9_INTX15 0x4000U // Enable for Interrupt 9.15
|
||||
#define PIE_IER9_INTX16 0x8000U // Enable for Interrupt 9.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR9 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR9_INTX1 0x1U // Flag for Interrupt 9.1
|
||||
#define PIE_IFR9_INTX2 0x2U // Flag for Interrupt 9.2
|
||||
#define PIE_IFR9_INTX3 0x4U // Flag for Interrupt 9.3
|
||||
#define PIE_IFR9_INTX4 0x8U // Flag for Interrupt 9.4
|
||||
#define PIE_IFR9_INTX5 0x10U // Flag for Interrupt 9.5
|
||||
#define PIE_IFR9_INTX6 0x20U // Flag for Interrupt 9.6
|
||||
#define PIE_IFR9_INTX7 0x40U // Flag for Interrupt 9.7
|
||||
#define PIE_IFR9_INTX8 0x80U // Flag for Interrupt 9.8
|
||||
#define PIE_IFR9_INTX9 0x100U // Flag for Interrupt 9.9
|
||||
#define PIE_IFR9_INTX10 0x200U // Flag for Interrupt 9.10
|
||||
#define PIE_IFR9_INTX11 0x400U // Flag for Interrupt 9.11
|
||||
#define PIE_IFR9_INTX12 0x800U // Flag for Interrupt 9.12
|
||||
#define PIE_IFR9_INTX13 0x1000U // Flag for Interrupt 9.13
|
||||
#define PIE_IFR9_INTX14 0x2000U // Flag for Interrupt 9.14
|
||||
#define PIE_IFR9_INTX15 0x4000U // Flag for Interrupt 9.15
|
||||
#define PIE_IFR9_INTX16 0x8000U // Flag for Interrupt 9.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER10 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER10_INTX1 0x1U // Enable for Interrupt 10.1
|
||||
#define PIE_IER10_INTX2 0x2U // Enable for Interrupt 10.2
|
||||
#define PIE_IER10_INTX3 0x4U // Enable for Interrupt 10.3
|
||||
#define PIE_IER10_INTX4 0x8U // Enable for Interrupt 10.4
|
||||
#define PIE_IER10_INTX5 0x10U // Enable for Interrupt 10.5
|
||||
#define PIE_IER10_INTX6 0x20U // Enable for Interrupt 10.6
|
||||
#define PIE_IER10_INTX7 0x40U // Enable for Interrupt 10.7
|
||||
#define PIE_IER10_INTX8 0x80U // Enable for Interrupt 10.8
|
||||
#define PIE_IER10_INTX9 0x100U // Enable for Interrupt 10.9
|
||||
#define PIE_IER10_INTX10 0x200U // Enable for Interrupt 10.10
|
||||
#define PIE_IER10_INTX11 0x400U // Enable for Interrupt 10.11
|
||||
#define PIE_IER10_INTX12 0x800U // Enable for Interrupt 10.12
|
||||
#define PIE_IER10_INTX13 0x1000U // Enable for Interrupt 10.13
|
||||
#define PIE_IER10_INTX14 0x2000U // Enable for Interrupt 10.14
|
||||
#define PIE_IER10_INTX15 0x4000U // Enable for Interrupt 10.15
|
||||
#define PIE_IER10_INTX16 0x8000U // Enable for Interrupt 10.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR10 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR10_INTX1 0x1U // Flag for Interrupt 10.1
|
||||
#define PIE_IFR10_INTX2 0x2U // Flag for Interrupt 10.2
|
||||
#define PIE_IFR10_INTX3 0x4U // Flag for Interrupt 10.3
|
||||
#define PIE_IFR10_INTX4 0x8U // Flag for Interrupt 10.4
|
||||
#define PIE_IFR10_INTX5 0x10U // Flag for Interrupt 10.5
|
||||
#define PIE_IFR10_INTX6 0x20U // Flag for Interrupt 10.6
|
||||
#define PIE_IFR10_INTX7 0x40U // Flag for Interrupt 10.7
|
||||
#define PIE_IFR10_INTX8 0x80U // Flag for Interrupt 10.8
|
||||
#define PIE_IFR10_INTX9 0x100U // Flag for Interrupt 10.9
|
||||
#define PIE_IFR10_INTX10 0x200U // Flag for Interrupt 10.10
|
||||
#define PIE_IFR10_INTX11 0x400U // Flag for Interrupt 10.11
|
||||
#define PIE_IFR10_INTX12 0x800U // Flag for Interrupt 10.12
|
||||
#define PIE_IFR10_INTX13 0x1000U // Flag for Interrupt 10.13
|
||||
#define PIE_IFR10_INTX14 0x2000U // Flag for Interrupt 10.14
|
||||
#define PIE_IFR10_INTX15 0x4000U // Flag for Interrupt 10.15
|
||||
#define PIE_IFR10_INTX16 0x8000U // Flag for Interrupt 10.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER11 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER11_INTX1 0x1U // Enable for Interrupt 11.1
|
||||
#define PIE_IER11_INTX2 0x2U // Enable for Interrupt 11.2
|
||||
#define PIE_IER11_INTX3 0x4U // Enable for Interrupt 11.3
|
||||
#define PIE_IER11_INTX4 0x8U // Enable for Interrupt 11.4
|
||||
#define PIE_IER11_INTX5 0x10U // Enable for Interrupt 11.5
|
||||
#define PIE_IER11_INTX6 0x20U // Enable for Interrupt 11.6
|
||||
#define PIE_IER11_INTX7 0x40U // Enable for Interrupt 11.7
|
||||
#define PIE_IER11_INTX8 0x80U // Enable for Interrupt 11.8
|
||||
#define PIE_IER11_INTX9 0x100U // Enable for Interrupt 11.9
|
||||
#define PIE_IER11_INTX10 0x200U // Enable for Interrupt 11.10
|
||||
#define PIE_IER11_INTX11 0x400U // Enable for Interrupt 11.11
|
||||
#define PIE_IER11_INTX12 0x800U // Enable for Interrupt 11.12
|
||||
#define PIE_IER11_INTX13 0x1000U // Enable for Interrupt 11.13
|
||||
#define PIE_IER11_INTX14 0x2000U // Enable for Interrupt 11.14
|
||||
#define PIE_IER11_INTX15 0x4000U // Enable for Interrupt 11.15
|
||||
#define PIE_IER11_INTX16 0x8000U // Enable for Interrupt 11.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR11 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR11_INTX1 0x1U // Flag for Interrupt 11.1
|
||||
#define PIE_IFR11_INTX2 0x2U // Flag for Interrupt 11.2
|
||||
#define PIE_IFR11_INTX3 0x4U // Flag for Interrupt 11.3
|
||||
#define PIE_IFR11_INTX4 0x8U // Flag for Interrupt 11.4
|
||||
#define PIE_IFR11_INTX5 0x10U // Flag for Interrupt 11.5
|
||||
#define PIE_IFR11_INTX6 0x20U // Flag for Interrupt 11.6
|
||||
#define PIE_IFR11_INTX7 0x40U // Flag for Interrupt 11.7
|
||||
#define PIE_IFR11_INTX8 0x80U // Flag for Interrupt 11.8
|
||||
#define PIE_IFR11_INTX9 0x100U // Flag for Interrupt 11.9
|
||||
#define PIE_IFR11_INTX10 0x200U // Flag for Interrupt 11.10
|
||||
#define PIE_IFR11_INTX11 0x400U // Flag for Interrupt 11.11
|
||||
#define PIE_IFR11_INTX12 0x800U // Flag for Interrupt 11.12
|
||||
#define PIE_IFR11_INTX13 0x1000U // Flag for Interrupt 11.13
|
||||
#define PIE_IFR11_INTX14 0x2000U // Flag for Interrupt 11.14
|
||||
#define PIE_IFR11_INTX15 0x4000U // Flag for Interrupt 11.15
|
||||
#define PIE_IFR11_INTX16 0x8000U // Flag for Interrupt 11.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIER12 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IER12_INTX1 0x1U // Enable for Interrupt 12.1
|
||||
#define PIE_IER12_INTX2 0x2U // Enable for Interrupt 12.2
|
||||
#define PIE_IER12_INTX3 0x4U // Enable for Interrupt 12.3
|
||||
#define PIE_IER12_INTX4 0x8U // Enable for Interrupt 12.4
|
||||
#define PIE_IER12_INTX5 0x10U // Enable for Interrupt 12.5
|
||||
#define PIE_IER12_INTX6 0x20U // Enable for Interrupt 12.6
|
||||
#define PIE_IER12_INTX7 0x40U // Enable for Interrupt 12.7
|
||||
#define PIE_IER12_INTX8 0x80U // Enable for Interrupt 12.8
|
||||
#define PIE_IER12_INTX9 0x100U // Enable for Interrupt 12.9
|
||||
#define PIE_IER12_INTX10 0x200U // Enable for Interrupt 12.10
|
||||
#define PIE_IER12_INTX11 0x400U // Enable for Interrupt 12.11
|
||||
#define PIE_IER12_INTX12 0x800U // Enable for Interrupt 12.12
|
||||
#define PIE_IER12_INTX13 0x1000U // Enable for Interrupt 12.13
|
||||
#define PIE_IER12_INTX14 0x2000U // Enable for Interrupt 12.14
|
||||
#define PIE_IER12_INTX15 0x4000U // Enable for Interrupt 12.15
|
||||
#define PIE_IER12_INTX16 0x8000U // Enable for Interrupt 12.16
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PIEIFR12 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define PIE_IFR12_INTX1 0x1U // Flag for Interrupt 12.1
|
||||
#define PIE_IFR12_INTX2 0x2U // Flag for Interrupt 12.2
|
||||
#define PIE_IFR12_INTX3 0x4U // Flag for Interrupt 12.3
|
||||
#define PIE_IFR12_INTX4 0x8U // Flag for Interrupt 12.4
|
||||
#define PIE_IFR12_INTX5 0x10U // Flag for Interrupt 12.5
|
||||
#define PIE_IFR12_INTX6 0x20U // Flag for Interrupt 12.6
|
||||
#define PIE_IFR12_INTX7 0x40U // Flag for Interrupt 12.7
|
||||
#define PIE_IFR12_INTX8 0x80U // Flag for Interrupt 12.8
|
||||
#define PIE_IFR12_INTX9 0x100U // Flag for Interrupt 12.9
|
||||
#define PIE_IFR12_INTX10 0x200U // Flag for Interrupt 12.10
|
||||
#define PIE_IFR12_INTX11 0x400U // Flag for Interrupt 12.11
|
||||
#define PIE_IFR12_INTX12 0x800U // Flag for Interrupt 12.12
|
||||
#define PIE_IFR12_INTX13 0x1000U // Flag for Interrupt 12.13
|
||||
#define PIE_IFR12_INTX14 0x2000U // Flag for Interrupt 12.14
|
||||
#define PIE_IFR12_INTX15 0x4000U // Flag for Interrupt 12.15
|
||||
#define PIE_IFR12_INTX16 0x8000U // Flag for Interrupt 12.16
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,207 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_sci.h
|
||||
//
|
||||
// TITLE: Definitions for the SCI registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_SCI_H
|
||||
#define HW_SCI_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the SCI register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_O_CCR 0x0U // Communications control register
|
||||
#define SCI_O_CTL1 0x1U // Control register 1
|
||||
#define SCI_O_HBAUD 0x2U // Baud rate (high) register
|
||||
#define SCI_O_LBAUD 0x3U // Baud rate (low) register
|
||||
#define SCI_O_CTL2 0x4U // Control register 2
|
||||
#define SCI_O_RXST 0x5U // Receive status register
|
||||
#define SCI_O_RXEMU 0x6U // Receive emulation buffer register
|
||||
#define SCI_O_RXBUF 0x7U // Receive data buffer
|
||||
#define SCI_O_TXBUF 0x9U // Transmit data buffer
|
||||
#define SCI_O_FFTX 0xAU // FIFO transmit register
|
||||
#define SCI_O_FFRX 0xBU // FIFO receive register
|
||||
#define SCI_O_FFCT 0xCU // FIFO control register
|
||||
#define SCI_O_PRI 0xFU // SCI priority control
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCICCR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_CCR_SCICHAR_S 0U
|
||||
#define SCI_CCR_SCICHAR_M 0x7U // Character length control
|
||||
#define SCI_CCR_ADDRIDLE_MODE 0x8U // ADDR/IDLE Mode control
|
||||
#define SCI_CCR_LOOPBKENA 0x10U // Loop Back enable
|
||||
#define SCI_CCR_PARITYENA 0x20U // Parity enable
|
||||
#define SCI_CCR_PARITY 0x40U // Even or Odd Parity
|
||||
#define SCI_CCR_STOPBITS 0x80U // Number of Stop Bits
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCICTL1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_CTL1_RXENA 0x1U // SCI receiver enable
|
||||
#define SCI_CTL1_TXENA 0x2U // SCI transmitter enable
|
||||
#define SCI_CTL1_SLEEP 0x4U // SCI sleep
|
||||
#define SCI_CTL1_TXWAKE 0x8U // Transmitter wakeup method
|
||||
#define SCI_CTL1_SWRESET 0x20U // Software reset
|
||||
#define SCI_CTL1_RXERRINTENA 0x40U // Receive error interrupt enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCIHBAUD register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_HBAUD_BAUD_S 0U
|
||||
#define SCI_HBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCIHBAUD
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCILBAUD register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_LBAUD_BAUD_S 0U
|
||||
#define SCI_LBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCILBAUD
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCICTL2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_CTL2_TXINTENA 0x1U // Transmit __interrupt enable
|
||||
#define SCI_CTL2_RXBKINTENA 0x2U // Receiver-buffer break enable
|
||||
#define SCI_CTL2_TXEMPTY 0x40U // Transmitter empty flag
|
||||
#define SCI_CTL2_TXRDY 0x80U // Transmitter ready flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCIRXST register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_RXST_RXWAKE 0x2U // Receiver wakeup detect flag
|
||||
#define SCI_RXST_PE 0x4U // Parity error flag
|
||||
#define SCI_RXST_OE 0x8U // Overrun error flag
|
||||
#define SCI_RXST_FE 0x10U // Framing error flag
|
||||
#define SCI_RXST_BRKDT 0x20U // Break-detect flag
|
||||
#define SCI_RXST_RXRDY 0x40U // Receiver ready flag
|
||||
#define SCI_RXST_RXERROR 0x80U // Receiver error flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCIRXEMU register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_RXEMU_ERXDT_S 0U
|
||||
#define SCI_RXEMU_ERXDT_M 0xFFU // Receive emulation buffer data
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCIRXBUF register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_RXBUF_SAR_S 0U
|
||||
#define SCI_RXBUF_SAR_M 0xFFU // Receive Character bits
|
||||
#define SCI_RXBUF_SCIFFPE 0x4000U // Receiver error flag
|
||||
#define SCI_RXBUF_SCIFFFE 0x8000U // Receiver error flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCITXBUF register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_TXBUF_TXDT_S 0U
|
||||
#define SCI_TXBUF_TXDT_M 0xFFU // Transmit data buffer
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCIFFTX register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_FFTX_TXFFIL_S 0U
|
||||
#define SCI_FFTX_TXFFIL_M 0x1FU // Interrupt level
|
||||
#define SCI_FFTX_TXFFIENA 0x20U // Interrupt enable
|
||||
#define SCI_FFTX_TXFFINTCLR 0x40U // Clear INT flag
|
||||
#define SCI_FFTX_TXFFINT 0x80U // INT flag
|
||||
#define SCI_FFTX_TXFFST_S 8U
|
||||
#define SCI_FFTX_TXFFST_M 0x1F00U // FIFO status
|
||||
#define SCI_FFTX_TXFIFORESET 0x2000U // FIFO reset
|
||||
#define SCI_FFTX_SCIFFENA 0x4000U // Enhancement enable
|
||||
#define SCI_FFTX_SCIRST 0x8000U // SCI reset rx/tx channels
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCIFFRX register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_FFRX_RXFFIL_S 0U
|
||||
#define SCI_FFRX_RXFFIL_M 0x1FU // Interrupt level
|
||||
#define SCI_FFRX_RXFFIENA 0x20U // Interrupt enable
|
||||
#define SCI_FFRX_RXFFINTCLR 0x40U // Clear INT flag
|
||||
#define SCI_FFRX_RXFFINT 0x80U // INT flag
|
||||
#define SCI_FFRX_RXFFST_S 8U
|
||||
#define SCI_FFRX_RXFFST_M 0x1F00U // FIFO status
|
||||
#define SCI_FFRX_RXFIFORESET 0x2000U // FIFO reset
|
||||
#define SCI_FFRX_RXFFOVRCLR 0x4000U // Clear overflow
|
||||
#define SCI_FFRX_RXFFOVF 0x8000U // FIFO overflow
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCIFFCT register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_FFCT_FFTXDLY_S 0U
|
||||
#define SCI_FFCT_FFTXDLY_M 0xFFU // FIFO transmit delay
|
||||
#define SCI_FFCT_CDC 0x2000U // Auto baud mode enable
|
||||
#define SCI_FFCT_ABDCLR 0x4000U // Auto baud clear
|
||||
#define SCI_FFCT_ABD 0x8000U // Auto baud detect
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SCIPRI register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SCI_PRI_FREESOFT_S 3U
|
||||
#define SCI_PRI_FREESOFT_M 0x18U // Emulation modes
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,429 @@
|
|||
//###########################################################################
|
||||
//
|
||||
// FILE: hw_sdfm.h
|
||||
//
|
||||
// TITLE: Definitions for the SDFM registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef HW_SDFM_H
|
||||
#define HW_SDFM_H
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the SDFM register offsets
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_O_SDIFLG 0x0U // Interrupt Flag Register
|
||||
#define SDFM_O_SDIFLGCLR 0x2U // Interrupt Flag Clear Register
|
||||
#define SDFM_O_SDCTL 0x4U // SD Control Register
|
||||
#define SDFM_O_SDMFILEN 0x6U // SD Master Filter Enable
|
||||
#define SDFM_O_SDCTLPARM1 0x10U // Control Parameter Register for Ch1
|
||||
#define SDFM_O_SDDFPARM1 0x11U // Data Filter Parameter Register for Ch1
|
||||
#define SDFM_O_SDDPARM1 0x12U // Integer Parameter Register for Ch1
|
||||
#define SDFM_O_SDCMPH1 0x13U // High-level Threshold Register for Ch1
|
||||
#define SDFM_O_SDCMPL1 0x14U // Low-level Threshold Register for Ch1
|
||||
#define SDFM_O_SDCPARM1 0x15U // Comparator Parameter Register for Ch1
|
||||
#define SDFM_O_SDDATA1 0x16U // Filter Data Register (16 or 32bit) for Ch1
|
||||
#define SDFM_O_SDCTLPARM2 0x20U // Control Parameter Register for Ch2
|
||||
#define SDFM_O_SDDFPARM2 0x21U // Data Filter Parameter Register for Ch2
|
||||
#define SDFM_O_SDDPARM2 0x22U // Integer Parameter Register for Ch2
|
||||
#define SDFM_O_SDCMPH2 0x23U // High-level Threshold Register for Ch2
|
||||
#define SDFM_O_SDCMPL2 0x24U // Low-level Threshold Register for Ch2
|
||||
#define SDFM_O_SDCPARM2 0x25U // Comparator Parameter Register for Ch2
|
||||
#define SDFM_O_SDDATA2 0x26U // Filter Data Register (16 or 32bit) for Ch2
|
||||
#define SDFM_O_SDCTLPARM3 0x30U // Control Parameter Register for Ch3
|
||||
#define SDFM_O_SDDFPARM3 0x31U // Data Filter Parameter Register for Ch3
|
||||
#define SDFM_O_SDDPARM3 0x32U // Integer Parameter Register for Ch3
|
||||
#define SDFM_O_SDCMPH3 0x33U // High-level Threshold Register for Ch3
|
||||
#define SDFM_O_SDCMPL3 0x34U // Low-level Threshold Register for Ch3
|
||||
#define SDFM_O_SDCPARM3 0x35U // Comparator Parameter Register for Ch3
|
||||
#define SDFM_O_SDDATA3 0x36U // Filter Data Register (16 or 32bit) for Ch3
|
||||
#define SDFM_O_SDCTLPARM4 0x40U // Control Parameter Register for Ch4
|
||||
#define SDFM_O_SDDFPARM4 0x41U // Data Filter Parameter Register for Ch4
|
||||
#define SDFM_O_SDDPARM4 0x42U // Integer Parameter Register for Ch4
|
||||
#define SDFM_O_SDCMPH4 0x43U // High-level Threshold Register for Ch4
|
||||
#define SDFM_O_SDCMPL4 0x44U // Low-level Threshold Register for Ch4
|
||||
#define SDFM_O_SDCPARM4 0x45U // Comparator Parameter Register for Ch4
|
||||
#define SDFM_O_SDDATA4 0x46U // Filter Data Register (16 or 32bit) for Ch4
|
||||
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDIFLG register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDIFLG_IFH1 0x1U // High-level Interrupt flag Filter 1
|
||||
#define SDFM_SDIFLG_IFL1 0x2U // Low-Level Interrupt flag Filter 1
|
||||
#define SDFM_SDIFLG_IFH2 0x4U // High-level Interrupt flag Filter 2
|
||||
#define SDFM_SDIFLG_IFL2 0x8U // Low-Level Interrupt flag Filter 2
|
||||
#define SDFM_SDIFLG_IFH3 0x10U // High-level Interrupt flag Filter 3
|
||||
#define SDFM_SDIFLG_IFL3 0x20U // Low-Level Interrupt flag Filter 3
|
||||
#define SDFM_SDIFLG_IFH4 0x40U // High-level Interrupt flag Filter 4
|
||||
#define SDFM_SDIFLG_IFL4 0x80U // Low-Level Interrupt flag Filter 4
|
||||
#define SDFM_SDIFLG_MF1 0x100U // Modulator Failure for Filter 1
|
||||
#define SDFM_SDIFLG_MF2 0x200U // Modulator Failure for Filter 2
|
||||
#define SDFM_SDIFLG_MF3 0x400U // Modulator Failure for Filter 3
|
||||
#define SDFM_SDIFLG_MF4 0x800U // Modulator Failure for Filter 4
|
||||
#define SDFM_SDIFLG_AF1 0x1000U // Acknowledge flag for Filter 1
|
||||
#define SDFM_SDIFLG_AF2 0x2000U // Acknowledge flag for Filter 2
|
||||
#define SDFM_SDIFLG_AF3 0x4000U // Acknowledge flag for Filter 3
|
||||
#define SDFM_SDIFLG_AF4 0x8000U // Acknowledge flag for Filter 4
|
||||
#define SDFM_SDIFLG_MIF 0x80000000U // Master Interrupt Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDIFLGCLR register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDIFLGCLR_IFH1 0x1U // High-level Interrupt flag Filter 1
|
||||
#define SDFM_SDIFLGCLR_IFL1 0x2U // Low-Level Interrupt flag Filter 1
|
||||
#define SDFM_SDIFLGCLR_IFH2 0x4U // High-level Interrupt flag Filter 2
|
||||
#define SDFM_SDIFLGCLR_IFL2 0x8U // Low-Level Interrupt flag Filter 2
|
||||
#define SDFM_SDIFLGCLR_IFH3 0x10U // High-level Interrupt flag Filter 3
|
||||
#define SDFM_SDIFLGCLR_IFL3 0x20U // Low-Level Interrupt flag Filter 3
|
||||
#define SDFM_SDIFLGCLR_IFH4 0x40U // High-level Interrupt flag Filter 4
|
||||
#define SDFM_SDIFLGCLR_IFL4 0x80U // Low-Level Interrupt flag Filter 4
|
||||
#define SDFM_SDIFLGCLR_MF1 0x100U // Modulator Failure for Filter 1
|
||||
#define SDFM_SDIFLGCLR_MF2 0x200U // Modulator Failure for Filter 2
|
||||
#define SDFM_SDIFLGCLR_MF3 0x400U // Modulator Failure for Filter 3
|
||||
#define SDFM_SDIFLGCLR_MF4 0x800U // Modulator Failure for Filter 4
|
||||
#define SDFM_SDIFLGCLR_AF1 0x1000U // Acknowledge flag for Filter 1
|
||||
#define SDFM_SDIFLGCLR_AF2 0x2000U // Acknowledge flag for Filter 2
|
||||
#define SDFM_SDIFLGCLR_AF3 0x4000U // Acknowledge flag for Filter 3
|
||||
#define SDFM_SDIFLGCLR_AF4 0x8000U // Acknowledge flag for Filter 4
|
||||
#define SDFM_SDIFLGCLR_MIF 0x80000000U // Master Interrupt Flag
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCTL register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCTL_MIE 0x2000U // Master Interrupt enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDMFILEN register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDMFILEN_MFE 0x800U // Master Filter Enable.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCTLPARM1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCTLPARM1_MOD_S 0U
|
||||
#define SDFM_SDCTLPARM1_MOD_M 0x3U // Delta-Sigma Modulator mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDFPARM1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDFPARM1_DOSR_S 0U
|
||||
#define SDFM_SDDFPARM1_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1
|
||||
#define SDFM_SDDFPARM1_FEN 0x100U // Filter Enable
|
||||
#define SDFM_SDDFPARM1_AE 0x200U // Ack Enable
|
||||
#define SDFM_SDDFPARM1_SST_S 10U
|
||||
#define SDFM_SDDFPARM1_SST_M 0xC00U // Data Filter Structure (DataFast/1/2/3)
|
||||
#define SDFM_SDDFPARM1_SDSYNCEN 0x1000U // Data FILTER Reset Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDPARM1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDPARM1_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement)
|
||||
#define SDFM_SDDPARM1_SH_S 11U
|
||||
#define SDFM_SDDPARM1_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode)
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCMPH1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCMPH1_HLT_S 0U
|
||||
#define SDFM_SDCMPH1_HLT_M 0x7FFFU // High-level threshold for the comparator filter output.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCMPL1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCMPL1_LLT_S 0U
|
||||
#define SDFM_SDCMPL1_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCPARM1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCPARM1_COSR_S 0U
|
||||
#define SDFM_SDCPARM1_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1
|
||||
#define SDFM_SDCPARM1_IEH 0x20U // High-level interrupt enable
|
||||
#define SDFM_SDCPARM1_IEL 0x40U // Low-level interrupt enable
|
||||
#define SDFM_SDCPARM1_CS1_CS0_S 7U
|
||||
#define SDFM_SDCPARM1_CS1_CS0_M 0x180U // Comparator filter structure
|
||||
// (Sincfast/Sinc1/Sinc2/Sinc3
|
||||
#define SDFM_SDCPARM1_MFIE 0x200U // Modulator Failure Interrupt enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDATA1 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDATA1_DATA16_S 0U
|
||||
#define SDFM_SDDATA1_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b
|
||||
// mode
|
||||
#define SDFM_SDDATA1_DATA32HI_S 16U
|
||||
#define SDFM_SDDATA1_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCTLPARM2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCTLPARM2_MOD_S 0U
|
||||
#define SDFM_SDCTLPARM2_MOD_M 0x3U // Delta-Sigma Modulator mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDFPARM2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDFPARM2_DOSR_S 0U
|
||||
#define SDFM_SDDFPARM2_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1
|
||||
#define SDFM_SDDFPARM2_FEN 0x100U // Filter Enable
|
||||
#define SDFM_SDDFPARM2_AE 0x200U // Ack Enable
|
||||
#define SDFM_SDDFPARM2_SST_S 10U
|
||||
#define SDFM_SDDFPARM2_SST_M 0xC00U // Data Filter Structure (SincFast/1/2/3)
|
||||
#define SDFM_SDDFPARM2_SDSYNCEN 0x1000U // Data FILTER Reset Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDPARM2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDPARM2_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement)
|
||||
#define SDFM_SDDPARM2_SH_S 11U
|
||||
#define SDFM_SDDPARM2_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode)
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCMPH2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCMPH2_HLT_S 0U
|
||||
#define SDFM_SDCMPH2_HLT_M 0x7FFFU // High-level threshold for the comparator filter output.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCMPL2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCMPL2_LLT_S 0U
|
||||
#define SDFM_SDCMPL2_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCPARM2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCPARM2_COSR_S 0U
|
||||
#define SDFM_SDCPARM2_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1
|
||||
#define SDFM_SDCPARM2_IEH 0x20U // High-level interrupt enable
|
||||
#define SDFM_SDCPARM2_IEL 0x40U // Low-level interrupt enable
|
||||
#define SDFM_SDCPARM2_CS1_CS0_S 7U
|
||||
#define SDFM_SDCPARM2_CS1_CS0_M 0x180U // Comparator filter structure
|
||||
// (Sincfast/Sinc1/Sinc2/Sinc3
|
||||
#define SDFM_SDCPARM2_MFIE 0x200U // Modulator Failure Interrupt enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDATA2 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDATA2_DATA16_S 0U
|
||||
#define SDFM_SDDATA2_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b
|
||||
// mode
|
||||
#define SDFM_SDDATA2_DATA32HI_S 16U
|
||||
#define SDFM_SDDATA2_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCTLPARM3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCTLPARM3_MOD_S 0U
|
||||
#define SDFM_SDCTLPARM3_MOD_M 0x3U // Delta-Sigma Modulator mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDFPARM3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDFPARM3_DOSR_S 0U
|
||||
#define SDFM_SDDFPARM3_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1
|
||||
#define SDFM_SDDFPARM3_FEN 0x100U // Filter Enable
|
||||
#define SDFM_SDDFPARM3_AE 0x200U // Ack Enable
|
||||
#define SDFM_SDDFPARM3_SST_S 10U
|
||||
#define SDFM_SDDFPARM3_SST_M 0xC00U // Data filter structure (SincFast/1/2/3)
|
||||
#define SDFM_SDDFPARM3_SDSYNCEN 0x1000U // Data FILTER Reset Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDPARM3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDPARM3_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement)
|
||||
#define SDFM_SDDPARM3_SH_S 11U
|
||||
#define SDFM_SDDPARM3_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode)
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCMPH3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCMPH3_HLT_S 0U
|
||||
#define SDFM_SDCMPH3_HLT_M 0x7FFFU // High-level threshold for the comparator filter output.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCMPL3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCMPL3_LLT_S 0U
|
||||
#define SDFM_SDCMPL3_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCPARM3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCPARM3_COSR_S 0U
|
||||
#define SDFM_SDCPARM3_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1
|
||||
#define SDFM_SDCPARM3_IEH 0x20U // High-level interrupt enable
|
||||
#define SDFM_SDCPARM3_IEL 0x40U // Low-level interrupt enable
|
||||
#define SDFM_SDCPARM3_CS1_CS0_S 7U
|
||||
#define SDFM_SDCPARM3_CS1_CS0_M 0x180U // Comparator filter structure
|
||||
// (Sincfast/Sinc1/Sinc2/Sinc3
|
||||
#define SDFM_SDCPARM3_MFIE 0x200U // Modulator Failure Interrupt enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDATA3 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDATA3_DATA16_S 0U
|
||||
#define SDFM_SDDATA3_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b
|
||||
// mode
|
||||
#define SDFM_SDDATA3_DATA32HI_S 16U
|
||||
#define SDFM_SDDATA3_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCTLPARM4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCTLPARM4_MOD_S 0U
|
||||
#define SDFM_SDCTLPARM4_MOD_M 0x3U // Delta-Sigma Modulator mode
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDFPARM4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDFPARM4_DOSR_S 0U
|
||||
#define SDFM_SDDFPARM4_DOSR_M 0xFFU // SINC Filter Oversample Ratio= DOSR+1
|
||||
#define SDFM_SDDFPARM4_FEN 0x100U // Filter Enable
|
||||
#define SDFM_SDDFPARM4_AE 0x200U // Ack Enable
|
||||
#define SDFM_SDDFPARM4_SST_S 10U
|
||||
#define SDFM_SDDFPARM4_SST_M 0xC00U // Data filter structure (SincFast/1/2/3)
|
||||
#define SDFM_SDDFPARM4_SDSYNCEN 0x1000U // SINC FILTER Reset Enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDPARM4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDPARM4_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement)
|
||||
#define SDFM_SDDPARM4_SH_S 11U
|
||||
#define SDFM_SDDPARM4_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode)
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCMPH4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCMPH4_HLT_S 0U
|
||||
#define SDFM_SDCMPH4_HLT_M 0x7FFFU // High-level threshold for the comparator filter output.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCMPL4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCMPL4_LLT_S 0U
|
||||
#define SDFM_SDCMPL4_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output.
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDCPARM4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDCPARM4_COSR_S 0U
|
||||
#define SDFM_SDCPARM4_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1
|
||||
#define SDFM_SDCPARM4_IEH 0x20U // High-level interrupt enable
|
||||
#define SDFM_SDCPARM4_IEL 0x40U // Low-level interrupt enable
|
||||
#define SDFM_SDCPARM4_CS1_CS0_S 7U
|
||||
#define SDFM_SDCPARM4_CS1_CS0_M 0x180U // Comparator filter structure
|
||||
// (Sincfast/Sinc1/Sinc2/Sinc3
|
||||
#define SDFM_SDCPARM4_MFIE 0x200U // Modulator Failure Interrupt enable
|
||||
|
||||
//*************************************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SDDATA4 register
|
||||
//
|
||||
//*************************************************************************************************
|
||||
#define SDFM_SDDATA4_DATA16_S 0U
|
||||
#define SDFM_SDDATA4_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b
|
||||
// mode
|
||||
#define SDFM_SDDATA4_DATA32HI_S 16U
|
||||
#define SDFM_SDDATA4_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode
|
||||
|
||||
|
||||
|
||||
#endif
|
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Reference in New Issue