234 lines
12 KiB
C
234 lines
12 KiB
C
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//###########################################################################
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//
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// FILE: hw_cmpss.h
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//
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// TITLE: Definitions for the CMPSS registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_CMPSS_H
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#define HW_CMPSS_H
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//*************************************************************************************************
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//
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// The following are defines for the CMPSS register offsets
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//
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//*************************************************************************************************
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#define CMPSS_O_COMPCTL 0x0U // CMPSS Comparator Control Register
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#define CMPSS_O_COMPHYSCTL 0x1U // CMPSS Comparator Hysteresis Control Register
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#define CMPSS_O_COMPSTS 0x2U // CMPSS Comparator Status Register
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#define CMPSS_O_COMPSTSCLR 0x3U // CMPSS Comparator Status Clear Register
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#define CMPSS_O_COMPDACCTL 0x4U // CMPSS DAC Control Register
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#define CMPSS_O_DACHVALS 0x6U // CMPSS High DAC Value Shadow Register
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#define CMPSS_O_DACHVALA 0x7U // CMPSS High DAC Value Active Register
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#define CMPSS_O_RAMPMAXREFA 0x8U // CMPSS Ramp Max Reference Active Register
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#define CMPSS_O_RAMPMAXREFS 0xAU // CMPSS Ramp Max Reference Shadow Register
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#define CMPSS_O_RAMPDECVALA 0xCU // CMPSS Ramp Decrement Value Active Register
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#define CMPSS_O_RAMPDECVALS 0xEU // CMPSS Ramp Decrement Value Shadow Register
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#define CMPSS_O_RAMPSTS 0x10U // CMPSS Ramp Status Register
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#define CMPSS_O_DACLVALS 0x12U // CMPSS Low DAC Value Shadow Register
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#define CMPSS_O_DACLVALA 0x13U // CMPSS Low DAC Value Active Register
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#define CMPSS_O_RAMPDLYA 0x14U // CMPSS Ramp Delay Active Register
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#define CMPSS_O_RAMPDLYS 0x15U // CMPSS Ramp Delay Shadow Register
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#define CMPSS_O_CTRIPLFILCTL 0x16U // CTRIPL Filter Control Register
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#define CMPSS_O_CTRIPLFILCLKCTL 0x17U // CTRIPL Filter Clock Control Register
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#define CMPSS_O_CTRIPHFILCTL 0x18U // CTRIPH Filter Control Register
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#define CMPSS_O_CTRIPHFILCLKCTL 0x19U // CTRIPH Filter Clock Control Register
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#define CMPSS_O_COMPLOCK 0x1AU // CMPSS Lock Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the COMPCTL register
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//
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//*************************************************************************************************
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#define CMPSS_COMPCTL_COMPHSOURCE 0x1U // High Comparator Source Select
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#define CMPSS_COMPCTL_COMPHINV 0x2U // High Comparator Invert Select
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#define CMPSS_COMPCTL_CTRIPHSEL_S 2U
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#define CMPSS_COMPCTL_CTRIPHSEL_M 0xCU // High Comparator Trip Select
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#define CMPSS_COMPCTL_CTRIPOUTHSEL_S 4U
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#define CMPSS_COMPCTL_CTRIPOUTHSEL_M 0x30U // High Comparator Trip Output Select
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#define CMPSS_COMPCTL_ASYNCHEN 0x40U // High Comparator Asynchronous Path Enable
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#define CMPSS_COMPCTL_COMPLSOURCE 0x100U // Low Comparator Source Select
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#define CMPSS_COMPCTL_COMPLINV 0x200U // Low Comparator Invert Select
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#define CMPSS_COMPCTL_CTRIPLSEL_S 10U
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#define CMPSS_COMPCTL_CTRIPLSEL_M 0xC00U // Low Comparator Trip Select
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#define CMPSS_COMPCTL_CTRIPOUTLSEL_S 12U
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#define CMPSS_COMPCTL_CTRIPOUTLSEL_M 0x3000U // Low Comparator Trip Output Select
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#define CMPSS_COMPCTL_ASYNCLEN 0x4000U // Low Comparator Asynchronous Path Enable
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#define CMPSS_COMPCTL_COMPDACE 0x8000U // Comparator/DAC Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the COMPHYSCTL register
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//
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//*************************************************************************************************
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#define CMPSS_COMPHYSCTL_COMPHYS_S 0U
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#define CMPSS_COMPHYSCTL_COMPHYS_M 0x7U // Comparator Hysteresis Trim
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the COMPSTS register
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//
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//*************************************************************************************************
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#define CMPSS_COMPSTS_COMPHSTS 0x1U // High Comparator Status
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#define CMPSS_COMPSTS_COMPHLATCH 0x2U // High Comparator Latched Status
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#define CMPSS_COMPSTS_COMPLSTS 0x100U // Low Comparator Status
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#define CMPSS_COMPSTS_COMPLLATCH 0x200U // Low Comparator Latched Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the COMPSTSCLR register
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//
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//*************************************************************************************************
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#define CMPSS_COMPSTSCLR_HLATCHCLR 0x2U // High Comparator Latched Status Clear
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#define CMPSS_COMPSTSCLR_HSYNCCLREN 0x4U // High Comparator EPWMSYNCPER Clear Enable
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#define CMPSS_COMPSTSCLR_LLATCHCLR 0x200U // Low Comparator Latched Status Clear
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#define CMPSS_COMPSTSCLR_LSYNCCLREN 0x400U // Low Comparator EPWMSYNCPER Clear Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the COMPDACCTL register
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//
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//*************************************************************************************************
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#define CMPSS_COMPDACCTL_DACSOURCE 0x1U // DAC Source Control
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#define CMPSS_COMPDACCTL_RAMPSOURCE_S 1U
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#define CMPSS_COMPDACCTL_RAMPSOURCE_M 0x1EU // Ramp Generator Source Control
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#define CMPSS_COMPDACCTL_SELREF 0x20U // DAC Reference Select
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#define CMPSS_COMPDACCTL_RAMPLOADSEL 0x40U // Ramp Load Select
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#define CMPSS_COMPDACCTL_SWLOADSEL 0x80U // Software Load Select
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#define CMPSS_COMPDACCTL_FREESOFT_S 14U
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#define CMPSS_COMPDACCTL_FREESOFT_M 0xC000U // Free/Soft Emulation Bits
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DACHVALS register
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//
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//*************************************************************************************************
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#define CMPSS_DACHVALS_DACVAL_S 0U
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#define CMPSS_DACHVALS_DACVAL_M 0xFFFU // DAC Value Control
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DACHVALA register
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//
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//*************************************************************************************************
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#define CMPSS_DACHVALA_DACVAL_S 0U
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#define CMPSS_DACHVALA_DACVAL_M 0xFFFU // DAC Value Control
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DACLVALS register
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//
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//*************************************************************************************************
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#define CMPSS_DACLVALS_DACVAL_S 0U
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#define CMPSS_DACLVALS_DACVAL_M 0xFFFU // DAC Value Control
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DACLVALA register
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//
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//*************************************************************************************************
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#define CMPSS_DACLVALA_DACVAL_S 0U
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#define CMPSS_DACLVALA_DACVAL_M 0xFFFU // DAC Value Control
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the RAMPDLYA register
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//
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//*************************************************************************************************
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#define CMPSS_RAMPDLYA_DELAY_S 0U
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#define CMPSS_RAMPDLYA_DELAY_M 0x1FFFU // Ramp Delay Value
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the RAMPDLYS register
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//
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//*************************************************************************************************
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#define CMPSS_RAMPDLYS_DELAY_S 0U
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#define CMPSS_RAMPDLYS_DELAY_M 0x1FFFU // Ramp Delay Value
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CTRIPLFILCTL register
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//
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//*************************************************************************************************
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#define CMPSS_CTRIPLFILCTL_SAMPWIN_S 4U
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#define CMPSS_CTRIPLFILCTL_SAMPWIN_M 0x1F0U // Sample Window
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#define CMPSS_CTRIPLFILCTL_THRESH_S 9U
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#define CMPSS_CTRIPLFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold
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#define CMPSS_CTRIPLFILCTL_FILINIT 0x8000U // Filter Initialization Bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CTRIPLFILCLKCTL register
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//
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//*************************************************************************************************
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#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_S 0U
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#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CTRIPHFILCTL register
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//
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//*************************************************************************************************
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#define CMPSS_CTRIPHFILCTL_SAMPWIN_S 4U
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#define CMPSS_CTRIPHFILCTL_SAMPWIN_M 0x1F0U // Sample Window
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#define CMPSS_CTRIPHFILCTL_THRESH_S 9U
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#define CMPSS_CTRIPHFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold
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#define CMPSS_CTRIPHFILCTL_FILINIT 0x8000U // Filter Initialization Bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CTRIPHFILCLKCTL register
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//
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//*************************************************************************************************
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#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_S 0U
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#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the COMPLOCK register
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//
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//*************************************************************************************************
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#define CMPSS_COMPLOCK_COMPCTL 0x1U // COMPCTL Lock
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#define CMPSS_COMPLOCK_COMPHYSCTL 0x2U // COMPHYSCTL Lock
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#define CMPSS_COMPLOCK_DACCTL 0x4U // DACCTL Lock
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#define CMPSS_COMPLOCK_CTRIP 0x8U // CTRIP Lock
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#endif
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