156 lines
7.5 KiB
C
156 lines
7.5 KiB
C
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//###########################################################################
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//
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// FILE: hw_spi.h
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//
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// TITLE: Definitions for the SPI registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_SPI_H
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#define HW_SPI_H
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//*************************************************************************************************
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//
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// The following are defines for the SPI register offsets
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//
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//*************************************************************************************************
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#define SPI_O_CCR 0x0U // SPI Configuration Control Register
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#define SPI_O_CTL 0x1U // SPI Operation Control Register
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#define SPI_O_STS 0x2U // SPI Status Register
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#define SPI_O_BRR 0x4U // SPI Baud Rate Register
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#define SPI_O_RXEMU 0x6U // SPI Emulation Buffer Register
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#define SPI_O_RXBUF 0x7U // SPI Serial Input Buffer Register
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#define SPI_O_TXBUF 0x8U // SPI Serial Output Buffer Register
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#define SPI_O_DAT 0x9U // SPI Serial Data Register
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#define SPI_O_FFTX 0xAU // SPI FIFO Transmit Register
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#define SPI_O_FFRX 0xBU // SPI FIFO Receive Register
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#define SPI_O_FFCT 0xCU // SPI FIFO Control Register
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#define SPI_O_PRI 0xFU // SPI Priority Control Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SPICCR register
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//
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//*************************************************************************************************
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#define SPI_CCR_SPICHAR_S 0U
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#define SPI_CCR_SPICHAR_M 0xFU // Character Length Control
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#define SPI_CCR_SPILBK 0x10U // SPI Loopback
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#define SPI_CCR_HS_MODE 0x20U // High Speed mode control
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#define SPI_CCR_CLKPOLARITY 0x40U // Shift Clock Polarity
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#define SPI_CCR_SPISWRESET 0x80U // SPI Software Reset
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SPICTL register
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//
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//*************************************************************************************************
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#define SPI_CTL_SPIINTENA 0x1U // SPI Interupt Enable
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#define SPI_CTL_TALK 0x2U // Master/Slave Transmit Enable
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#define SPI_CTL_MASTER_SLAVE 0x4U // SPI Network Mode Control
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#define SPI_CTL_CLK_PHASE 0x8U // SPI Clock Phase
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#define SPI_CTL_OVERRUNINTENA 0x10U // Overrun Interrupt Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SPISTS register
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//
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//*************************************************************************************************
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#define SPI_STS_BUFFULL_FLAG 0x20U // SPI Transmit Buffer Full Flag
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#define SPI_STS_INT_FLAG 0x40U // SPI Interrupt Flag
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#define SPI_STS_OVERRUN_FLAG 0x80U // SPI Receiver Overrun Flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SPIBRR register
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//
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//*************************************************************************************************
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#define SPI_BRR_SPI_BIT_RATE_S 0U
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#define SPI_BRR_SPI_BIT_RATE_M 0x7FU // SPI Bit Rate Control
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SPIFFTX register
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//
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//*************************************************************************************************
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#define SPI_FFTX_TXFFIL_S 0U
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#define SPI_FFTX_TXFFIL_M 0x1FU // TXFIFO Interrupt Level
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#define SPI_FFTX_TXFFIENA 0x20U // TXFIFO Interrupt Enable
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#define SPI_FFTX_TXFFINTCLR 0x40U // TXFIFO Interrupt Clear
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#define SPI_FFTX_TXFFINT 0x80U // TXFIFO Interrupt Flag
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#define SPI_FFTX_TXFFST_S 8U
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#define SPI_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status
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#define SPI_FFTX_TXFIFO 0x2000U // TXFIFO Reset
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#define SPI_FFTX_SPIFFENA 0x4000U // FIFO Enhancements Enable
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#define SPI_FFTX_SPIRST 0x8000U // SPI Reset
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SPIFFRX register
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//
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//*************************************************************************************************
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#define SPI_FFRX_RXFFIL_S 0U
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#define SPI_FFRX_RXFFIL_M 0x1FU // RXFIFO Interrupt Level
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#define SPI_FFRX_RXFFIENA 0x20U // RXFIFO Interrupt Enable
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#define SPI_FFRX_RXFFINTCLR 0x40U // RXFIFO Interupt Clear
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#define SPI_FFRX_RXFFINT 0x80U // RXFIFO Interrupt Flag
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#define SPI_FFRX_RXFFST_S 8U
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#define SPI_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status
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#define SPI_FFRX_RXFIFORESET 0x2000U // RXFIFO Reset
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#define SPI_FFRX_RXFFOVFCLR 0x4000U // Receive FIFO Overflow Clear
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#define SPI_FFRX_RXFFOVF 0x8000U // Receive FIFO Overflow Flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SPIFFCT register
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//
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//*************************************************************************************************
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#define SPI_FFCT_TXDLY_S 0U
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#define SPI_FFCT_TXDLY_M 0xFFU // FIFO Transmit Delay Bits
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SPIPRI register
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//
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//*************************************************************************************************
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#define SPI_PRI_TRIWIRE 0x1U // 3-wire mode select bit
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#define SPI_PRI_STEINV 0x2U // SPISTE inversion bit
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#define SPI_PRI_FREE 0x10U // Free emulation mode
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#define SPI_PRI_SOFT 0x20U // Soft emulation mode
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#endif
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