297 lines
9.0 KiB
C
297 lines
9.0 KiB
C
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//###########################################################################
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//
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// FILE: upp.c
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//
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// TITLE: C28x uPP driver.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#include <stdbool.h>
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#include <stdint.h>
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#include "upp.h"
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//*****************************************************************************
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//
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// UPP_setDMAReadThreshold
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//
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//*****************************************************************************
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void
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UPP_setDMAReadThreshold(uint32_t base, UPP_DMAChannel channel,
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UPP_ThresholdSize size)
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{
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//
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// Check the arguments.
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//
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ASSERT(UPP_isBaseValid(base));
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if(channel == UPP_DMA_CHANNEL_I)
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{
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//
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// Set DMA read threshold for channel I.
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//
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HWREGH(base + UPP_O_THCFG) = (HWREGH(base + UPP_O_THCFG) &
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~(uint16_t)UPP_THCFG_RDSIZEI_M) |
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(uint16_t)size;
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}
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else
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{
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//
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// Set DMA read threshold for channel Q.
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//
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HWREGH(base + UPP_O_THCFG) = (HWREGH(base + UPP_O_THCFG) &
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~(uint16_t)UPP_THCFG_RDSIZEQ_M) |
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((uint16_t)size << UPP_THCFG_RDSIZEQ_S);
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}
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}
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//*****************************************************************************
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//
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// UPP_setDMADescriptor
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//
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//*****************************************************************************
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void
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UPP_setDMADescriptor(uint32_t base, UPP_DMAChannel channel,
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const UPP_DMADescriptor * const desc)
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{
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//
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// Check the arguments.
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//
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ASSERT(UPP_isBaseValid(base));
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if(channel == UPP_DMA_CHANNEL_I)
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{
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//
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// Sets DMA descriptors for channel I.
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//
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HWREG(base + UPP_O_CHIDESC0) = desc->addr;
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HWREG(base + UPP_O_CHIDESC1) = ((uint32_t)desc->byteCount |
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(((uint32_t)desc->lineCount) <<
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UPP_CHIDESC1_LCNT_S));
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HWREGH(base + UPP_O_CHIDESC2) = desc->lineOffset;
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}
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else
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{
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//
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// Sets DMA descriptors for channel Q.
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//
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HWREG(base + UPP_O_CHQDESC0) = desc->addr;
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HWREG(base + UPP_O_CHQDESC1) = ((uint32_t)desc->byteCount |
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(((uint32_t)desc->lineCount) <<
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UPP_CHQDESC1_LCNT_S));
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HWREGH(base + UPP_O_CHQDESC2) = desc->lineOffset;
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}
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}
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//*****************************************************************************
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//
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// UPP_getDMAChannelStatus
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//
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//*****************************************************************************
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void
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UPP_getDMAChannelStatus(uint32_t base, UPP_DMAChannel channel,
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UPP_DMAChannelStatus * const status)
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{
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uint32_t cntStatus;
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//
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// Check the arguments.
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//
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ASSERT(UPP_isBaseValid(base));
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if(channel == UPP_DMA_CHANNEL_I)
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{
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//
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// Return the current status for channel I.
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//
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cntStatus = HWREG(base + UPP_O_CHIST1);
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status->curAddr = HWREG(base + UPP_O_CHIST0);
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status->curByteCount = (uint16_t)(cntStatus & UPP_CHIDESC1_BCNT_M);
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status->curLineCount = (uint16_t)(cntStatus >> UPP_CHIDESC1_LCNT_S);
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}
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else
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{
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//
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// Return the current status for channel Q.
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//
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cntStatus = HWREG(base + UPP_O_CHQST1);
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status->curAddr = HWREG(base + UPP_O_CHQST0);
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status->curByteCount = (uint16_t)(cntStatus & UPP_CHQDESC1_BCNT_M);
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status->curLineCount = (uint16_t)(cntStatus >> UPP_CHQDESC1_LCNT_S);
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}
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}
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//*****************************************************************************
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//
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// UPP_isDescriptorPending
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//
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//*****************************************************************************
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bool
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UPP_isDescriptorPending(uint32_t base, UPP_DMAChannel channel)
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{
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bool status;
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//
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// Check the arguments.
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//
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ASSERT(UPP_isBaseValid(base));
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if(channel == UPP_DMA_CHANNEL_I)
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{
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//
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// Return the pend status for channel I descriptor.
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//
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status = ((HWREGH(base + UPP_O_CHIST2) &
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(uint16_t)UPP_CHIST2_PEND) == UPP_CHIST2_PEND);
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}
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else
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{
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//
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// Return the pend status for channel Q descriptor.
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//
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status = ((HWREGH(base + UPP_O_CHQST2) &
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(uint16_t)UPP_CHQST2_PEND) == UPP_CHQST2_PEND);
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}
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return(status);
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}
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//*****************************************************************************
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//
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// UPP_isDescriptorActive
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//
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//*****************************************************************************
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bool
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UPP_isDescriptorActive(uint32_t base, UPP_DMAChannel channel)
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{
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bool status;
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//
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// Check the arguments.
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//
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ASSERT(UPP_isBaseValid(base));
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if(channel == UPP_DMA_CHANNEL_I)
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{
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//
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// Returns active status for channel I descriptor.
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//
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status = ((HWREGH(base + UPP_O_CHIST2) &
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(uint16_t)UPP_CHIST2_ACT) == UPP_CHIST2_ACT);
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}
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else
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{
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//
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// Returns active status for channel Q descriptor.
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//
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status = ((HWREGH(base + UPP_O_CHQST2) &
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(uint16_t)UPP_CHQST2_ACT) == UPP_CHQST2_ACT);
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}
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return(status);
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}
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//*****************************************************************************
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//
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// UPP_getDMAFIFOWatermark
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//
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//*****************************************************************************
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uint16_t
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UPP_getDMAFIFOWatermark(uint32_t base, UPP_DMAChannel channel)
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{
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uint16_t status;
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//
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// Check the arguments.
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//
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ASSERT(UPP_isBaseValid(base));
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if(channel == UPP_DMA_CHANNEL_I)
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{
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//
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// Return the watermark for FIFO block count for DMA Channel I.
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//
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status = ((HWREGH(base + UPP_O_CHIST2) &
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(uint16_t)UPP_CHIST2_WM_M) >> UPP_CHIST2_WM_S);
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}
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else
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{
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//
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// Return the watermark for FIFO block count for DMA Channel I.
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//
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status = ((HWREGH(base + UPP_O_CHQST2) &
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(uint16_t)UPP_CHQST2_WM_M) >> UPP_CHQST2_WM_S);
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}
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return(status);
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}
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//*****************************************************************************
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//
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// UPP_readRxMsgRAM
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//
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//*****************************************************************************
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void
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UPP_readRxMsgRAM(uint32_t rxBase, uint16_t array[], uint16_t length,
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uint16_t offset)
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{
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uint16_t i;
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//
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// Check the arguments.
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//
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ASSERT(UPP_isRxBaseValid(rxBase));
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ASSERT((length + offset) < UPP_RX_MSGRAM_MAX_SIZE);
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for(i = 0U; i < length; i++)
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{
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//
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// Read one 16-bit word.
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//
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array[i] = HWREGH(rxBase + offset + i);
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}
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}
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//*****************************************************************************
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//
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// UPP_writeTxMsgRAM
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//
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//*****************************************************************************
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void
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UPP_writeTxMsgRAM(uint32_t txBase, const uint16_t array[], uint16_t length,
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uint16_t offset)
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{
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uint16_t i;
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//
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// Check the arguments.
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//
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ASSERT(UPP_isTxBaseValid(txBase));
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ASSERT((length + offset) < UPP_TX_MSGRAM_MAX_SIZE);
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for(i = 0U; i < length; i++)
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{
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//
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// Write one 16-bit word.
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//
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HWREGH(txBase + offset + i) = array[i];
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}
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}
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