110 lines
5.2 KiB
C
110 lines
5.2 KiB
C
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#ifndef DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_
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#define DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_
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//*****************************************************************************
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// CLB
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//*****************************************************************************
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#define CLB_LOCAL_IN_MUX_SPISIMO_SLAVE CLB_LOCAL_IN_MUX_SPIPICO_PERIPHERAL
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#define CLB_LOCAL_IN_MUX_SPISIMO_MASTER CLB_LOCAL_IN_MUX_SPIPICO_CONTROLLER
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#define CLB_GLOBAL_IN_MUX_SPI1_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI1_SPIPOCI_CONTROLLER
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#define CLB_GLOBAL_IN_MUX_SPI1_SPISTE CLB_GLOBAL_IN_MUX_SPI1_SPIPTE
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#define CLB_GLOBAL_IN_MUX_SPI2_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI2_SPIPOCI_CONTROLLER
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#define CLB_GLOBAL_IN_MUX_SPI2_SPISTE CLB_GLOBAL_IN_MUX_SPI2_SPIPTE
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#define CLB_GLOBAL_IN_MUX_SPI3_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI3_SPIPOCI_CONTROLLER
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#define CLB_GLOBAL_IN_MUX_SPI3_SPISTE CLB_GLOBAL_IN_MUX_SPI3_SPIPTE
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#define CLB_GLOBAL_IN_MUX_SPI4_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI4_SPIPOCI_CONTROLLER
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#define CLB_GLOBAL_IN_MUX_SPI4_SPISTE CLB_GLOBAL_IN_MUX_SPI4_SPIPTE
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//*****************************************************************************
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// SPI
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//*****************************************************************************
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#define SPI_MODE_SLAVE SPI_MODE_PERIPHERAL
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#define SPI_MODE_MASTER SPI_MODE_CONTROLLER
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#define SPI_MODE_SLAVE_OD SPI_MODE_PERIPHERAL_OD
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#define SPI_MODE_MASTER_OD SPI_MODE_CONTROLLER_OD
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#define SPI_STE_ACTIVE_LOW SPI_PTE_ACTIVE_LOW
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#define SPI_STE_ACTIVE_HIGH SPI_PTE_ACTIVE_HIGH
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#define SPI_setSTESignalPolarity SPI_setPTESignalPolarity
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//*****************************************************************************
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// Interrupt
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//*****************************************************************************
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#define Interrupt_enableMaster Interrupt_enableGlobal
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#define Interrupt_disableMaster Interrupt_disableGlobal
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//*****************************************************************************
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// SysCtrl
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//*****************************************************************************
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#define SysCtl_AccessMaster SysCtl_AccessController
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#define SYSCTL_SEC_MASTER_CLA SYSCTL_SEC_CONTROLLER_CLA
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#define SYSCTL_SEC_MASTER_DMA SYSCTL_SEC_CONTROLLER_DMA
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#define SysCtl_selectSecMaster SysCtl_selectSecController
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//*****************************************************************************
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// GPIO
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//*****************************************************************************
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#define GPIO_setMasterCore GPIO_setControllerCore
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//*****************************************************************************
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// Memcfg
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//*****************************************************************************
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#define MemCfg_LSRAMMMasterSel MemCfg_LSRAMMControllerSel
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#define MEMCFG_LSRAMMASTER_CPU_ONLY MEMCFG_LSRAMCONTROLLER_CPU_ONLY
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#define MEMCFG_LSRAMMASTER_CPU_CLA1 MEMCFG_LSRAMCONTROLLER_CPU_CLA1
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#define MemCfg_setLSRAMMasterSel MemCfg_setLSRAMControllerSel
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#define MemCfg_GSRAMMasterSel MemCfg_GSRAMControllerSel
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#define MEMCFG_GSRAMMASTER_CPU1 MEMCFG_GSRAMCONTROLLER_CPU1
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#define MEMCFG_GSRAMMASTER_CPU2 MEMCFG_GSRAMCONTROLLER_CPU2
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#define MemCfg_setGSRAMMasterSel MemCfg_setGSRAMControllerSel
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//*****************************************************************************
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// EMIF
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//*****************************************************************************
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#define EMIF_MasterSelect EMIF_ControllerSelect
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#define EMIF_selectMaster EMIF_selectController
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#define EMIF_MASTER_CPU1_NG EMIF_CONTROLLER_CPU1_NG
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#define EMIF_MASTER_CPU1_G EMIF_CONTROLLER_CPU1_G
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#define EMIF_MASTER_CPU2_G EMIF_CONTROLLER_CPU2_G
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#define EMIF_MASTER_CPU1_NG2 EMIF_CONTROLLER_CPU1_NG2
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//*****************************************************************************
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// I2C
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//*****************************************************************************
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#define I2C_MASTER_SEND_MODE I2C_CONTROLLER_SEND_MODE
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#define I2C_MASTER_RECEIVE_MODE I2C_CONTROLLER_RECEIVE_MODE
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#define I2C_SLAVE_SEND_MODE I2C_TARGET_SEND_MODE
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#define I2C_SLAVE_RECEIVE_MODE I2C_TARGET_RECEIVE_MODE
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#define I2C_INT_ADDR_SLAVE I2C_INT_ADDR_TARGET
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#define I2C_STS_ADDR_SLAVE I2C_STS_ADDR_TARGET
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#define I2C_STS_SLAVE_DIR I2C_STS_TARGET_DIR
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#define I2C_INTSRC_ADDR_SLAVE I2C_INTSRC_ADDR_TARGET
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#define I2C_initMaster I2C_initController
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#define I2C_setSlaveAddress I2C_setTargetAddress
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#define I2C_setOwnSlaveAddress I2C_setOwnAddress
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//*****************************************************************************
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// SDFM
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//*****************************************************************************
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#define SDFM_enableMasterInterrupt SDFM_enableMainInterrupt
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#define SDFM_disableMasterInterrupt SDFM_disableMainInterrupt
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#define SDFM_enableMasterFilter SDFM_enableMainFilter
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#define SDFM_disableMasterFilter SDFM_disableMainFilter
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#define SDFM_MASTER_INTERRUPT_FLAG SDFM_MAIN_INTERRUPT_FLAG
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#endif /* DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ */
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