488 lines
12 KiB
C
488 lines
12 KiB
C
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//###########################################################################
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//
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// FILE: gpio.c
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//
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// TITLE: C28x GPIO driver.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#include "gpio.h"
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//*****************************************************************************
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//
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// GPIO_setDirectionMode
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//
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//*****************************************************************************
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void
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GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO)
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{
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volatile uint32_t *gpioBaseAddr;
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uint32_t pinMask;
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//
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// Check the arguments.
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//
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ASSERT(GPIO_isPinValid(pin));
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gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
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((pin / 32U) * GPIO_CTRL_REGS_STEP);
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pinMask = (uint32_t)1U << (pin % 32U);
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EALLOW;
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//
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// Set the data direction
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//
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if(pinIO == GPIO_DIR_MODE_OUT)
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{
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//
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// Output
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//
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gpioBaseAddr[GPIO_GPxDIR_INDEX] |= pinMask;
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}
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else
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{
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//
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// Input
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//
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gpioBaseAddr[GPIO_GPxDIR_INDEX] &= ~pinMask;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// GPIO_getDirectionMode
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//
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//*****************************************************************************
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GPIO_Direction
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GPIO_getDirectionMode(uint32_t pin)
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{
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volatile uint32_t *gpioBaseAddr;
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//
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// Check the arguments.
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//
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ASSERT(GPIO_isPinValid(pin));
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gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
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((pin / 32U) * GPIO_CTRL_REGS_STEP);
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return((GPIO_Direction)((uint32_t)((gpioBaseAddr[GPIO_GPxDIR_INDEX] >>
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(pin % 32U)) & 1U)));
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}
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//*****************************************************************************
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//
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// GPIO_setInterruptPin
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//
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//*****************************************************************************
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void
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GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum)
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{
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XBAR_InputNum input;
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//
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// Check the arguments.
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//
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ASSERT(GPIO_isPinValid(pin));
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//
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// Pick the X-BAR input that corresponds to the requested XINT.
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//
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switch(extIntNum)
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{
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case GPIO_INT_XINT1:
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input = XBAR_INPUT4;
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break;
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case GPIO_INT_XINT2:
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input = XBAR_INPUT5;
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break;
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case GPIO_INT_XINT3:
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input = XBAR_INPUT6;
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break;
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case GPIO_INT_XINT4:
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input = XBAR_INPUT13;
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break;
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case GPIO_INT_XINT5:
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input = XBAR_INPUT14;
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break;
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default:
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//
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// Invalid interrupt. Shouldn't happen if enum value is used.
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// XBAR_INPUT1 isn't tied to an XINT, so we'll use it to check for
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// a bad value.
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//
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input = XBAR_INPUT1;
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break;
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}
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if(input != XBAR_INPUT1)
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{
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XBAR_setInputPin(input, (uint16_t)pin);
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}
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}
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//*****************************************************************************
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//
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// GPIO_setPadConfig
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//
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//*****************************************************************************
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void
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GPIO_setPadConfig(uint32_t pin, uint32_t pinType)
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{
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volatile uint32_t *gpioBaseAddr;
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uint32_t pinMask;
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//
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// Check the arguments.
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//
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ASSERT(GPIO_isPinValid(pin));
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gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
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((pin / 32U) * GPIO_CTRL_REGS_STEP);
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pinMask = (uint32_t)1U << (pin % 32U);
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EALLOW;
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//
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// Enable open drain if necessary
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//
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if((pinType & GPIO_PIN_TYPE_OD) != 0U)
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{
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gpioBaseAddr[GPIO_GPxODR_INDEX] |= pinMask;
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}
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else
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{
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gpioBaseAddr[GPIO_GPxODR_INDEX] &= ~pinMask;
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}
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//
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// Enable pull-up if necessary
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//
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if((pinType & GPIO_PIN_TYPE_PULLUP) != 0U)
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{
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gpioBaseAddr[GPIO_GPxPUD_INDEX] &= ~pinMask;
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}
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else
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{
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gpioBaseAddr[GPIO_GPxPUD_INDEX] |= pinMask;
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}
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//
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// Invert polarity if necessary
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//
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if((pinType & GPIO_PIN_TYPE_INVERT) != 0U)
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{
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gpioBaseAddr[GPIO_GPxINV_INDEX] |= pinMask;
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}
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else
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{
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gpioBaseAddr[GPIO_GPxINV_INDEX] &= ~pinMask;
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}
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EDIS;
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}
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//*****************************************************************************
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//
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// GPIO_getPadConfig
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//
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//*****************************************************************************
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uint32_t
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GPIO_getPadConfig(uint32_t pin)
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{
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volatile uint32_t *gpioBaseAddr;
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uint32_t pinMask;
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uint32_t pinTypeRes;
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//
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// Check the arguments.
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//
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ASSERT(GPIO_isPinValid(pin));
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gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
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((pin / 32U) * GPIO_CTRL_REGS_STEP);
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pinMask = (uint32_t)1U << (pin % 32U);
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pinTypeRes = GPIO_PIN_TYPE_STD;
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//
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// Get open drain value
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//
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if((gpioBaseAddr[GPIO_GPxODR_INDEX] & pinMask) != 0U)
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{
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pinTypeRes |= GPIO_PIN_TYPE_OD;
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}
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//
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// Get pull-up value
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//
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if((gpioBaseAddr[GPIO_GPxPUD_INDEX] & pinMask) == 0U)
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{
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pinTypeRes |= GPIO_PIN_TYPE_PULLUP;
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}
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//
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// Get polarity value
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//
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if((gpioBaseAddr[GPIO_GPxINV_INDEX] & pinMask) != 0U)
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{
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pinTypeRes |= GPIO_PIN_TYPE_INVERT;
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}
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return(pinTypeRes);
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}
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//*****************************************************************************
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//
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// GPIO_setQualificationMode
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//
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//*****************************************************************************
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void
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GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification)
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{
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volatile uint32_t *gpioBaseAddr;
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uint32_t qSelIndex;
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uint32_t shiftAmt;
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//
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// Check the arguments.
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//
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ASSERT(GPIO_isPinValid(pin));
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gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
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((pin / 32U) * GPIO_CTRL_REGS_STEP);
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shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U);
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qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U);
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//
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// Write the input qualification mode to the register.
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//
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EALLOW;
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gpioBaseAddr[qSelIndex] &= ~((uint32_t)GPIO_GPAQSEL1_GPIO0_M << shiftAmt);
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gpioBaseAddr[qSelIndex] |= (uint32_t)qualification << shiftAmt;
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EDIS;
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}
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//*****************************************************************************
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//
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// GPIO_getQualificationMode
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//
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//*****************************************************************************
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GPIO_QualificationMode
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GPIO_getQualificationMode(uint32_t pin)
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{
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volatile uint32_t *gpioBaseAddr;
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uint32_t qSelIndex;
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uint32_t qualRes;
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uint32_t shiftAmt;
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//
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// Check the arguments.
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//
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ASSERT(GPIO_isPinValid(pin));
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gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
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((pin / 32U) * GPIO_CTRL_REGS_STEP);
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shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U);
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qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U);
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//
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// Read the qualification mode register and shift and mask to get the
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// value for the specified pin.
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//
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qualRes = (gpioBaseAddr[qSelIndex] >> shiftAmt) &
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(uint32_t)GPIO_GPAQSEL1_GPIO0_M;
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return((GPIO_QualificationMode)qualRes);
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}
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//*****************************************************************************
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//
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// GPIO_setQualificationPeriod
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//
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//*****************************************************************************
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void
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GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider)
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{
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volatile uint32_t *gpioBaseAddr;
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uint32_t pinMask, regVal, shiftAmt;
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//
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// Check the arguments.
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//
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ASSERT(GPIO_isPinValid(pin));
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ASSERT((divider >= 1U) && (divider <= 510U));
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shiftAmt = (pin % 32U) & ~((uint32_t)0x7U);
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pinMask = (uint32_t)0xFFU << shiftAmt;
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//
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// Divide divider by two to get the value that needs to go into the field.
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// Then shift it into the right place.
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//
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regVal = (divider / 2U) << shiftAmt;
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//
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// Write the divider parameter into the register.
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//
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gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
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((pin / 32U) * GPIO_CTRL_REGS_STEP);
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EALLOW;
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gpioBaseAddr[GPIO_GPxCTRL_INDEX] &= ~pinMask;
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gpioBaseAddr[GPIO_GPxCTRL_INDEX] |= regVal;
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EDIS;
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}
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//*****************************************************************************
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//
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// GPIO_setControllerCore
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//
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//*****************************************************************************
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void
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GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core)
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{
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volatile uint32_t *gpioBaseAddr;
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uint32_t cSelIndex;
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uint32_t shiftAmt;
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//
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// Check the arguments.
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//
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ASSERT(GPIO_isPinValid(pin));
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gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
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((pin / 32U) * GPIO_CTRL_REGS_STEP);
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shiftAmt = (uint32_t)GPIO_GPACSEL1_GPIO1_S * (pin % 8U);
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cSelIndex = GPIO_GPxCSEL_INDEX + ((pin % 32U) / 8U);
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//
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// Write the core parameter into the register.
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//
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EALLOW;
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gpioBaseAddr[cSelIndex] &= ~((uint32_t)GPIO_GPACSEL1_GPIO0_M << shiftAmt);
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gpioBaseAddr[cSelIndex] |= (uint32_t)core << shiftAmt;
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EDIS;
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}
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//*****************************************************************************
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||
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//
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||
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// GPIO_setAnalogMode
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode)
|
||
|
|
{
|
||
|
|
volatile uint32_t *gpioBaseAddr;
|
||
|
|
uint32_t pinMask;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT((pin == 42U) || (pin == 43U));
|
||
|
|
|
||
|
|
pinMask = (uint32_t)1U << (pin % 32U);
|
||
|
|
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
|
||
|
|
((pin / 32U) * GPIO_CTRL_REGS_STEP);
|
||
|
|
|
||
|
|
EALLOW;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Set the analog mode selection.
|
||
|
|
//
|
||
|
|
if(mode == GPIO_ANALOG_ENABLED)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Enable analog mode
|
||
|
|
//
|
||
|
|
gpioBaseAddr[GPIO_GPxAMSEL_INDEX] |= pinMask;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Disable analog mode
|
||
|
|
//
|
||
|
|
gpioBaseAddr[GPIO_GPxAMSEL_INDEX] &= ~pinMask;
|
||
|
|
}
|
||
|
|
|
||
|
|
EDIS;
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// GPIO_setPinConfig
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
GPIO_setPinConfig(uint32_t pinConfig)
|
||
|
|
{
|
||
|
|
uint32_t muxRegAddr;
|
||
|
|
uint32_t pinMask, shiftAmt;
|
||
|
|
|
||
|
|
muxRegAddr = (uint32_t)GPIOCTRL_BASE + (pinConfig >> 16);
|
||
|
|
shiftAmt = ((pinConfig >> 8) & (uint32_t)0xFFU);
|
||
|
|
pinMask = (uint32_t)0x3U << shiftAmt;
|
||
|
|
|
||
|
|
EALLOW;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Clear fields in MUX register first to avoid glitches
|
||
|
|
//
|
||
|
|
HWREG(muxRegAddr) &= ~pinMask;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Write value into GMUX register
|
||
|
|
//
|
||
|
|
HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) =
|
||
|
|
(HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) & ~pinMask) |
|
||
|
|
(((pinConfig >> 2) & (uint32_t)0x3U) << shiftAmt);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Write value into MUX register
|
||
|
|
//
|
||
|
|
HWREG(muxRegAddr) |= ((pinConfig & (uint32_t)0x3U) << shiftAmt);
|
||
|
|
EDIS;
|
||
|
|
}
|