441 lines
24 KiB
C
441 lines
24 KiB
C
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//###########################################################################
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//
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// FILE: hw_dcsm.h
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//
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// TITLE: Definitions for the DCSM registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_DCSM_H
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#define HW_DCSM_H
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//*************************************************************************************************
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//
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// The following are defines for the DCSM register offsets
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//
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//*************************************************************************************************
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#define DCSM_O_Z1OTP_LINKPOINTER1 0x0U // Zone 1 Link Pointer1 in Z1 OTP
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#define DCSM_O_Z1OTP_LINKPOINTER2 0x4U // Zone 1 Link Pointer2 in Z1 OTP
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#define DCSM_O_Z1OTP_LINKPOINTER3 0x8U // Zone 1 Link Pointer3 in Z1 OTP
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#define DCSM_O_Z1OTP_PSWDLOCK 0x10U // Secure Password Lock in Z1 OTP
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#define DCSM_O_Z1OTP_CRCLOCK 0x14U // Secure CRC Lock in Z1 OTP
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#define DCSM_O_Z1OTP_BOOTCTRL 0x1EU // Boot Mode in Z1 OTP
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#define DCSM_O_Z2OTP_LINKPOINTER1 0x0U // Zone 2 Link Pointer1 in Z2 OTP
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#define DCSM_O_Z2OTP_LINKPOINTER2 0x4U // Zone 2 Link Pointer2 in Z2 OTP
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#define DCSM_O_Z2OTP_LINKPOINTER3 0x8U // Zone 2 Link Pointer3 in Z2 OTP
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#define DCSM_O_Z2OTP_PSWDLOCK 0x10U // Secure Password Lock in Z2 OTP
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#define DCSM_O_Z2OTP_CRCLOCK 0x14U // Secure CRC Lock in Z2 OTP
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#define DCSM_O_Z2OTP_BOOTCTRL 0x1EU // Boot Mode in Z2 OTP
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#define DCSM_O_Z1_LINKPOINTER 0x0U // Zone 1 Link Pointer
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#define DCSM_O_Z1_OTPSECLOCK 0x2U // Zone 1 OTP Secure JTAG lock
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#define DCSM_O_Z1_BOOTCTRL 0x4U // Boot Mode
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#define DCSM_O_Z1_LINKPOINTERERR 0x6U // Link Pointer Error
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#define DCSM_O_Z1_CSMKEY0 0x10U // Zone 1 CSM Key 0
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#define DCSM_O_Z1_CSMKEY1 0x12U // Zone 1 CSM Key 1
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#define DCSM_O_Z1_CSMKEY2 0x14U // Zone 1 CSM Key 2
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#define DCSM_O_Z1_CSMKEY3 0x16U // Zone 1 CSM Key 3
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#define DCSM_O_Z1_CR 0x19U // Zone 1 CSM Control Register
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#define DCSM_O_Z1_GRABSECTR 0x1AU // Zone 1 Grab Flash Sectors Register
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#define DCSM_O_Z1_GRABRAMR 0x1CU // Zone 1 Grab RAM Blocks Register
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#define DCSM_O_Z1_EXEONLYSECTR 0x1EU // Zone 1 Flash Execute_Only Sector Register
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#define DCSM_O_Z1_EXEONLYRAMR 0x20U // Zone 1 RAM Execute_Only Block Register
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#define DCSM_O_Z2_LINKPOINTER 0x0U // Zone 2 Link Pointer
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#define DCSM_O_Z2_OTPSECLOCK 0x2U // Zone 2 OTP Secure JTAG lock
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#define DCSM_O_Z2_BOOTCTRL 0x4U // Boot Mode
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#define DCSM_O_Z2_LINKPOINTERERR 0x6U // Link Pointer Error
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#define DCSM_O_Z2_CSMKEY0 0x10U // Zone 2 CSM Key 0
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#define DCSM_O_Z2_CSMKEY1 0x12U // Zone 2 CSM Key 1
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#define DCSM_O_Z2_CSMKEY2 0x14U // Zone 2 CSM Key 2
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#define DCSM_O_Z2_CSMKEY3 0x16U // Zone 2 CSM Key 3
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#define DCSM_O_Z2_CR 0x19U // Zone 2 CSM Control Register
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#define DCSM_O_Z2_GRABSECTR 0x1AU // Zone 2 Grab Flash Sectors Register
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#define DCSM_O_Z2_GRABRAMR 0x1CU // Zone 2 Grab RAM Blocks Register
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#define DCSM_O_Z2_EXEONLYSECTR 0x1EU // Zone 2 Flash Execute_Only Sector Register
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#define DCSM_O_Z2_EXEONLYRAMR 0x20U // Zone 2 RAM Execute_Only Block Register
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#define DCSM_O_FLSEM 0x0U // Flash Wrapper Semaphore Register
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#define DCSM_O_SECTSTAT 0x2U // Sectors Status Register
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#define DCSM_O_RAMSTAT 0x4U // RAM Status Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the Z1_LINKPOINTER register
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//
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//*************************************************************************************************
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#define DCSM_Z1_LINKPOINTER_LINKPOINTER_S 0U
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#define DCSM_Z1_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone1 LINK Pointer.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the Z1_OTPSECLOCK register
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//
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//*************************************************************************************************
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#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_S 4U
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#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone1 Password Lock.
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#define DCSM_Z1_OTPSECLOCK_CRCLOCK_S 8U
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#define DCSM_Z1_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone1 CRC Lock.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the Z1_BOOTCTRL register
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//
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//*************************************************************************************************
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#define DCSM_Z1_BOOTCTRL_KEY_S 0U
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#define DCSM_Z1_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key
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#define DCSM_Z1_BOOTCTRL_BMODE_S 8U
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#define DCSM_Z1_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode
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#define DCSM_Z1_BOOTCTRL_BOOTPIN0_S 16U
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#define DCSM_Z1_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping
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#define DCSM_Z1_BOOTCTRL_BOOTPIN1_S 24U
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#define DCSM_Z1_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the Z1_CR register
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//
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//*************************************************************************************************
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#define DCSM_Z1_CR_ALLZERO 0x8U // CSMPSWD All Zeros
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#define DCSM_Z1_CR_ALLONE 0x10U // CSMPSWD All Ones
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#define DCSM_Z1_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY
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#define DCSM_Z1_CR_ARMED 0x40U // CSM Armed
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#define DCSM_Z1_CR_FORCESEC 0x8000U // Force Secure
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the Z1_GRABSECTR register
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//
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//*************************************************************************************************
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#define DCSM_Z1_GRABSECTR_GRAB_SECTA_S 0U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A
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#define DCSM_Z1_GRABSECTR_GRAB_SECTB_S 2U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B
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#define DCSM_Z1_GRABSECTR_GRAB_SECTC_S 4U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C
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#define DCSM_Z1_GRABSECTR_GRAB_SECTD_S 6U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D
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#define DCSM_Z1_GRABSECTR_GRAB_SECTE_S 8U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E
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#define DCSM_Z1_GRABSECTR_GRAB_SECTF_S 10U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F
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#define DCSM_Z1_GRABSECTR_GRAB_SECTG_S 12U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G
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#define DCSM_Z1_GRABSECTR_GRAB_SECTH_S 14U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H
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#define DCSM_Z1_GRABSECTR_GRAB_SECTI_S 16U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I
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#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_S 18U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J
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#define DCSM_Z1_GRABSECTR_GRAB_SECTK_S 20U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K
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#define DCSM_Z1_GRABSECTR_GRAB_SECTL_S 22U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L
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#define DCSM_Z1_GRABSECTR_GRAB_SECTM_S 24U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M
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#define DCSM_Z1_GRABSECTR_GRAB_SECTN_S 26U
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#define DCSM_Z1_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the Z1_GRABRAMR register
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//
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//*************************************************************************************************
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#define DCSM_Z1_GRABRAMR_GRAB_RAM0_S 0U
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#define DCSM_Z1_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0
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#define DCSM_Z1_GRABRAMR_GRAB_RAM1_S 2U
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#define DCSM_Z1_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1
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#define DCSM_Z1_GRABRAMR_GRAB_RAM2_S 4U
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#define DCSM_Z1_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2
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#define DCSM_Z1_GRABRAMR_GRAB_RAM3_S 6U
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#define DCSM_Z1_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3
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#define DCSM_Z1_GRABRAMR_GRAB_RAM4_S 8U
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#define DCSM_Z1_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4
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#define DCSM_Z1_GRABRAMR_GRAB_RAM5_S 10U
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#define DCSM_Z1_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5
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#define DCSM_Z1_GRABRAMR_GRAB_RAM6_S 12U
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#define DCSM_Z1_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0
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#define DCSM_Z1_GRABRAMR_GRAB_RAM7_S 14U
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#define DCSM_Z1_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1
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#define DCSM_Z1_GRABRAMR_GRAB_CLA1_S 28U
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#define DCSM_Z1_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the Z1_EXEONLYSECTR register
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//
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//*************************************************************************************************
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M
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#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the Z1_EXEONLYRAMR register
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//
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//*************************************************************************************************
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#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0
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#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1
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#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2
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#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3
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#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4
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#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5
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#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0
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#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the Z2_LINKPOINTER register
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//
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//*************************************************************************************************
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#define DCSM_Z2_LINKPOINTER_LINKPOINTER_S 0U
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#define DCSM_Z2_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone2 LINK Pointer.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the Z2_OTPSECLOCK register
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//
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//*************************************************************************************************
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#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_S 4U
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#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone2 Password Lock.
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#define DCSM_Z2_OTPSECLOCK_CRCLOCK_S 8U
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#define DCSM_Z2_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone2 CRC Lock.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the Z2_BOOTCTRL register
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//
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//*************************************************************************************************
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#define DCSM_Z2_BOOTCTRL_KEY_S 0U
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#define DCSM_Z2_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key
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#define DCSM_Z2_BOOTCTRL_BMODE_S 8U
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#define DCSM_Z2_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode
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#define DCSM_Z2_BOOTCTRL_BOOTPIN0_S 16U
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#define DCSM_Z2_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping
|
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#define DCSM_Z2_BOOTCTRL_BOOTPIN1_S 24U
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#define DCSM_Z2_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping
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//*************************************************************************************************
|
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//
|
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// The following are defines for the bit fields in the Z2_CR register
|
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//
|
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//*************************************************************************************************
|
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#define DCSM_Z2_CR_ALLZERO 0x8U // CSMPSWD All Zeros
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#define DCSM_Z2_CR_ALLONE 0x10U // CSMPSWD All Ones
|
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#define DCSM_Z2_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY
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#define DCSM_Z2_CR_ARMED 0x40U // CSM Armed
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#define DCSM_Z2_CR_FORCESEC 0x8000U // Force Secure
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//*************************************************************************************************
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//
|
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// The following are defines for the bit fields in the Z2_GRABSECTR register
|
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//
|
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//*************************************************************************************************
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTA_S 0U
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#define DCSM_Z2_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A
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#define DCSM_Z2_GRABSECTR_GRAB_SECTB_S 2U
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#define DCSM_Z2_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTC_S 4U
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#define DCSM_Z2_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C
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#define DCSM_Z2_GRABSECTR_GRAB_SECTD_S 6U
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#define DCSM_Z2_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D
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#define DCSM_Z2_GRABSECTR_GRAB_SECTE_S 8U
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#define DCSM_Z2_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTF_S 10U
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#define DCSM_Z2_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F
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#define DCSM_Z2_GRABSECTR_GRAB_SECTG_S 12U
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTH_S 14U
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#define DCSM_Z2_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTI_S 16U
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_S 18U
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTK_S 20U
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTL_S 22U
|
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|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTM_S 24U
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M
|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTN_S 26U
|
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|
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#define DCSM_Z2_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N
|
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|
|
|
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|
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//*************************************************************************************************
|
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|
|
//
|
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|
|
// The following are defines for the bit fields in the Z2_GRABRAMR register
|
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|
|
//
|
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|
|
//*************************************************************************************************
|
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|
|
#define DCSM_Z2_GRABRAMR_GRAB_RAM0_S 0U
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM1_S 2U
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM2_S 4U
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM3_S 6U
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM4_S 8U
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM5_S 10U
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5
|
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|
|
#define DCSM_Z2_GRABRAMR_GRAB_RAM6_S 12U
|
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|
|
#define DCSM_Z2_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0
|
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|
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#define DCSM_Z2_GRABRAMR_GRAB_RAM7_S 14U
|
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|
|
#define DCSM_Z2_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1
|
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|
|
#define DCSM_Z2_GRABRAMR_GRAB_CLA1_S 28U
|
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|
|
#define DCSM_Z2_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1
|
||
|
|
|
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|
|
//*************************************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the Z2_EXEONLYSECTR register
|
||
|
|
//
|
||
|
|
//*************************************************************************************************
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A
|
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|
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#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M
|
||
|
|
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N
|
||
|
|
|
||
|
|
//*************************************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the Z2_EXEONLYRAMR register
|
||
|
|
//
|
||
|
|
//*************************************************************************************************
|
||
|
|
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0
|
||
|
|
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1
|
||
|
|
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2
|
||
|
|
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3
|
||
|
|
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4
|
||
|
|
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5
|
||
|
|
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0
|
||
|
|
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1
|
||
|
|
|
||
|
|
|
||
|
|
//*************************************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the FLSEM register
|
||
|
|
//
|
||
|
|
//*************************************************************************************************
|
||
|
|
#define DCSM_FLSEM_SEM_S 0U
|
||
|
|
#define DCSM_FLSEM_SEM_M 0x3U // Flash Semaphore Bit
|
||
|
|
#define DCSM_FLSEM_KEY_S 8U
|
||
|
|
#define DCSM_FLSEM_KEY_M 0xFF00U // Semaphore Key
|
||
|
|
|
||
|
|
//*************************************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SECTSTAT register
|
||
|
|
//
|
||
|
|
//*************************************************************************************************
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTA_S 0U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTA_M 0x3U // Zone Status Flash Sector A
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTB_S 2U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTB_M 0xCU // Zone Status Flash Sector B
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTC_S 4U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTC_M 0x30U // Zone Status Flash Sector C
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTD_S 6U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTD_M 0xC0U // Zone Status Flash Sector D
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTE_S 8U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTE_M 0x300U // Zone Status Flash Sector E
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTF_S 10U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTF_M 0xC00U // Zone Status Flash Sector F
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTG_S 12U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTG_M 0x3000U // Zone Status Flash Sector G
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTH_S 14U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTH_M 0xC000U // Zone Status Flash Sector H
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTI_S 16U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTI_M 0x30000U // Zone Status Flash Sector I
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTJ_S 18U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTJ_M 0xC0000U // Zone Status Flash Sector J
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTK_S 20U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTK_M 0x300000U // Zone Status Flash Sector K
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTL_S 22U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTL_M 0xC00000U // Zone Status Flash Sector L
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTM_S 24U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTM_M 0x3000000U // Zone Status Flash Sector M
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTN_S 26U
|
||
|
|
#define DCSM_SECTSTAT_STATUS_SECTN_M 0xC000000U // Zone Status Flash Sector N
|
||
|
|
|
||
|
|
//*************************************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the RAMSTAT register
|
||
|
|
//
|
||
|
|
//*************************************************************************************************
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM0_S 0U
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM0_M 0x3U // Zone Status RAM LS0
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM1_S 2U
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM1_M 0xCU // Zone Status RAM LS1
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM2_S 4U
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM2_M 0x30U // Zone Status RAM LS2
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM3_S 6U
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM3_M 0xC0U // Zone Status RAM LS3
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM4_S 8U
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM4_M 0x300U // Zone Status RAM LS4
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM5_S 10U
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM5_M 0xC00U // Zone Status RAM LS5
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM6_S 12U
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM6_M 0x3000U // Zone Status RAM D0
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM7_S 14U
|
||
|
|
#define DCSM_RAMSTAT_STATUS_RAM7_M 0xC000U // Zone Status RAM D1
|
||
|
|
#define DCSM_RAMSTAT_STATUS_CLA1_S 28U
|
||
|
|
#define DCSM_RAMSTAT_STATUS_CLA1_M 0x30000000U // Zone Status CLA1
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|