285 lines
14 KiB
C
285 lines
14 KiB
C
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//###########################################################################
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//
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// FILE: hw_mcbsp.h
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//
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// TITLE: Definitions for the MCBSP registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_MCBSP_H
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#define HW_MCBSP_H
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//*************************************************************************************************
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//
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// The following are defines for the MCBSP register offsets
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//
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//*************************************************************************************************
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#define MCBSP_O_DRR2 0x0U // Data receive register bits 31-16
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#define MCBSP_O_DRR1 0x1U // Data receive register bits 15-0
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#define MCBSP_O_DXR2 0x2U // Data transmit register bits 31-16
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#define MCBSP_O_DXR1 0x3U // Data transmit register bits 15-0
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#define MCBSP_O_SPCR2 0x4U // Serial port control register 2
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#define MCBSP_O_SPCR1 0x5U // Serial port control register 1
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#define MCBSP_O_RCR2 0x6U // Receive Control register 2
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#define MCBSP_O_RCR1 0x7U // Receive Control register 1
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#define MCBSP_O_XCR2 0x8U // Transmit Control register 2
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#define MCBSP_O_XCR1 0x9U // Transmit Control register 1
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#define MCBSP_O_SRGR2 0xAU // Sample rate generator register 2
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#define MCBSP_O_SRGR1 0xBU // Sample rate generator register 1
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#define MCBSP_O_MCR2 0xCU // Multi-channel control register 2
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#define MCBSP_O_MCR1 0xDU // Multi-channel control register 1
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#define MCBSP_O_RCERA 0xEU // Receive channel enable partition A
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#define MCBSP_O_RCERB 0xFU // Receive channel enable partition B
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#define MCBSP_O_XCERA 0x10U // Transmit channel enable partition A
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#define MCBSP_O_XCERB 0x11U // Transmit channel enable partition B
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#define MCBSP_O_PCR 0x12U // Pin Control register
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#define MCBSP_O_RCERC 0x13U // Receive channel enable partition C
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#define MCBSP_O_RCERD 0x14U // Receive channel enable partition D
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#define MCBSP_O_XCERC 0x15U // Transmit channel enable partition C
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#define MCBSP_O_XCERD 0x16U // Transmit channel enable partition D
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#define MCBSP_O_RCERE 0x17U // Receive channel enable partition E
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#define MCBSP_O_RCERF 0x18U // Receive channel enable partition F
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#define MCBSP_O_XCERE 0x19U // Transmit channel enable partition E
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#define MCBSP_O_XCERF 0x1AU // Transmit channel enable partition F
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#define MCBSP_O_RCERG 0x1BU // Receive channel enable partition G
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#define MCBSP_O_RCERH 0x1CU // Receive channel enable partition H
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#define MCBSP_O_XCERG 0x1DU // Transmit channel enable partition G
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#define MCBSP_O_XCERH 0x1EU // Transmit channel enable partition H
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#define MCBSP_O_MFFINT 0x23U // Interrupt enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DRR2 register
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//
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//*************************************************************************************************
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#define MCBSP_DRR2_HWLB_S 0U
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#define MCBSP_DRR2_HWLB_M 0xFFU // High word low byte
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#define MCBSP_DRR2_HWHB_S 8U
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#define MCBSP_DRR2_HWHB_M 0xFF00U // High word high byte
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DRR1 register
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//
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//*************************************************************************************************
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#define MCBSP_DRR1_LWLB_S 0U
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#define MCBSP_DRR1_LWLB_M 0xFFU // Low word low byte
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#define MCBSP_DRR1_LWHB_S 8U
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#define MCBSP_DRR1_LWHB_M 0xFF00U // Low word high byte
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DXR2 register
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//
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//*************************************************************************************************
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#define MCBSP_DXR2_HWLB_S 0U
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#define MCBSP_DXR2_HWLB_M 0xFFU // High word low byte
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#define MCBSP_DXR2_HWHB_S 8U
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#define MCBSP_DXR2_HWHB_M 0xFF00U // High word high byte
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DXR1 register
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//
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//*************************************************************************************************
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#define MCBSP_DXR1_LWLB_S 0U
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#define MCBSP_DXR1_LWLB_M 0xFFU // Low word low byte
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#define MCBSP_DXR1_LWHB_S 8U
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#define MCBSP_DXR1_LWHB_M 0xFF00U // Low word high byte
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SPCR2 register
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//
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//*************************************************************************************************
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#define MCBSP_SPCR2_XRST 0x1U // Transmitter reset
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#define MCBSP_SPCR2_XRDY 0x2U // Transmitter ready
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#define MCBSP_SPCR2_XEMPTY 0x4U // Transmitter empty
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#define MCBSP_SPCR2_XSYNCERR 0x8U // Transmit sync error INT flag
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#define MCBSP_SPCR2_XINTM_S 4U
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#define MCBSP_SPCR2_XINTM_M 0x30U // Transmit Interupt mode bits
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#define MCBSP_SPCR2_GRST 0x40U // Sample rate generator reset
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#define MCBSP_SPCR2_FRST 0x80U // Frame sync logic reset
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#define MCBSP_SPCR2_SOFT 0x100U // SOFT bit
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#define MCBSP_SPCR2_FREE 0x200U // FREE bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SPCR1 register
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//
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//*************************************************************************************************
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#define MCBSP_SPCR1_RRST 0x1U // Receiver reset
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#define MCBSP_SPCR1_RRDY 0x2U // Receiver ready
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#define MCBSP_SPCR1_RFULL 0x4U // Receiver full
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#define MCBSP_SPCR1_RSYNCERR 0x8U // Receive sync error INT flag
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#define MCBSP_SPCR1_RINTM_S 4U
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#define MCBSP_SPCR1_RINTM_M 0x30U // Receive Interupt mode bits
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#define MCBSP_SPCR1_DXENA 0x80U // DX delay enable
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#define MCBSP_SPCR1_CLKSTP_S 11U
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#define MCBSP_SPCR1_CLKSTP_M 0x1800U // Clock stop mode
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#define MCBSP_SPCR1_RJUST_S 13U
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#define MCBSP_SPCR1_RJUST_M 0x6000U // Rx sign extension and justification mode
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#define MCBSP_SPCR1_DLB 0x8000U // Digital loopback
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the RCR2 register
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//
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//*************************************************************************************************
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#define MCBSP_RCR2_RDATDLY_S 0U
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#define MCBSP_RCR2_RDATDLY_M 0x3U // Receive data delay
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#define MCBSP_RCR2_RFIG 0x4U // Receive frame sync ignore
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#define MCBSP_RCR2_RCOMPAND_S 3U
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#define MCBSP_RCR2_RCOMPAND_M 0x18U // Receive Companding Mode selects
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#define MCBSP_RCR2_RWDLEN2_S 5U
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#define MCBSP_RCR2_RWDLEN2_M 0xE0U // Receive word length 2
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#define MCBSP_RCR2_RFRLEN2_S 8U
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#define MCBSP_RCR2_RFRLEN2_M 0x7F00U // Receive Frame length 2
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#define MCBSP_RCR2_RPHASE 0x8000U // Receive Phase
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the RCR1 register
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//
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//*************************************************************************************************
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#define MCBSP_RCR1_RWDLEN1_S 5U
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#define MCBSP_RCR1_RWDLEN1_M 0xE0U // Receive word length 1
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#define MCBSP_RCR1_RFRLEN1_S 8U
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#define MCBSP_RCR1_RFRLEN1_M 0x7F00U // Receive Frame length 1
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the XCR2 register
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//
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//*************************************************************************************************
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#define MCBSP_XCR2_XDATDLY_S 0U
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#define MCBSP_XCR2_XDATDLY_M 0x3U // Transmit data delay
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#define MCBSP_XCR2_XFIG 0x4U // Transmit frame sync ignore
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#define MCBSP_XCR2_XCOMPAND_S 3U
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#define MCBSP_XCR2_XCOMPAND_M 0x18U // Transmit Companding Mode selects
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#define MCBSP_XCR2_XWDLEN2_S 5U
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#define MCBSP_XCR2_XWDLEN2_M 0xE0U // Transmit word length 2
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#define MCBSP_XCR2_XFRLEN2_S 8U
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#define MCBSP_XCR2_XFRLEN2_M 0x7F00U // Transmit Frame length 2
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#define MCBSP_XCR2_XPHASE 0x8000U // Transmit Phase
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the XCR1 register
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//
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//*************************************************************************************************
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#define MCBSP_XCR1_XWDLEN1_S 5U
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#define MCBSP_XCR1_XWDLEN1_M 0xE0U // Transmit word length 1
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#define MCBSP_XCR1_XFRLEN1_S 8U
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#define MCBSP_XCR1_XFRLEN1_M 0x7F00U // Transmit Frame length 1
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SRGR2 register
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//
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//*************************************************************************************************
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#define MCBSP_SRGR2_FPER_S 0U
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#define MCBSP_SRGR2_FPER_M 0xFFFU // Frame-sync period
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#define MCBSP_SRGR2_FSGM 0x1000U // Frame sync generator mode
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#define MCBSP_SRGR2_CLKSM 0x2000U // Sample rate generator mode
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#define MCBSP_SRGR2_GSYNC 0x8000U // CLKG sync
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SRGR1 register
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//
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//*************************************************************************************************
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#define MCBSP_SRGR1_CLKGDV_S 0U
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#define MCBSP_SRGR1_CLKGDV_M 0xFFU // CLKG divider
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#define MCBSP_SRGR1_FWID_S 8U
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#define MCBSP_SRGR1_FWID_M 0xFF00U // Frame width
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MCR2 register
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//
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//*************************************************************************************************
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#define MCBSP_MCR2_XMCM_S 0U
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#define MCBSP_MCR2_XMCM_M 0x3U // Transmit data delay
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#define MCBSP_MCR2_XCBLK_S 2U
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#define MCBSP_MCR2_XCBLK_M 0x1CU // Transmit frame sync ignore
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#define MCBSP_MCR2_XPABLK_S 5U
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#define MCBSP_MCR2_XPABLK_M 0x60U // Transmit Companding Mode selects
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#define MCBSP_MCR2_XPBBLK_S 7U
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#define MCBSP_MCR2_XPBBLK_M 0x180U // Transmit word length 2
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#define MCBSP_MCR2_XMCME 0x200U // Transmit Frame length 2
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MCR1 register
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//
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//*************************************************************************************************
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#define MCBSP_MCR1_RMCM 0x1U // Receive multichannel mode
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#define MCBSP_MCR1_RCBLK_S 2U
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#define MCBSP_MCR1_RCBLK_M 0x1CU // eceive current block
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#define MCBSP_MCR1_RPABLK_S 5U
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#define MCBSP_MCR1_RPABLK_M 0x60U // Receive partition A Block
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#define MCBSP_MCR1_RPBBLK_S 7U
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#define MCBSP_MCR1_RPBBLK_M 0x180U // Receive partition B Block
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#define MCBSP_MCR1_RMCME 0x200U // Receive multi-channel enhance mode
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the PCR register
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//
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//*************************************************************************************************
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#define MCBSP_PCR_CLKRP 0x1U // Receive Clock polarity
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#define MCBSP_PCR_CLKXP 0x2U // Transmit clock polarity
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#define MCBSP_PCR_FSRP 0x4U // Receive Frame synchronization polarity
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#define MCBSP_PCR_FSXP 0x8U // Transmit Frame synchronization polarity
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#define MCBSP_PCR_SCLKME 0x80U // Sample clock mode selection
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#define MCBSP_PCR_CLKRM 0x100U // Receiver Clock Mode
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#define MCBSP_PCR_CLKXM 0x200U // Transmit Clock Mode.
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#define MCBSP_PCR_FSRM 0x400U // Receive Frame Synchronization Mode
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#define MCBSP_PCR_FSXM 0x800U // Transmit Frame Synchronization Mode
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MFFINT register
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//
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//*************************************************************************************************
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#define MCBSP_MFFINT_XINT 0x1U // Enable for Receive Interrupt
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#define MCBSP_MFFINT_RINT 0x4U // Enable for transmit Interrupt
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#endif
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