133 lines
6.8 KiB
C
133 lines
6.8 KiB
C
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//###########################################################################
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//
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// FILE: hw_nmi.h
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//
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// TITLE: Definitions for the NMI registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_NMI_H
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#define HW_NMI_H
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//*************************************************************************************************
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//
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// The following are defines for the NMI register offsets
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//
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//*************************************************************************************************
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#define NMI_O_CFG 0x0U // NMI Configuration Register
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#define NMI_O_FLG 0x1U // NMI Flag Register (XRSn Clear)
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#define NMI_O_FLGCLR 0x2U // NMI Flag Clear Register
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#define NMI_O_FLGFRC 0x3U // NMI Flag Force Register
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#define NMI_O_WDCNT 0x4U // NMI Watchdog Counter Register
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#define NMI_O_WDPRD 0x5U // NMI Watchdog Period Register
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#define NMI_O_SHDFLG 0x6U // NMI Shadow Flag Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the NMICFG register
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//
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//*************************************************************************************************
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#define NMI_CFG_NMIE 0x1U // Global NMI Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the NMIFLG register
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//
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//*************************************************************************************************
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#define NMI_FLG_NMIINT 0x1U // NMI Interrupt Flag
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#define NMI_FLG_CLOCKFAIL 0x2U // Clock Fail Interrupt Flag
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#define NMI_FLG_RAMUNCERR 0x4U // RAM Uncorrectable Error NMI Flag
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#define NMI_FLG_FLUNCERR 0x8U // Flash Uncorrectable Error NMI Flag
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#define NMI_FLG_CPU1HWBISTERR 0x10U // HW BIST Error NMI Flag
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#define NMI_FLG_CPU2HWBISTERR 0x20U // HW BIST Error NMI Flag
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#define NMI_FLG_PIEVECTERR 0x40U // PIE Vector Fetch Error Flag
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#define NMI_FLG_CLBNMI 0x100U // Configurable Logic Block NMI Flag
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#define NMI_FLG_CPU2WDRSN 0x200U // CPU2 WDRSn Reset Indication Flag
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#define NMI_FLG_CPU2NMIWDRSN 0x400U // CPU2 NMIWDRSn Reset Indication Flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the NMIFLGCLR register
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//
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//*************************************************************************************************
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#define NMI_FLGCLR_NMIINT 0x1U // NMIINT Flag Clear
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#define NMI_FLGCLR_CLOCKFAIL 0x2U // CLOCKFAIL Flag Clear
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#define NMI_FLGCLR_RAMUNCERR 0x4U // RAMUNCERR Flag Clear
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#define NMI_FLGCLR_FLUNCERR 0x8U // FLUNCERR Flag Clear
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#define NMI_FLGCLR_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Clear
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#define NMI_FLGCLR_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Clear
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#define NMI_FLGCLR_PIEVECTERR 0x40U // PIEVECTERR Flag Clear
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#define NMI_FLGCLR_CLBNMI 0x100U // CLBNMI Flag Clear
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#define NMI_FLGCLR_CPU2WDRSN 0x200U // CPU2WDRSn Flag Clear
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#define NMI_FLGCLR_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Clear
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#define NMI_FLGCLR_OVF 0x800U // OVF Flag Clear
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the NMIFLGFRC register
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//
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//*************************************************************************************************
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#define NMI_FLGFRC_CLOCKFAIL 0x2U // CLOCKFAIL Flag Force
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#define NMI_FLGFRC_RAMUNCERR 0x4U // RAMUNCERR Flag Force
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#define NMI_FLGFRC_FLUNCERR 0x8U // FLUNCERR Flag Force
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#define NMI_FLGFRC_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Force
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#define NMI_FLGFRC_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Force
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#define NMI_FLGFRC_PIEVECTERR 0x40U // PIEVECTERR Flag Force
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#define NMI_FLGFRC_CLBNMI 0x100U // CLBNMI Flag Force
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#define NMI_FLGFRC_CPU2WDRSN 0x200U // CPU2WDRSn Flag Force
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#define NMI_FLGFRC_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Force
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#define NMI_FLGFRC_OVF 0x800U // OVF Flag Force
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the NMISHDFLG register
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//
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//*************************************************************************************************
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#define NMI_SHDFLG_CLOCKFAIL 0x2U // Shadow CLOCKFAIL Flag
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#define NMI_SHDFLG_RAMUNCERR 0x4U // Shadow RAMUNCERR Flag
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#define NMI_SHDFLG_FLUNCERR 0x8U // Shadow FLUNCERR Flag
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#define NMI_SHDFLG_CPU1HWBISTERR 0x10U // Shadow CPU1HWBISTERR Flag
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#define NMI_SHDFLG_CPU2HWBISTERR 0x20U // Shadow CPU2HWBISTERR Flag
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#define NMI_SHDFLG_PIEVECTERR 0x40U // Shadow PIEVECTERR Flag
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#define NMI_SHDFLG_CLBNMI 0x100U // Shadow CLBNMI Flag
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#define NMI_SHDFLG_CPU2WDRSN 0x200U // Shadow CPU2WDRSn Flag
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#define NMI_SHDFLG_CPU2NMIWDRSN 0x400U // Shadow CPU2NMIWDRSn Flag
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#define NMI_SHDFLG_OVF 0x800U // Shadow OVF Flag
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#endif
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