208 lines
9.9 KiB
C
208 lines
9.9 KiB
C
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//###########################################################################
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//
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// FILE: hw_sci.h
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//
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// TITLE: Definitions for the SCI registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_SCI_H
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#define HW_SCI_H
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//*************************************************************************************************
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//
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// The following are defines for the SCI register offsets
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//
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//*************************************************************************************************
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#define SCI_O_CCR 0x0U // Communications control register
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#define SCI_O_CTL1 0x1U // Control register 1
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#define SCI_O_HBAUD 0x2U // Baud rate (high) register
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#define SCI_O_LBAUD 0x3U // Baud rate (low) register
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#define SCI_O_CTL2 0x4U // Control register 2
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#define SCI_O_RXST 0x5U // Receive status register
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#define SCI_O_RXEMU 0x6U // Receive emulation buffer register
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#define SCI_O_RXBUF 0x7U // Receive data buffer
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#define SCI_O_TXBUF 0x9U // Transmit data buffer
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#define SCI_O_FFTX 0xAU // FIFO transmit register
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#define SCI_O_FFRX 0xBU // FIFO receive register
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#define SCI_O_FFCT 0xCU // FIFO control register
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#define SCI_O_PRI 0xFU // SCI priority control
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCICCR register
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//
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//*************************************************************************************************
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#define SCI_CCR_SCICHAR_S 0U
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#define SCI_CCR_SCICHAR_M 0x7U // Character length control
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#define SCI_CCR_ADDRIDLE_MODE 0x8U // ADDR/IDLE Mode control
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#define SCI_CCR_LOOPBKENA 0x10U // Loop Back enable
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#define SCI_CCR_PARITYENA 0x20U // Parity enable
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#define SCI_CCR_PARITY 0x40U // Even or Odd Parity
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#define SCI_CCR_STOPBITS 0x80U // Number of Stop Bits
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCICTL1 register
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//
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//*************************************************************************************************
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#define SCI_CTL1_RXENA 0x1U // SCI receiver enable
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#define SCI_CTL1_TXENA 0x2U // SCI transmitter enable
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#define SCI_CTL1_SLEEP 0x4U // SCI sleep
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#define SCI_CTL1_TXWAKE 0x8U // Transmitter wakeup method
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#define SCI_CTL1_SWRESET 0x20U // Software reset
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#define SCI_CTL1_RXERRINTENA 0x40U // Receive error interrupt enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCIHBAUD register
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//
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//*************************************************************************************************
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#define SCI_HBAUD_BAUD_S 0U
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#define SCI_HBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCIHBAUD
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCILBAUD register
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//
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//*************************************************************************************************
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#define SCI_LBAUD_BAUD_S 0U
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#define SCI_LBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCILBAUD
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCICTL2 register
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//
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//*************************************************************************************************
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#define SCI_CTL2_TXINTENA 0x1U // Transmit __interrupt enable
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#define SCI_CTL2_RXBKINTENA 0x2U // Receiver-buffer break enable
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#define SCI_CTL2_TXEMPTY 0x40U // Transmitter empty flag
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#define SCI_CTL2_TXRDY 0x80U // Transmitter ready flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCIRXST register
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//
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//*************************************************************************************************
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#define SCI_RXST_RXWAKE 0x2U // Receiver wakeup detect flag
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#define SCI_RXST_PE 0x4U // Parity error flag
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#define SCI_RXST_OE 0x8U // Overrun error flag
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#define SCI_RXST_FE 0x10U // Framing error flag
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#define SCI_RXST_BRKDT 0x20U // Break-detect flag
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#define SCI_RXST_RXRDY 0x40U // Receiver ready flag
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#define SCI_RXST_RXERROR 0x80U // Receiver error flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCIRXEMU register
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//
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//*************************************************************************************************
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#define SCI_RXEMU_ERXDT_S 0U
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#define SCI_RXEMU_ERXDT_M 0xFFU // Receive emulation buffer data
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCIRXBUF register
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//
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//*************************************************************************************************
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#define SCI_RXBUF_SAR_S 0U
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#define SCI_RXBUF_SAR_M 0xFFU // Receive Character bits
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#define SCI_RXBUF_SCIFFPE 0x4000U // Receiver error flag
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#define SCI_RXBUF_SCIFFFE 0x8000U // Receiver error flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCITXBUF register
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//
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//*************************************************************************************************
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#define SCI_TXBUF_TXDT_S 0U
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#define SCI_TXBUF_TXDT_M 0xFFU // Transmit data buffer
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCIFFTX register
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//
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//*************************************************************************************************
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#define SCI_FFTX_TXFFIL_S 0U
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#define SCI_FFTX_TXFFIL_M 0x1FU // Interrupt level
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#define SCI_FFTX_TXFFIENA 0x20U // Interrupt enable
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#define SCI_FFTX_TXFFINTCLR 0x40U // Clear INT flag
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#define SCI_FFTX_TXFFINT 0x80U // INT flag
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#define SCI_FFTX_TXFFST_S 8U
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#define SCI_FFTX_TXFFST_M 0x1F00U // FIFO status
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#define SCI_FFTX_TXFIFORESET 0x2000U // FIFO reset
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#define SCI_FFTX_SCIFFENA 0x4000U // Enhancement enable
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#define SCI_FFTX_SCIRST 0x8000U // SCI reset rx/tx channels
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCIFFRX register
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//
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//*************************************************************************************************
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#define SCI_FFRX_RXFFIL_S 0U
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#define SCI_FFRX_RXFFIL_M 0x1FU // Interrupt level
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#define SCI_FFRX_RXFFIENA 0x20U // Interrupt enable
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#define SCI_FFRX_RXFFINTCLR 0x40U // Clear INT flag
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#define SCI_FFRX_RXFFINT 0x80U // INT flag
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#define SCI_FFRX_RXFFST_S 8U
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#define SCI_FFRX_RXFFST_M 0x1F00U // FIFO status
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#define SCI_FFRX_RXFIFORESET 0x2000U // FIFO reset
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#define SCI_FFRX_RXFFOVRCLR 0x4000U // Clear overflow
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#define SCI_FFRX_RXFFOVF 0x8000U // FIFO overflow
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCIFFCT register
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//
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//*************************************************************************************************
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#define SCI_FFCT_FFTXDLY_S 0U
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#define SCI_FFCT_FFTXDLY_M 0xFFU // FIFO transmit delay
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#define SCI_FFCT_CDC 0x2000U // Auto baud mode enable
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#define SCI_FFCT_ABDCLR 0x4000U // Auto baud clear
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#define SCI_FFCT_ABD 0x8000U // Auto baud detect
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCIPRI register
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//
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//*************************************************************************************************
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#define SCI_PRI_FREESOFT_S 3U
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#define SCI_PRI_FREESOFT_M 0x18U // Emulation modes
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#endif
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